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ADC081500High Performance, Low Power, 8-Bit, 1.5 GSPS A/DConverterGeneral DescriptionThe ADC081500 is a low power, high performance CMOSanalog-to-digital converter that digitizes signals to 8 bitsresolution at sample rates up to 1.7 GSPS. Consuming atypical 1.2 W at 1.5 GSPS from a single 1.9 Volt supply, thisdevice is guaranteed to have no missing codes over the fulloperating temperature range. The unique folding and inter-polating architecture, the fully differential comparator design,the innovative design of the internal sample-and-hold ampli-fier and the self-calibration scheme enable a very flat re-sponse of all dynamic parameters beyond Nyquist, produc-ing a high 7.3 ENOB with a 748 MHz input signal and a 1.5GHz sample rate while providing a 10-18 B.E.R. Outputformatting is offset binary and the LVDS digital outputs arecompliant with IEEE 1596.3-1996, with the exception of anadjustable output offset voltage between 0.8V and 1.2V.

The converter output has a 1:2 demultiplexer that feeds twoLVDS buses and reduces the output data rate on each bus toone-half the sample rate.

The converter typically consumes less than 3.5 mW in thePower Down Mode and is available in a 128-lead, thermallyenhanced exposed pad LQFP and operates over the Indus-trial (-40˚C ≤ TA ≤ +85˚C) temperature range.

Featuresn Internal Sample-and-Holdn Single +1.9V ±0.1V Operationn Choice of SDR or DDR output clockingn Multiple ADC Synchronization Capabilityn Guaranteed No Missing Codesn Serial Interface for Extended Controln Fine Adjustment of Input Full-Scale Range and Offsetn Duty Cycle Corrected Sample Clock

Key Specificationsn Resolution 8 Bitsn Max Conversion Rate 1.5 GSPS (min)n Bit Error Rate 10-18 (typ)n ENOB @ 748 MHz Input 7.3 Bits (typ)n DNL ±0.15 LSB (typ)n Power Consumption

— Operating 1.2 W (typ)— Power Down Mode 3.5 mW (typ)

Applicationsn Direct RF Down Conversionn Digital Oscilloscopesn Satellite Set-top boxesn Communications Systemsn Test Instrumentation

Block Diagram

20153153

March 2006A

DC

081500H

ighP

erformance,Low

Pow

er,8-Bit,1.5

GS

PS

A/D

Converter

© 2006 National Semiconductor Corporation DS201531 www.national.com

Ordering Information

Industrial Temperature Range(-40˚C < TA < +85˚C)

NS Package

ADC081500CIYB 128-Pin Exposed Pad LQFP

ADC081500EVAL Evaluation Board

Pin Configuration

20153101

* Exposed pad on back of package must be soldered to ground plane to ensure rated performance.

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Pin Descriptions and Equivalent Circuits

Pin Functions

Pin No. Symbol Equivalent Circuit Description

3OutV /SCLK

Output Voltage Amplitude and Serial Interface Clock.Tie this pin high for normal differential DCLK and dataamplitude. Ground this pin for a reduced differentialoutput amplitude and reduced power consumption. SeeSection 1.1.6. When the extended control mode isenabled, this pin functions as the SCLK input whichclocks in the serial data. See Section 1.3

4OutEdge /

DDR /SDATA

DCLK Edge Select, Double Data Rate Enable andSerial Data Input. This input sets the output edge ofDCLK+ at which the output data transitions. (SeeSection 1.1.5.2). When this pin is floating or connectedto 1/2 the supply voltage, DDR clocking is enabled.When the extended control mode is enabled, this pinfunctions as the (SDATA) input. See Section 1.2 fordetails on the extended control mode.

15 DCLK_RSTDCLK Reset. A positive pulse on this pin is used toreset and synchronize the DCLK outputs of multipleconverters. See Section 1.5 for detailed description.

26 PDPower Down Pin. A logic high on the PD pin puts thedevice into the Power Down Mode.

30 CAL

Calibration Cycle Initiate. A minimum 80 input clockcycles logic low followed by a minimum of 80 inputclock cycles high on this pin initiates the self calibrationsequence. See Section 2.4.2.

14 FSR/ECE

Full Scale Range Select and Extended Control Enable.In non-extended control mode, a logic low on this pinsets the full-scale differential input range to 650 mVP-P.A logic high on this pin sets the full-scale differentialinput range to 870 mVP-P. See Section 1.1.4. To enablethe extended control mode, whereby the serial interfaceand control registers are employed, allow this pin tofloat or connect it to a voltage equal to VA/2. SeeSection 1.2 for information on the extended controlmode.

127CalDly /

SCS

Calibration Delay and Serial Interface Chip Select. Witha logic high or low on pin 14, this pin functions asCalibration Delay and sets the number of input clockcycles after power up before calibration begins (SeeSection 1.1.1). With pin 14 floating, this pin acts as theenable pin for the serial interface input and the CalDlyvalue becomes "0" (short delay with no provision for along power-up calibration delay).

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Pin Descriptions and Equivalent Circuits (Continued)

Pin Functions


1819

CLK+CLK-

LVDS Clock input pins for the ADC. The differentialclock signal must be a.c. coupled to these pins. Theinput signal is sampled on the falling edge of CLK+.See Section 2.3.

1110

VIN+VIN−

Analog signal inputs to the ADC. The differentialfull-scale input range is 650 mVP-P when the FSR pin islow, or 870 mVP-P when the FSR pin is high.

7 VCMO

Common Mode Voltage. The voltage output at this pinis required to be the common mode input voltage atVIN+ and VIN− when d.c. coupling is used. This pinshould be grounded when a.c. coupling is used at theanalog inputs. This pin is capable of sourcing or sinking100µA. See Section 2.2.

31 VBG Bandgap output voltage capable of 100 µA source/sink.

126 CalRunCalibration Running indication. This pin is at a logichigh when calibration is running.

32 REXTExternal bias resistor connection. Nominal value is3.3k-Ohms (±0.1%) to ground. See Section 1.1.1.

3435

Tdiode_PTdiode_N

Temperature Diode Positive (Anode) and Negative(Cathode) for die temperature measurements. SeeSection 2.6.2.

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Pin Functions


838485868990919293949596100101102103

D7−D7+D6−D6+D5−D5+D4−D4+D3−D3+D2−D2+D1−D1+D0−D0+

The LVDS Data Outputs that are not delayed in theoutput demultiplexer. Compared with the Dd outputs,these outputs represent the later time samples. Theseoutputs should always be terminated with a 100Ωdifferential resistor.

104105106107111112113114115116117118122123124125

Dd7−Dd7+Dd6−Dd6+Dd5−Dd5+Dd4−Dd4+Dd3−Dd3+Dd2−Dd2+Dd1−Dd1+Dd0Dd0

The LVDS Data Outputs that are delayed by one CLKcycle in the output demultiplexer. Compared with the Doutputs, these outputs represent the earlier timesample. These outputs should always be terminatedwith a 100Ω differential resistor.

7980

OR+OR-

Out Of Range output. A differential high at these pinsindicates that the differential input is out of range(outside the range ±325 mV or ±435 mV as defined bythe FSR pin).

8281

DCLK+DCLK-

Differential Clock outputs used to latch the output data.Delayed and non-delayed data outputs are suppliedsynchronous to this signal. This signal is at 1/2 theinput clock rate in SDR mode and at 1/4 the input clockrate in the DDR mode. The DCLK outputs are notactive during a calibration cycle.

2, 5, 8, 13, 16, 17,20, 25, 28, 33, 128

VAAnalog power supply pins. Bypass these pins toground.

40, 51 ,62, 73, 88,99, 110, 121

VDROutput Driver power supply pins. Bypass these pins toDR GND.

1, 6, 9, 12, 21, 24,27, 41

GND Ground return for VA.

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Pin Functions


42, 53, 64, 74, 87,97, 108, 119

DR GND Ground return for VDR.

22, 23, 29, 36-39,43-50, 52, 54-61,63, 65-72, 75-78,

98, 109, 120

NC No Connection. Make no connection to these pins.

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Absolute Maximum Ratings(Notes 1, 2)

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage (VA, VDR) 2.2V

Voltage on Any Input Pin −0.15V to (VA

+0.15V)

Ground Difference|GND - DR GND| 0V to 100 mV

Input Current at Any Pin (Note 3) ±25 mA

Package Input Current (Note 3) ±50 mA

Power Dissipation at TA ≤ 85˚C 2.0 W

ESD Susceptibility (Note 4)Human Body ModelMachine Model

2500V250V

Soldering Temperature, Infrared,10 seconds, (Note 5), (Applies

to standard plated package only) 235˚C

Storage Temperature −65˚C to +150˚C

Operating Ratings (Notes 1, 2)

Ambient Temperature Range −40˚C ≤ TA ≤ +85˚C

Supply Voltage (VA) +1.8V to +2.0V

Driver Supply Voltage (VDR) +1.8V to VA

Analog Input Common ModeVoltage VCMO ±50mV

VIN+, VIN- Voltage Range(Maintaining Common Mode) 200mV to VA

Ground Difference(|GND - DR GND|) 0V

CLK Pins Voltage Range 0V to VA

Differential CLK Amplitude 0.4VP-P to 2.0VP-P

Package Thermal Resistance

Package θJAθJC (Top of

Package)

θJ-PAD

(Thermal

Pad)

128-LeadExposed Pad

LQFP26˚C / W 10˚C / W 2.8˚C / W

Converter Electrical CharacteristicsThe following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN (a.c. coupled) Full Scale Range =differential 870mVP-P, CL = 10 pF, Differential (a.c. coupled) sinewave input clock, fCLK = 1.5 GHz at 0.5VP-P with 50% dutycycle, VBG = Floating, Normal Control Mode, Single Data Rate Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance= 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6,7)

Symbol Parameter ConditionsTypical(Note 8)

Limits(Note 8)

Units(Limits)

STATIC CONVERTER CHARACTERISTICS

INL Integral Non-Linearity (Best fit)DC Coupled, 1MHz Sine WaveOveranged

±0.3 ±0.9 LSB (max)

DNL Differential Non-LinearityDC Coupled, 1MHz Sine WaveOveranged

±0.15 ±0.6 LSB (max)

Resolution with No MissingCodes

8 Bits

VOFF Offset Error -0.45−1.51.0

LSB (min)LSB (max)

VOFF_ADJ Input Offset Adjustment Range Extended Control Mode ±45 mV

PFSE Positive Full-Scale Error (Note 9) −0.6 ±25 mV (max)

NFSE Negative Full-Scale Error (Note 9) −1.31 ±25 mV (max)

FS_ADJ Full-Scale Adjustment Range Extended Control Mode ±20 ±15 %FS

DYNAMIC CONVERTER CHARACTERISTICS

FPBW Full Power Bandwidth 1.7 GHz

B.E.R. Bit Error Rate 10-18 Error/Sample

Gain Flatnessd.c. to 500 MHz ±0.5 dBFS

d.c. to 1 GHz ±1.0 dBFS

ENOB Effective Number of BitsfIN = 373 MHz, VIN = FSR − 0.5 dB 7.4 7.0 Bits (min)

fIN = 748 MHz, VIN = FSR − 0.5 dB 7.3 Bits (min)

SINADSignal-to-Noise Plus DistortionRatio

fIN = 373 MHz, VIN = FSR − 0.5 dB 46.3 43.9 dB (min)

fIN = 748 MHz, VIN = FSR − 0.5 dB 45.4 dB (min)

SNR Signal-to-Noise RatiofIN = 373 MHz, VIN = FSR − 0.5 dB 47 44.5 dB (min)

fIN = 748 MHz, VIN = FSR − 0.5 dB 46.3 dB (min)

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Converter Electrical Characteristics (Continued)

The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN (a.c. coupled) Full Scale Range =differential 870mVP-P, CL = 10 pF, Differential (a.c. coupled) sinewave input clock, fCLK = 1.5 GHz at 0.5VP-P with 50% dutycycle, VBG = Floating, Normal Control Mode, Single Data Rate Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance= 100Ω Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6,7)


Limits(Note 8)

Units(Limits)

DYNAMIC CONVERTER CHARACTERISTICS

THD Total Harmonic DistortionfIN = 373 MHz, VIN = FSR − 0.5 dB -54.5 -47 dB (max)

fIN = 748 MHz, VIN = FSR − 0.5 dB -53 dB (max)

2nd Harm Second Harmonic DistortionfIN = 373 MHz, VIN = FSR − 0.5 dB −60 dB

fIN = 748 MHz, VIN = FSR − 0.5 dB -57 dB

3rd Harm Third Harmonic DistortionfIN = 373 MHz, VIN = FSR − 0.5 dB −62 dB

fIN = 748 MHz, VIN = FSR − 0.5 dB -65 dB

SFDR Spurious-Free dynamic RangefIN = 373 MHz, VIN = FSR − 0.5 dB 56 48.5 dB (min)

fIN = 748 MHz, VIN = FSR − 0.5 dB 53 dB (min)

IMD Intermodulation DistortionfIN1 = 321 MHz, VIN = FSR − 7 dBfIN2 = 326 MHz, VIN = FSR − 7 dB

-50 dB

Out of Range Output Code(In addition to OR Output high)

(VIN+) − (VIN−) > + Full Scale 255

(VIN+) − (VIN−) < − Full Scale 0

ANALOG INPUT AND REFERENCE CHARACTERISTICS

VINFull Scale Analog DifferentialInput Range

FSR pin 14 Low 650570 mVP-P (min)

730 mVP-P (max)

FSR pin 14 High 870790 mVP-P (min)

950 mVP-P (max)

VCMIAnalog Input Common ModeVoltage

VCMOVCMO − 50VCMO + 50

mV (min)mV (max)

CINAnalog Input Capacitance(Notes 10, 11)

Differential 0.02 pF

Each input pin to ground 1.6 pF

RIN Differential Input Resistance 10094 Ω (min)

106 Ω (max)

ANALOG OUTPUT CHARACTERISTICS

VCMO Common Mode Output Voltage 1.260.951.45

V (min)V (max)

TC VCMOCommon Mode Output VoltageTemperature Coefficient

TA = −40˚C to +85˚C 118 ppm/˚C

VCMO_LVLVCMO input threshold to set DCCoupling mode

VA = 1.8V 0.60 V

VA = 2.0V 0.66 V

CLOAD

VCMO

Maximum VCMO loadCapacitance

80 pF

VBGBandgap Reference OutputVoltage

IBG = ±100 µA 1.261.201.33

V (min)V (max)

TC VBGBandgap Reference VoltageTemperature Coefficient

TA = −40˚C to +85˚C,IBG = ±100 µA

28 ppm/˚C

CLOAD

VBG

Maximum Bandgap Referenceload Capacitance

80 pF

TEMPERATURE DIODE CHARACTERISTICS

∆VBE Temperature Diode Voltage

192 µA vs. 12 µA,TJ = 25˚C

71.23 mV

192 µA vs. 12 µA,TJ = 85˚C

85.54 mV

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Limits(Note 8)

Units(Limits)

CLOCK INPUT CHARACTERISTICS

VID Differential Clock Input Level

Sine Wave Clock 0.60.42.0

VP-P (min)VP-P (max)

Square Wave Clock 0.60.42.0

VP-P (min)VP-P (max)

II Input Current VIN = 0 or VIN = VA ±1 µA

CINInput Capacitance(Notes 10, 11)

Differential 0.02 pF

Each input to ground 1.5 pF

DIGITAL CONTROL PIN CHARACTERISTICS

VIH Logic High Input Voltage (Note 12) 0.85 x VA V (min)

VIL Logic Low Input Voltage (Note 12) 0.15 x VA V (max)

CINInput Capacitance(Notes 11, 13)

Each input to ground 1.2 pF

DIGITAL OUTPUT CHARACTERISTICS

VODLVDS Differential OutputVoltage

Measured differentially, OutV = VA,VBG = Floating (Note 15)

710400 mVP-P (min)

920 mVP-P (max)

Measured differentially, OutV =GND, VBG = Floating (Note 15)

510280 mVP-P (min)

720 mVP-P (max)

∆ VO DIFFChange in LVDS Output SwingBetween Logic Levels

±1 mV

VOS Output Offset Voltage VBG = Floating 800 mV

VOS Output Offset Voltage VBG = VA (Note 15) 1200 mV

∆ VOSOutput Offset Voltage ChangeBetween Logic Levels

±1 mV

IOS Output Short Circuit CurrentOutput+ & Output- connected to0.8V

±4 mA

ZO Differential Output Impedance 100 Ohms

VOH CalRun High level output IOH = -400uA (Note 12) 1.65 1.5 V

VOL CalRun Low level output IOH = 400uA (Note 12) 0.15 0.3 V

POWER SUPPLY CHARACTERISTICS

IA Analog Supply CurrentPD = LowPD = High

5241.8

600 mA (max)mA

IDR Output Driver Supply CurrentPD = LowPD = High

1160.012

165 mA (max)mA

PD Power ConsumptionPD = LowPD = High

1.23.5

1.45 W (max)mW

PSRR1D.C. Power Supply RejectionRatio

Change in Full Scale Error withchange in VA from 1.8V to 2.0V

30 dB

PSRR2A.C. Power Supply RejectionRatio

248 MHz, 50mVP-P riding on VA 51 dB

AC ELECTRICAL CHARACTERISTICS

fCLK1Maximum Input ClockFrequency

1.7 1.5 GHz (min)

fCLK2Minimum Input ClockFrequency

200 MHz

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Limits(Note 8)

Units(Limits)


Input Clock Duty Cycle200 MHz ≤ Input clock frequency ≤1.5 GHz (Note 12)

502080

% (min)% (max)

tCL Input Clock Low Time (Note 11) 333 133 ps (min)

tCH Input Clock High Time (Note 11) 333 133 ps (min)

DCLK Duty Cycle (Note 11) 504555

% (min)% (max)

tRS Reset Setup Time (Note 11) 150 ps

tRH Reset Hold Time (Note 11) 250 ps

tSDSynchronizing Edge to DCLKOutput Delay

fCLKIN = 1.5 GHzfCLKIN = 200 MHz

3.533.85

ns

tRPW Reset Pulse Width (Note 11) 4Clock Cycles

(min)

tLHTDifferential Low to HighTransition Time

10% to 90%, CL = 2.5 pF 250 ps

tHLTDifferential High to LowTransition Time

10% to 90%, CL = 2.5 pF 250 ps

tOSK DCLK to Data Output Skew50% of DCLK transition to 50% ofData transition, SDR Modeand DDR Mode, 0˚ DCLK (Note 11)

±50 ps (max)

tSU Data to DCLK Set-Up Time DDR Mode, 90˚ DCLK (Note 11) 1 ns

tH DCLK to Data Hold Time DDR Mode, 90˚ DCLK (Note 11) 1 ns

tAD Sampling (Aperture) DelayInput CLK+ Fall to Acquisition ofData

1.3 ns

tAJ Aperture Jitter 0.4 ps rms

tOD

Input Clock to Data OutputDelay (in addition to PipelineDelay)

50% of Input Clock transition to 50%of Data transition

3.1 ns

Pipeline Delay (Latency)(Notes 11, 14)

D Outputs 13 Input ClockCyclesDd Outputs 14

Over Range Recovery TimeDifferential VIN step from ±1.2V to0V to get accurate conversion

1Input Clock

Cycle

tWUPD low to Rated AccuracyConversion (Wake-Up Time)

500 ns

fSCLK Serial Clock Frequency (Note 11) 100 MHz

tSSUData to Serial Clock SetupTime

(Note 11) 2.5 ns (min)

tSH Data to Serial Clock Hold Time (Note 11) 1 ns (min)

Serial Clock Low Time 4 ns (min)

Serial Clock High Time 4 ns (min)

tCAL Calibration Cycle Time 1.4 x 105 Clock Cycles

tCAL_L CAL Pin Low Time See Figure 9 (Note 11) 80Clock Cycles

(min)

tCAL_H CAL Pin High Time See Figure 9 (Note 11) 80Clock Cycles

(min)

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Limits(Note 8)

Units(Limits)


tCalDlyCalibration delay determined bypin 127

See Section 1.1.1, Figure 9,(Note 11)

225 Clock Cycles(min)

tCalDlyCalibration delay determined bypin 127

See Section 1.1.1, Figure 9,(Note 11)

231 Clock Cycles(max)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute MaximumRatings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications andtest conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics maydegrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin should be limited to25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.This limit is not placed upon the power, ground and digital output pins.

Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.

Note 5: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.

Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.

20153104

Note 7: To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,achieving rated performance requires that the backside exposed pad be well grounded.

Note 8: Typical figures are at TA = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing QualityLevel).

Note 9: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, see SpecificationDefinitions for Gain Error.

Note 10: The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to groundare isolated from the die capacitances by lead and bond wire inductances.

Note 11: This parameter is guaranteed by design and is not tested in production.

Note 12: This parameter is guaranteed by design and/or characterization and is not tested in production.

Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the diecapacitances by lead and bond wire inductances.

Note 14: The ADC081500 converter has two LVDS output buses, which each clock data out at one half the sample rate. The second bus (D0 through D7) has apipeline latency that is one Input Clock cycle less than the latency of the first bus (Dd0 through Dd7).

Note 15: Tying VBG to the supply rail will increase the output offset voltage (VOS) by 400mv (typical), as shown in the VOS specification above. Tying VBG to thesupply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 40mV (typical).

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Specification DefinitionsAPERTURE (SAMPLING) DELAY is that time required afterthe fall of the clock input for the sampling switch to open. TheSample/Hold circuit effectively stops capturing the input sig-nal and goes into the “hold” mode the aperture delay time(tAD) after the input clock goes low.

APERTURE JITTER (tAJ) is the variation in aperture delayfrom sample to sample. Aperture jitter shows up as inputnoise.

Bit Error Rate (B.E.R.) is the probability of error and isdefined as the probable number of errors per unit of timedivided by the number of bits seen in that amount of time. AB.E.R. of 10-18 corresponds to a statistical error in one bitabout every four (4) years.

CLOCK DUTY CYCLE is the ratio of the time that the clockwave form is at a logic high to the total time of one clockperiod.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure ofthe maximum deviation from the ideal step size of 1 LSB.Measured at 1.5 GSPS with a ramp input.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVEBITS) is another method of specifying Signal-to-Noise andDistortion Ratio, or SINAD. ENOB is defined as (SINAD −1.76) / 6.02 and says that the converter is equivalent to aperfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH (FPBW) is a measure of thefrequency at which the reconstructed output fundamentaldrops 3 dB below its low frequency value for a full scaleinput.

GAIN ERROR is the deviation from the ideal slope of thetransfer function. It can be calculated from Offset and Full-Scale Errors:

Pos. Gain Error = Offset Error − Pos. Full-Scale Error

Neg. Gain Error = −(Offset Error − Neg. Full-ScaleError)

Gain Error = Neg. Full-Scale Error − Pos. Full-ScaleError = Pos. Gain Error + Neg. Gain Error

INTEGRAL NON-LINEARITY (INL) is a measure of thedeviation of each individual code from a straight line throughthe input to output transfer function. The deviation of anygiven code from this straight line is measured from thecenter of that code value. The best fit method is used.

INTERMODULATION DISTORTION (IMD) is the creation ofadditional spectral components as a result of two sinusoidalfrequencies being applied to the ADC input at the same time.it is defined as the ratio of the power in the second and thirdorder intermodulation products to the power in one of theoriginal frequencies. IMD is usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has thesmallest value or weight of all bits. This value is

VFS / 2n

where VFS is the differential full-scale amplitude of 650 mVor 870 mV as set by the FSR input and "n" is the ADCresolution in bits, which is 8 for the ADC081500.

LVDS DIFFERENTIAL OUTPUT VOLTAGE (VOD) is theabsolute value of the difference between the VD+ & VD-outputs; each measured with respect to Ground.

LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpointbetween the D+ and D- pins output voltage; i.e., [(VD+) +(VD-)]/2.

MISSING CODES are those output codes that are skippedand will never appear at the ADC outputs. These codescannot be reached with any input value.

MSB (MOST SIGNIFICANT BIT) is the bit that has thelargest value or weight. Its value is one half of full scale.

NEGATIVE FULL-SCALE ERROR (NFSE) is a measure ofhow far the last code transition is from the ideal 1/2 LSBabove a differential −435 mV with the FSR pin high, or 1/2LSB above a differential −325 mV with the FSR pin low. Forthe ADC081500 the reference voltage is assumed to beideal, so this error is a combination of full-scale error andreference voltage error.

OFFSET ERROR (VOFF) is a measure of how far the mid-scale point is from the ideal zero voltage differential input.

Offset Error = Actual Input causing average of 8ksamples to result in an average code of 127.5.

OUTPUT DELAY (tOD) is the time delay (in addition toPipeline Delay) after the falling edge of CLK+ before the dataupdate is present at the output pins.

OVER-RANGE RECOVERY TIME is the time required afterthe differential input voltages goes from ±1.2V to 0V for theconverter to recover and make a conversion with its ratedaccuracy.

PIPELINE DELAY (LATENCY) is the number of input clockcycles between initiation of conversion and when that data ispresented to the output driver stage. New data is available atevery clock cycle, but the data lags the conversion by thePipeline Delay plus the tOD.

POSITIVE FULL-SCALE ERROR (PFSE) is a measure ofhow far the last code transition is from the ideal 1-1/2 LSBbelow a differential +435 mV with the FSR pin high, or 1-1/2LSB below a differential +325 mV with the FSR pin low. Forthe ADC081500 the reference voltage is assumed to beideal, so this error is a combination of full-scale error andreference voltage error.

POWER SUPPLY REJECTION RATIO (PSRR) can be oneof two specifications. PSRR1 (DC PSRR) is the ratio of thechange in full-scale error that results from a power supplyvoltage change from 1.8V to 2.0V. PSRR2 (AC PSRR) is ameasure of how well an a.c. signal riding upon the powersupply is rejected from the output and is measured with a248 MHz, 50 mVP-P signal riding upon the power supply. It isthe ratio of the output amplitude of that signal at the output toits amplitude on the power supply pin. PSRR is expressed indB.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed indB, of the rms value of the input signal at the output to the

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FIGURE 1.

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(Continued)

rms value of the sum of all other spectral components belowone-half the sampling frequency, not including harmonics ord.c.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SI-NAD) is the ratio, expressed in dB, of the rms value of theinput signal at the output to the rms value of all of the otherspectral components below half the input clock frequency,including harmonics but excluding d.c.

SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the differ-ence, expressed in dB, between the rms values of the inputsignal at the output and the peak spurious signal, where aspurious signal is any signal present in the output spectrumthat is not present at the input, excluding d.c.

TOTAL HARMONIC DISTORTION (THD) is the ratio ex-pressed in dB, of the rms total of the first nine harmoniclevels at the output to the level of the fundamental at theoutput. THD is calculated as

where Af1 is the RMS power of the fundamental (output)frequency and Af2 through Af10 are the RMS power of thefirst 9 harmonic frequencies in the output spectrum.

– Second Harmonic Distortion (2nd Harm) is the differ-ence, expressed in dB, between the RMS power in the inputfrequency seen at the output and the power in its 2ndharmonic level at the output.

– Third Harmonic Distortion (3rd Harm) is the differenceexpressed in dB between the RMS power in the input fre-quency seen at the output and the power in its 3rd harmoniclevel at the output.

Transfer Characteristic

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FIGURE 2. Input / Output Transfer Characteristic

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Timing Diagrams

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FIGURE 3. ADC081500 Timing — SDR Clocking

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FIGURE 4. ADC081500 Timing — DDR Clocking

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Timing Diagrams (Continued)

20153119

FIGURE 5. Serial Interface Timing

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FIGURE 6. Clock Reset Timing in DDR Mode

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FIGURE 7. Clock Reset Timing in SDR Mode with OUTEDGE Low

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Timing Diagrams (Continued)

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FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE High

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FIGURE 9. Self Calibration and On-Command Calibration Timing

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Typical Performance Characteristics VA = VDR = 1.9V, FCLK = 1500MHz, TA = 25˚C unless other-wise stated.

INL vs. CODE INL vs. TEMPERATURE

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DNL vs. CODE DNL vs. TEMPERATURE

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POWER DISSIPATION vs. SAMPLE RATE ENOB vs. TEMPERATURE

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Typical Performance Characteristics VA = VDR = 1.9V, FCLK = 1500MHz, TA = 25˚C unlessotherwise stated. (Continued)

ENOB vs. SUPPLY VOLTAGE ENOB vs. SAMPLE RATE

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ENOB vs. INPUT FREQUENCY SNR vs. TEMPERATURE

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SNR vs. SUPPLY VOLTAGE SNR vs. SAMPLE RATE

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SNR vs. INPUT FREQUENCY THD vs. TEMPERATURE

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THD vs. SUPPLY VOLTAGE THD vs. SAMPLE RATE

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THD vs. INPUT FREQUENCY SFDR vs. TEMPERATURE

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SFDR vs. SUPPLY VOLTAGE SFDR vs. SAMPLE RATE

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SFDR vs. INPUT FREQUENCY Spectral Response at FIN = 373 MHZ

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Spectral Response at FIN = 745 MHZ FULL POWER BANDWIDTH

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1.0 Functional DescriptionThe ADC081500 is a versatile A/D Converter with an inno-vative architecture permitting very high speed operation. Thecontrols available ease the application of the device to circuitsolutions. Optimum performance requires adherence to theprovisions discussed here and in the Applications Informa-tion Section.

While it is generally poor practice to allow an active pin tofloat, pins 4 and 14 of the ADC081500 are designed to be leftfloating without jeopardy. In all discussions throughout thisdata sheet, whenever a function is called by allowing acontrol pin to float, connecting that pin to a potential of onehalf the VA supply voltage will have the same effect asallowing it to float.

1.1 OVERVIEW

The ADC081500 uses a calibrated folding and interpolatingarchitecture that achieves over 7.4 effective bits. The use offolding amplifiers greatly reduces the number of comparatorsand power consumption. Interpolation reduces the numberof front-end amplifiers required, minimizing the load on theinput signal and further reducing power requirements. Inaddition to other things, on-chip calibration reduces the INLbow often seen with folding architectures. The result is anextremely fast, high performance, low power converter.

The analog input signal that is within the converter’s inputvoltage range is digitized to eight bits at speeds of 200MSPS to 1.7 GSPS, typical. Differential input voltages belownegative full-scale will cause the output word to consist of allzeroes. Differential input voltages above positive full-scalewill cause the output word to consist of all ones. Either ofthese conditions at the input will cause the OR (Out ofRange) output to be activated. That is, the single OR outputindicates the output code is below negative full scale orabove positive full scale.

The ADC081500 has a 1:2 demultiplexer that feeds twoLVDS output buses. The data on these buses provide anoutput word rate on each bus at half the ADC sampling rateand must be interleaved by the user to provide output wordsat the full conversion rate.

The output levels may be selected to be normal or reduced.Using reduced levels saves power but could result in erro-neous data capture of some or all of the bits, especially athigher sample rates and in marginally designed systems.

1.1.1 Self-Calibration

A self-calibration is performed upon power-up and can alsobe invoked by the user upon command. Calibration trims the100Ω analog input differential termination resistor and mini-mizes full-scale error, offset error, DNL and INL, resulting inmaximizing SNR, THD, SINAD (SNDR) and ENOB. Internalbias currents are also set with the calibration process. All ofthis is true whether the calibration is performed upon powerup or is performed upon command. Running the self calibra-tion is an important part of this chip’s functionality and isrequired in order to obtain adequate performance. In addi-tion to the requirement to be run at power-up, self calibrationmust be re-run whenever the sense of the FSR pin ischanged. For best performance, we recommend that selfcalibration be run 20 seconds or more after application ofpower and whenever the operating temperature changessignificantly relative to the specific system performance re-quirements. See Section 2.4.2.2 for more information. Cali-

bration can not be initiated or run while the device is in thepower-down mode. See Section 1.1.7 for information on theinteraction between Power Down and Calibration.

During the calibration process, the input termination resistoris trimmed to a value that is equal to REXT / 33. This externalresistor is located between pin 32 and ground. REXT must be3300 Ω ±0.1%. With this value, the input termination resistoris trimmed to be 100 Ω. Because REXT is also used to set theproper current for the Track and Hold amplifier, for thepreamplifiers and for the comparators, other values of REXT

should not be used.

In normal operation, calibration is performed just after appli-cation of power and whenever a valid calibration commandis given, which is holding the CAL pin low for at least 80 inputclock cycles, then hold it high for at least another 80 inputclock cycles. The time taken by the calibration procedure isspecified in the A.C. Characteristics Table. Holding the CALpin high upon power up will prevent the calibration processfrom running until the CAL pin experiences the above-mentioned 80 input clock cycles low followed by 80 cycleshigh.

CalDly (pin 127) is used to select one of two delay times afterthe application of power to the start of calibration. Thiscalibration delay is 225 input clock cycles (about 22 ms at 1.5GSPS) with CalDly low, or 231 input clock cycles (about 1.4seconds at 1.5 GSPS) with CalDly high. These delay valuesallow the power supply to come up and stabilize beforecalibration takes place. If the PD pin is high upon power-up,the calibration delay counter will be disabled until the PD pinis brought low. Therefore, holding the PD pin high duringpower up will further delay the start of the power-up calibra-tion cycle. The best setting of the CalDly pin depends uponthe power-on settling time of the power supply.

The CalRun output is high whenever the calibration proce-dure is running. This is true whether the calibration is done atpower-up or on-command.

1.1.2 Acquiring the Input

Data is acquired at the falling edge of CLK+ (pin 18) and thedigital equivalent of that data is available at the digital out-puts 13 input clock cycles later for the D output bus and 14input clock cycles later for the Dd output bus. There is anadditional internal delay called tOD before the data is avail-able at the outputs. See the Timing Diagram. TheADC081500 will convert as long as the input clock signal ispresent. The fully differential comparator design and theinnovative design of the sample-and-hold amplifier, togetherwith self calibration, enables a very flat SINAD/ENOB re-sponse beyond 1.5 GHz. The ADC081500 output data sig-naling is LVDS and the output format is offset binary.

1.1.3 Control Modes

Much of the user control can be accomplished with severalcontrol pins that are provided. Examples include initiation ofthe calibration cycle, power down mode and full scale rangesetting. However, the ADC081500 also provides an Ex-tended Control mode whereby a serial interface is used toaccess register-based control of several advanced features.The Extended Control mode is not intended to be enabledand disabled dynamically. Rather, the user is expected toemploy either the Normal Control mode or the ExtendedControl mode at all times. When the device is in the Ex-tended Control mode, pin-based control of several featuresis replaced with register-based control and those pin-based

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1.0 Functional Description (Continued)

controls are disabled. These pins are OutV (pin 3), OutEdge/DDR (pin 4), FSR (pin 14) and CalDly (pin 127). See Section1.2 for details on the Extended Control mode.

1.1.4 The Analog Inputs

The ADC081500 must be driven with a differential inputsignal. Operation with a single-ended signal is not recom-mended. It is important that the input signals are either a.c.coupled to the inputs with the VCMO pin grounded, or d.c.coupled with the VCMO pin left floating. An input commonmode voltage equal to the VCMO output must be providedwhen d.c. coupling is used.

Two full-scale range settings are provided with pin 14 (FSR).A high on pin 14 causes an input full-scale range setting of870 mVP-P, while grounding pin 14 causes an input full-scalerange setting of 650 mVP-P.

In the Extended Control mode, the full-scale input range canbe set to values between 560 mVP-P and 840 mVP-P througha serial interface. See Section 2.2

1.1.5 Clocking

The ADC081500 must be driven with an a.c. coupled, differ-ential clock signal. Section 2.3 describes the use of the clockinput pins. A differential LVDS output clock is available foruse in latching the ADC output data into whatever device isused to receive the data. The ADC081500 offers options foroutput clocking. These options include a choice of whichDCLK (DCLK) edge the output data transitions on, and achoice of Single Data Rate (SDR) or Double Data Rate(DDR) outputs.

The ADC081500 also has the option to use a duty cyclecorrected clock receiver as part of the input clock circuit. Thisfeature is enabled by default and provides improved ADCclocking. This circuitry allows the ADC to be clocked with asignal source having a duty cycle ratio of 80 / 20 % (worstcase).

1.1.5.1 OutEdge Setting

To help ease data capture in the SDR mode, the output datamay be caused to transition on either the positive or thenegative edge of the output data clock (DCLK). This ischosen with the OutEdge input (pin 4). A high on the Out-Edge input pin causes the output data to transition on therising edge of DCLK, while grounding this input causes theoutput to transition on the falling edge of DCLK. See Section2.4.3.

1.1.5.2 Double Data Rate

A choice of single data rate (SDR) or double data rate (DDR)output is offered. With single data rate the output clock(DCLK) frequency is the same as the data rate of the twooutput buses. With double data rate the DCLK frequency is

half the data rate and data is sent to the outputs on bothedges of DCLK. DDR clocking is enabled in Normal Controlmode by allowing pin 4 to float.

1.1.6 The LVDS Outputs

The data outputs, the Out Of Range (OR) and DCLK, areLVDS. Output current sources provide 3 mA of output currentto a differential 100 Ohm load when the OutV input (pin 14)is high or 2.2 mA when the OutV input is low. For short LVDSlines and low noise systems, satisfactory performance maybe realized with the OutV input low, which results in lowerpower consumption. If the LVDS lines are long and/or thesystem in which the ADC081500 is used is noisy, it may benecessary to tie the OutV pin high.

The LVDS data output have a typical common mode voltageof 800mV when the VBG pin is unconnected and floating.This common mode voltage can be increased to 1.2V bytying the VBG pin to VA if a higher common mode is required.

1.1.7 Power Down

The ADC081500 is in the active state when the Power Downpin (PD) is low. When the PD pin is high, the device is in thepower down mode. In this power down mode the data outputpins (positive and negative) are put into a high impedancestate and the devices power consumption is reduced to aminimal level. The DCLK+/- and OR +/- are not tri-stated,they are weakly pulled down to ground internally. Thereforewhen the device is powered down the DCLK +/- and OR +/-should not be terminated to a DC voltage. Also note, thatupon return to normal operation after power down mode, thepipeline will contain meaningless information.

If the PD input is brought high while a calibration is running,the device will not go into power down until the calibrationsequence is complete. However, if power is applied and PDis already high, the device will not begin the calibrationsequence until the PD input goes low. If a manual calibrationis requested while the device is powered down, the calibra-tion will not begin at all. That is, the manual calibration inputis completely ignored in the power down state.

1.2 NORMAL/EXTENDED CONTROL MODES

The ADC081500 may be operated in one of two modes. Inthe simpler Normal Control mode, the user affects availableconfiguration and control of the device through several con-trol pins. The Extended Control mode provides additionalconfiguration and control options through a serial interfaceand a set of 3 registers. The two control modes are selectedwith pin 14 (FSR/ECE: Extended Control Enable). Thechoice of control modes is required to be a fixed selectionand is not intended to be switched dynamically while thedevice is operational.

Table 1 shows how several of the device features are af-fected by the control mode chosen.

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TABLE 1. Features and modes

Feature Normal Control Mode Extended Control Mode

SDR or DDR Clocking Selected with pin 4Selected with DE bit in theConfiguration Register

DDR Clock Phase Not Selectable (0˚ Phase Only)Selected with DCP bit in theConfiguration Register. See Section1.4 REGISTER DESCRIPTION

SDR Data transitions with rising orfalling DCLK edge

Selected with pin 4Selected with the OE bit in theConfiguration Register

LVDS output level Selected with pin 3Selected with the OV bit (9)in theConfiguration Register

Power-On Calibration Delay Delay Selected with pin 127 Short delay only.

Full-Scale RangeOptions (650 mVP-P or 870 mVP-P)selected with pin 14.

Up to 512 step adjustments over anominal range of 560 mV to 840 mV.Selected using register 3h.

Input Offset Adjust Not possible±45 mV adjustments in 512 stepsusing register 2h.

The default state of the Extended Control Mode is set uponpower-on reset (internally performed by the device) and isshown in Table 2.

TABLE 2. Extended Control Mode Operation (Pin 14Floating)

FeatureExtended Control Mode

Default State

SDR or DDR Clocking DDR Clocking

DDR Clock PhaseData changes with DCLK

edge (0˚ phase)

LVDS Output AmplitudeNormal amplitude

(710 mVP-P)

Calibration Delay Short Delay

Full-Scale Range 700 mV nominal

Input Offset Adjust No adjustment

1.3 THE SERIAL INTERFACE

The 3-pin serial interface is enabled only when the device isin the Extended Control mode. The pins of this interface areSerial Clock (SCLK), Serial Data (SDATA) and Serial Inter-face Chip Select (SCS) Three write only registers are acces-sible through this serial interface.

SCS: This signal should be asserted low while accessing aregister through the serial interface. Setup and hold timeswith respect to the SCLK must be observed.

SCLK: Serial data input is accepted with the rising edge ofthis signal.

SDATA: Each register access requires a specific 32-bit pat-tern at this input. This pattern consists of a header, registeraddress and register value. The data is shifted in MSB first.Setup and hold times with respect to the SCLK must beobserved. See the Timing Diagram.

Each Register access consists of 32 bits, as shown in Figure5 of the Timing Diagrams. The fixed header pattern is 00000000 0001 (eleven zeros followed by a 1). The loadingsequence is such that a "0" is loaded first. These 12 bits formthe header. The next 4 bits are the address of the register

that is to be written to and the last 16 bits are the data writtento the addressed register. The addresses of the variousregisters are indicated in Table 3.

Refer to the Register Description (Section 1.4) for informa-tion on the data to be written to the registers.

Subsequent register accesses may be performed immedi-ately, starting with the 33rd SCLK. This means that the SCSinput does not have to be de-asserted and asserted againbetween register addresses. It is possible, although not rec-ommended, to keep the SCS input permanently enabled (ata logic low) when using extended control.

IMPORTANT NOTE: The Serial Interface should not beused when calibrating the ADC. Doing so will impair theperformance of the device until it is re-calibrated correctly.Programming the serial registers will also reduce dynamicperformance of the ADC for the duration of the registeraccess time.

TABLE 3. Register Addresses

4-Bit Address

Loading Sequence:A3 loaded after H0, A0 loaded last

A3 A2 A1 A0 Hex Register Addressed

0 0 0 0 0h Reserved

0 0 0 1 1h Configuration

0 0 1 0 2h Input Offset

0 0 1 1 3h Input Full-ScaleVoltage Adjust

0 1 0 0 4h Reserved

0 1 0 1 5h Reserved

0 1 1 0 6h Reserved

0 1 1 1 7h Reserved

1 0 0 0 8h Reserved

1 0 0 1 9h Reserved

1 0 1 0 Ah Reserved

1 0 1 1 Bh Reserved

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TABLE 3. Register Addresses (Continued)

1 1 0 0 Ch Reserved

1 1 0 1 Dh Reserved

1 1 1 0 Eh Reserved

1 1 1 1 Fh Reserved

1.4 REGISTER DESCRIPTION

Three write-only registers provide several control and con-figuration options in the Extended Control Mode. These reg-isters have no effect when the device is in the NormalControl Mode. Each register description below also showsthe Power-On Reset (POR) state of each control bit.

Configuration Register

Addr: 1h (0001b) W only (0xB2FF)

D15 D14 D13 D12 D11 D10 D9 D8

1 0 1 DCS DCP nDE OV OE

D7 D6 D5 D4 D3 D2 D1 D0

1 1 1 1 1 1 1 1

Bit 15 Must be set to 1b



Bit 12 DCS: Duty Cycle Stabilizer. When this bit isset to 1b , a duty cycle stabilization circuit isapplied to the clock input. When this bit is setto 0b the stabilization circuit is disabled.

POR State: 1b

Bit 11 DCP: DDR Clock Phase. This bit only has aneffect in the DDR mode. When this bit is setto 0b, the DCLK edges are time-aligned withthe data bus edges ("0˚ Phase"). When thisbit is set to a 1b, the DCLK edges are placedin the middle of the data bit-cells ("90˚Phase").

POR State: 0b

Bit 10 nDE: DDR Enable. When this bit is set to 0b,data bus clocking follows the DDR (DoubleData Rate) mode whereby a data word isoutput with each rising and falling edge ofDCLK. When this bit is set to a 1b, data busclocking follows the SDR (single data rate)mode whereby each data word is output witheither the rising or falling edge of DCLK , asdetermined by the OutEdge bit.

POR State: 0b

Bit 9 OV: Output Voltage. This bit determines theLVDS outputs’ voltage amplitude and has thesame function as the OutV pin that is used inthe normal control mode. When this bit is setto 1b, the standard output amplitude of 710mVP-P is used. When this bit is set to 0b, thereduced output amplitude of 510 mVP-P isused.

POR State: 1b

Bit 8 OE: Output Edge. This bit selects the DCLKedge with which the data words transition inthe SDR mode and has the same effect asthe OutEdge pin in the normal control mode.When this bit is 1, the data outputs changewith the rising edge of DCLK+. When this bitis 0, the data output change with the fallingedge of DCLK+.

POR State: 0b

Bits 7:0 Must be set to 1b.

Input Offset

Addr: 2h (0010b) W only (0x007F)

D15 D14 D13 D12 D11 D10 D9 D8

(MSB) Offset Value (LSB)

D7 D6 D5 D4 D3 D2 D1 D0

Sign 1 1 1 1 1 1 1

Bits 15:8 Input Offset Value. The input offset of theADC is adjusted linearly and monotonicallyby the value in this field. 00h provides anominal zero offset, while FFh provides anominal 45 mV of offset. Thus, each codestep provides 0.176 mV of offset.

POR State: 0000 0000 b

Bit 7 Sign bit. 0b gives positive offset, 1b givesnegative offset.

POR State: 0b

Bit 6:0 Must be set to 1b

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Input Full-Scale Voltage Adjust

Addr: 3h (0011b) W only (0x807F)

D15 D14 D13 D12 D11 D10 D9 D8

(MSB) Adjust Value

D7 D6 D5 D4 D3 D2 D1 D0

(LSB) 1 1 1 1 1 1 1

Bit 15:7 Input Full Scale Voltage Adjust Value. Theinput full-scale voltage or gain of the ADC isadjusted linearly and monotonically with a 9bit data value. The adjustment range is±20% of the nominal 700 mVP-P differentialvalue.

0000 0000 0 560mVP-P

1000 0000 0Default Value

700mVP-P

1111 1111 1 840mVP-P

For best performance, it is recommendedthat the value in this field be limited to therange of 0110 0000 0b to 1110 0000 0b. i.e.,limit the amount of adjustment to ±15%. Theremaining ±5% headroom allows for theADC’s own full scale variation. A gainadjustment does not require ADCre-calibration.

POR State: 1000 0000 0b (no adjustment)

Bits 6:0 Must be set to 1b

1.4.1 Note Regarding Extended Mode Offset Correction

When using the Input Offset Adjust register, the followinginformation should be noted.

For offset values of +0000 0000 and -0000 0000, the actualoffset is not the same. By changing only the sign bit in thiscase, an offset step in the digital output code of about 1/10thof an LSB is experienced. This is shown more clearly in theFigure below.

1.5 MULTIPLE ADC SYNCHRONIZATION

The ADC081500 has the capability to precisely reset itssampling clock input to DCLK output relationship as deter-

mined by the user-supplied DCLK_RST pulse. This allowsmultiple ADCs in a system to have their DCLK (and data)outputs transition at the same time with respect to the sharedCLK input that they all use for sampling.

The DCLK_RST signal must observe some timing require-ments that are shown in Figure 6, Figure 7 and Figure 8 ofthe Timing Diagrams. The DCLK_RST pulse must be of aminimum width and its deassertion edge must observe setupand hold times with respect to the CLK input rising edge.These times are specified in the AC Electrical Characteris-tics Table.

The DCLK_RST signal can be asserted asynchronous to theinput clock. If DCLK_RST is asserted, the DCLK output isimmediately held in a designated state. The state in whichDCLK is held during the reset period is determined by themode of operation (SDR/DDR) and the setting of the OutputEdge configuration pin or bit. (Refer to Figure 6, Figure 7 andFigure 8 for the DCLK reset state conditions). Therefore,depending upon when the DCLK_RST signal is asserted,there may be a narrow pulse on the DCLK line during thisreset event. When the DCLK_RST signal is de-asserted insynchronization with the CLK rising edge, the next CLKfalling edge synchronizes the DCLK output with those ofother ADC081500s in the system. The DCLK output is en-abled again after a constant delay (relative to the input clockfrequency) which is equal to the CLK input to DCLK outputdelay (tSD). The device always exhibits this delay character-istic in normal operation.

The DCLK-RST pin should NOT be brought high while thecalibration process is running (while CalRun is high). Doingso could cause a digital glitch in the digital circuitry, resultingin corruption and invalidation of the calibration.

2.0 Applications Information

2.1 THE REFERENCE VOLTAGE

The voltage reference for the ADC081500 is derived from a1.254V bandgap reference, a buffered version of which ismade available at pin 31, VBG for user convenience and hasan output current capability of ±100 µA. This referencevoltage should be buffered if more current is required.

The internal bandgap-derived reference voltage has a nomi-nal value of 650 mV or 870 mV, as determined by the FSRpin and described in Section 1.1.4.

There is no provision for the use of an external referencevoltage, but the full-scale input voltage can be adjustedthrough a Configuration Register in the Extended Controlmode, as explained in Section 1.2.

Differential input signals up to the chosen full-scale level willbe digitized to 8 bits. Signal excursions beyond the full-scalerange will be clipped at the output. These large signal excur-sions will also activate the OR output for the time that thesignal is out of range. See Section 2.2.2.

One extra feature of the VBG pin is that it can be used toraise the common mode voltage level of the LVDS outputs.The output offset voltage (VOS) is typically 800mV when theVBG pin is used as an output or left unconnected. To raisethe LVDS offset voltage to a typical value of 1200mV the VBG

pin can be connected directly to the supply rails.

2.2 THE ANALOG INPUT

The analog input is a differential one to which the signalsource may be a.c. coupled or d.c. coupled. The full-scaleinput range is selected with the FSR pin to be 650 mVP-P or870 mVP-P, or can be adjusted to values between 560 mVP-P

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FIGURE 10. Extended Mode Offset Behavior

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2.0 Applications Information(Continued)

and 840 mVP-P in the Extended Control mode through theSerial Interface. For best performance, it is recommendedthat the full-scale range be kept between 595 mVP-P and 805mVP-P.

Table 4 gives the input to output relationship with the FSRpin high and the normal (non-extended) mode is used. Withthe FSR pin grounded, the millivolt values in Table 4 arereduced to 75% of the values indicated. In the EnhancedControl Mode, these values will be determined by the fullscale range and offset settings in the Control Registers.

TABLE 4. DIFFERENTIAL INPUT TO OUTPUTRELATIONSHIP (Normal Control Mode, FSR High)

VIN+ VIN− Output Code

VCM − 217.5mV VCM + 217.5mV 0000 0000

VCM − 109 mV VCM + 109 mV 0100 0000

VCM VCM0111 1111 /1000 0000

VCM + 109 mV VCM −109 mV 1100 0000

VCM + 217.5mV VCM − 217.5mV 1111 1111

The buffered analog inputs simplify the task of driving theseinputs and the RC pole that is generally used at samplingADC inputs is not required. If it is desired to use an amplifiercircuit before the ADC, use care in choosing an amplifier withadequate noise and distortion performance and adequategain at the frequencies used for the application.

Note that a precise d.c. common mode voltage must bepresent at the ADC inputs. This common mode voltage,VCMO, is provided on-chip when a.c. input coupling is usedand the input signal is a.c. coupled to the ADC.

When the inputs are a.c. coupled, the VCMO output must begrounded, as shown in Figure 11. This causes the on-chipVCMO voltage to be connected to the inputs through on-chip50k-Ohm resistors.

When the d.c. coupled mode is used, a common modevoltage must be provided at the differential inputs. Thiscommon mode voltage should track the VCMO output pin.Note that the VCMO output potential will change with tem-perature. The common mode output of the driving deviceshould track this change.

Full-scale distortion performance falls off rapidly as theinput common mode voltage deviates from VCMO. This is

a direct result of using a very low supply voltage tominimize power. Keep the input common voltage within50 mV of VCMO.

Performance is as good in the d.c. coupled mode as it isin the a.c. coupled mode, provided the input commonmode voltage at both analog inputs remain within 50 mVof VCMO.

If d.c. coupling is used, it is best to servo the input commonmode voltage, using the VCMO pin, to maintain optimumperformance. An example of this type of circuit is shown inFigure 12.

One such circuit should be used in front of the VIN+ input andanother in front of the VIN− input. In that figure, RD1, RD2 andRD3 are used to divide the VCMO potential so that, after beinggained up by the amplifier, the input common mode voltageis equal to VCMO from the ADC. RD1 and RD2 are split toallow the bypass capacitor to isolate the input signal fromVCMO. RIN, RD2 and RD3 will divide the input signal, if nec-essary. If there is no need to divide the input signal, RIN is notneeded. Capacitor "C" in Figure 12 should be chosen tokeep any component of the input signal from affecting VCMO.

Be sure that the current drawn from the VCMO output doesnot exceed 100 µA.

The Input impedance in the d.c. coupled mode (VCMO pin notgrounded) consists of a precision 100Ω resistor betweenVIN+ and VIN− and a capacitance from each of these inputsto ground. In the a.c. coupled mode the input appears thesame except there is also a resistor of 50K between eachanalog input pin and the VCMO potential.

Driving the inputs beyond full scale will result in a saturationor clipping of the reconstructed output.

2.2.1 Handling Single-Ended Input Signals

There is no provision for the ADC081500 to adequatelyprocess single-ended input signals. The best way to handlesingle-ended signals is to convert them to differential signalsbefore presenting them to the ADC. The easiest way toaccomplish single-ended to differential signal conversion iswith an appropriate balun-connected transformer, as shownin Figure 13.

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FIGURE 11. Differential Input Drive

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FIGURE 12. Example of Servoing the Analog Input withVCMO

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The 100 Ohm external resistor placed across the outputterminals of the balun in parallel with the ADC081500’son-chip 100 Ohm resistor makes a 50 Ohms differentialimpedance at the balun output. Or, 25 Ohms to virtualground at each of the balun output terminals.

Looking into the balun, the source sees the impedance of thefirst coil in series with the impedance at the output of thatcoil. Since the transformer has a 1:1 turns ratio, the imped-ance across the first coil is exactly the same as that at theoutput of the second coil, namely 25 Ohms to virtual ground.So, the 25 Ohms across the first coil in series with the 25Ohms at its output gives 50 Ohms total impedance to matchthe source.

2.2.2 Out Of Range (OR) Indication

When the conversion result is clipped the Out of Rangeoutput is activated such that OR+ goes high and OR- goeslow. This output is active as long as accurate data on theoutput bus would be outside the range of 00h to FFh.

2.2.3 Full-Scale Input Range

As with all A/D Converters, the input range is determined bythe value of the ADC’s reference voltage. The referencevoltage of the ADC081500 is derived from an internal band-gap reference. The FSR pin controls the effective referencevoltage of the ADC081500 such that the differential full-scaleinput range at the analog inputs is 870 mVP-P with the FSRpin high, or is 650 mVP-P with FSR pin low. Best SNR isobtained with FSR high, but better distortion and SFDR areobtained with the FSR pin low.

2.3 THE CLOCK INPUTS

The ADC081500 has differential LVDS clock inputs, CLK+and CLK-, which must be driven with an a.c. coupled, differ-ential clock signal. Although the ADC081500 is tested and itsperformance is guaranteed with a differential 1.5 GHz clock,it typically will function well with input clock frequenciesindicated in the Electrical Characteristics Table. The clockinputs are internally terminated and biased. The input clocksignal must be capacitively coupled to the clock pins asindicated in Figure 14.

Operation up to the sample rates indicated in the ElectricalCharacteristics Table is typically possible if the maximumambient temperatures indicated are not exceeded. Operat-ing at higher sample rates than indicated for the given am-bient temperature may result in reduced device reliabilityand product lifetime. This is because of the higher powerconsumption and die temperatures at high sample rates.Important also for reliability is proper thermal management .See Section 2.6.2.

The differential input clock line pair should have a character-istic impedance of 100Ω and (when using a balun), beterminated at the clock source in that (100Ω) characteristicimpedance. The input clock line should be as short and asdirect as possible. The ADC081500 clock input is internallyterminated with an untrimmed 100Ω resistor.

Insufficient input clock levels will result in poor dynamicperformance. Excessively high input clock levels couldcause a change in the analog input offset voltage. To avoidthese problems, keep the input clock level within the rangespecified in the Electrical Characteristics Table.

The low and high times of the input clock signal can affectthe performance of any A/D Converter. The ADC081500features a duty cycle clock correction circuit which can main-tain performance over the temperature range of operation.The ADC will meet its performance specification if the inputclock high and low times are maintained within the range(20/80% ratio) as specified in the Electrical CharacteristicsTable.

High speed, high performance ADCs such as theADC081500 require a very stable input clock signal withminimum phase noise or jitter. ADC jitter requirements aredefined by the ADC resolution (number of bits), maximumADC input frequency and the input signal amplitude relativeto the ADC input full scale range. The maximum jitter (thesum of the jitter from all sources) allowed to prevent ajitter-induced reduction in SNR is found to be

tJ(MAX) = (VIN(P-P)/VINFSR) x (1/(2(N+1) x π x fIN))

where tJ(MAX) is the rms total of all jitter sources in seconds,VIN(P-P) is the peak-to-peak analog input signal, VINFSR is thefull-scale range of the ADC, "N" is the ADC resolution in bitsand fIN is the maximum input frequency, in Hertz, to the ADCanalog input.

Note that the maximum jitter described above is the arith-metic sum of the jitter from all sources, including that in theADC input clock, that added by the system to the ADC inputclock and input signals and that added by the ADC itself.Since the effective jitter added by the ADC is beyond usercontrol, the best the user can do is to keep the sum of theexternally added input clock jitter and the jitter added by theanalog circuitry to the analog signal to a minimum.

Input clock amplitudes above those specified in the ElectricalCharacteristics Table may result in increased input offsetvoltage. This would cause the converter to produce an out-put code other than the expected 127/128 when both inputpins are at the same potential.

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FIGURE 13. Single-Ended to Differential signalconversion with a balun-connected transformer

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FIGURE 14. Differential (LVDS) Input Clock Connection

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2.4 CONTROL PINS

Six control pins (without the use of the serial interface)provide a wide range of possibilities in the operation of theADC081500 and facilitate its use. These control pins provideFull-Scale Input Range setting, Self Calibration, CalibrationDelay, Output Edge Synchronization choice, LVDS OutputLevel choice and a Power Down feature.

2.4.1 Full-Scale Input Range Setting

The input full-scale range can be selected to be either 650mVP-P or 870 mVP-P, as selected with the FSR control input(pin 14) in the Normal Mode of operation. In the ExtendedControl Mode, the input full-scale range may be set to beanywhere from 560 mVP-P to 840 mVP-P. See Section 2.2 formore information.

2.4.2 Self Calibration

The ADC081500 self-calibration must be run to achievespecified performance. The calibration procedure is runupon power-up and can be run any time on command. Thecalibration procedure is exactly the same whether there is aninput clock present upon power up or if the clock beginssome time after application of power. The CalRun outputindicator is high while a calibration is in progress. Note thatthe DCLK outputs are not active during a calibration cycle.

2.4.2.1 Power-On Calibration

Power-on calibration begins after a time delay following theapplication of power. This time delay is determined by thesetting of CalDly, as described in the Calibration Delay Sec-tion, below.

The calibration process will be not be performed if the CALpin is high at power up. In this case, the calibration cycle willnot begin until the on-command calibration conditions aremet. The ADC081500 will function with the CAL pin held highat power up, but no calibration will be done and performancewill be impaired. A manual calibration, however, may beperformed after powering up with the CAL pin high. SeeOn-Command Calibration Section 2.4.2.2.

The internal power-on calibration circuitry comes up in anunknown logic state. If the input clock is not running at powerup and the power on calibration circuitry is active, it will holdthe analog circuitry in power down and the power consump-tion will typically be less than 200 mW. The power consump-tion will be normal after the clock starts.

2.4.2.2 On-Command Calibration

On-command calibration may be run at any time. To initiatean on-command calibration, bring the CAL pin high for aminimum of 80 input clock cycles after it has been low for aminimum of 80 input clock cycles. Holding the CAL pin highupon power up will prevent execution of power-on calibrationuntil the CAL pin is low for a minimum of 80 input clockcycles, then brought high for a minimum of another 80 inputclock cycles. The calibration cycle will begin 80 input clockcycles after the CAL pin is thus brought high. The CalRunsignal should be monitored to determine when the calibra-tion cycle has completed.

The minimum 80 input clock cycle sequences are required toensure that random noise does not cause a calibration tobegin when it is not desired. As mentioned in section 1.1 forbest performance, a self calibration should be performed 20

seconds or more after power up and repeated when theoperating temperature changes significantly relative to thespecific system design performance requirements. ENOBchanges slightly with increasing junction temperature andcan be easily corrected by performing an on-command cali-bration.

2.4.2.3 Calibration Delay

The CalDly input (pin 127) is used to select one of two delaytimes after the application of power to the start of calibration,as described in Section 1.1.1. The calibration delay valuesallow the power supply to come up and stabilize beforecalibration takes place. With no delay or insufficient delay,calibration would begin before the power supply is stabilizedat its operating value and result in non-optimal calibrationcoefficients. If the PD pin is high upon power-up, the calibra-tion delay counter will be disabled until the PD pin is broughtlow. Therefore, holding the PD pin high during power up willfurther delay the start of the power-up calibration cycle. Thebest setting of the CalDly pin depends upon the power-onsettling time of the power supply.

Note that the calibration delay selection is not possible in theExtended Control mode and the short delay time is used.

2.4.3 Output Edge Synchronization

DCLK signals are available to help latch the converter outputdata into external circuitry. The output data can be synchro-nized with either edge of these DCLK signals. That is, theoutput data transition can be set to occur with either therising edge or the falling edge of the DCLK signal, so thateither edge of that DCLK signal can be used to latch theoutput data into the receiving circuit.

When OutEdge (pin 4) is high, the output data is synchro-nized with (changes with) the rising edge of the DCLK+ (pin82). When OutEdge is low, the output data is synchronizedwith the falling edge of DCLK+.

At the very high speeds of which the ADC081500 is capable,slight differences in the lengths of the DCLK and data linescan mean the difference between successful and erroneousdata capture. The OutEdge pin is used to capture data onthe DCLK edge that best suits the application circuit andlayout.

2.4.4 LVDS Output Level Control

The output level can be set to one of two levels with OutV(pin3). The strength of the output drivers is greater with OutVhigh. With OutV low there is less power consumption in theoutput drivers, but the lower output level means decreasednoise immunity.

For short LVDS lines and low noise systems, satisfactoryperformance may be realized with the OutV input low. If theLVDS lines are long and/or the system in which theADC081500 is used is noisy, it may be necessary to tie theOutV pin high.

2.4.6 Power Down Feature

The Power Down pin (PD) suspends device operation andputs the ADC081500 in a minimum power dissipation state.See Section 1.1.7 for details on the power down feature.

The digital data (+/-) output pins are put into a high imped-ance state when the PD pin is high. Upon return to normaloperation, the pipeline will contain meaningless informationand must be flushed.

If the PD input is brought high while a calibration is running,the device will not go into power down until the calibration

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sequence is complete. However, if power is applied and PDis already high, the device will not begin the calibrationsequence until the PD input goes low. If a manual calibrationis requested while the device is powered down, the calibra-tion will not begin at all. That is, the manual calibration inputis completely ignored in the power down state.

2.5 THE DIGITAL OUTPUTS

The ADC081500 demultiplexes the converter output datainto two LVDS output buses. The results of successive con-versions started on the odd falling edges of the CLK+ pin areavailable on one of the two LVDS buses, while the results ofconversions started on the even falling edges of the CLK+pin are available on the other LVDS bus. This means that,the word rate at each LVDS bus is 1/2 the ADC081500 inputclock rate and the two buses must be multiplexed to obtainthe entire 1.5 GSPS conversion result.

Since the minimum recommended input clock rate for thisdevice is 200 MHz, the effective data rate can be reduced toas low as 100 MSPS by using the results available on justone of the output buses with a 200 MHz input clock, deci-mating the 200 MSPS data by two.

There is one LVDS output clock pair (DCLK+/-) available foruse to latch the LVDS outputs on all buses. Whether the datais sent at the rising or falling edge of DCLK is determined bythe sense of the OutEdge pin, as described in Section 2.4.3.

DDR (Double Data Rate) clocking can also be used. In thismode a word of data is presented with each edge of DCLK,reducing the DCLK frequency to 1/4 the input clock fre-quency. See the Timing Diagram section for details.

The OutV pin is used to set the LVDS differential outputlevels. See Section 2.4.4.

The output format is Offset Binary. Accordingly, a full-scaleinput level with VIN+ positive with respect to VIN− will pro-duce an output code of all ones, a full-scale input level withVIN− positive with respect to VIN+ will produce an outputcode of all zeros and when VIN+ and VIN− are equal, theoutput code will vary between codes 127 and 128.

2.6 POWER CONSIDERATIONS

A/D converters draw sufficient transient current to corrupttheir own power supplies if not adequately bypassed. A 33µF capacitor should be placed within an inch (2.5 cm) of theA/D converter power pins. A 0.1 µF capacitor should beplaced as close as possible to each VA pin, preferably withinone-half centimeter. Leadless chip capacitors are preferredbecause they have low lead inductance.

The VA and VDR supply pins should be isolated from eachother to prevent any digital noise from being coupled into theanalog portions of the ADC. A ferrite choke, such as the JWMiller FB20009-3B, is recommended between these supplylines when a common source is used for them.

As is the case with all high speed converters, theADC081500 should be assumed to have little power supplynoise rejection. Any power supply used for digital circuitry ina system where a lot of digital power is being consumedshould not be used to supply power to the ADC081500. TheADC supplies should be the same supply used for otheranalog circuitry, if not a dedicated supply.

2.6.1 Supply Voltage

The ADC081500 is specified to operate with a supply voltageof 1.9V ±0.1V. It is very important to note that, while thisdevice will function with slightly higher supply voltages,these higher supply voltages may reduce product lifetime.

No pin should ever have a voltage on it that is in excess ofthe supply voltage or below ground by more than 150 mV,not even on a transient basis. This can be a problem uponapplication of power and power shut-down. Be sure that thesupplies to circuits driving any of the input pins, analog ordigital, do not come up any faster than does the voltage atthe ADC081500 power pins.

The Absolute Maximum Ratings should be strictly observed,even during power up and power down. A power supply thatproduces a voltage spike at turn-on and/or turn-off of powercan destroy the ADC081500. The circuit of Figure 15 willprovide supply overshoot protection.

Many linear regulators will produce output spiking atpower-on unless there is a minimum load provided. Activedevices draw very little current until their supply voltagesreach a few hundred millivolts. The result can be a turn-onspike that can destroy the ADC081500, unless a minimumload is provided for the supply. The 100Ω resistor at theregulator output provides a minimum output current duringpower-up to ensure there is no turn-on spiking.

In the circuit of Figure 15, an LM317 linear regulator issatisfactory if its input supply voltage is 4V to 5V . If a 3.3Vsupply is used, an LM1086 linear regulator is recommended.

The output drivers should have a supply voltage, VDR, that iswithin the range specified in the Operating Ratings table.This voltage should not exceed the VA supply voltage.

If the power is applied to the device without an input clocksignal present, the current drawn by the device might bebelow 200 mA. This is because the ADC081500 gets resetthrough clocked logic and its initial state is unknown. If thereset logic comes up in the "on" state, it will cause most ofthe analog circuitry to be powered down, resulting in lessthan 100 mA of current draw. This current is greater than thepower down current because not all of the ADC is powereddown. The device current will be normal after the input clockis established.

2.6.2 Thermal Management

The ADC081500 is capable of impressive speeds and per-formance at very low power levels for its speed. However,the power consumption is still high enough to require atten-tion to thermal management. For reliability reasons, the dietemperature should be kept to a maximum of 130˚C. That is,TA (ambient temperature) plus ADC power consumptiontimes θJA (junction to ambient thermal resistance) should not

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FIGURE 15. Non-Spiking Power Supply

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exceed 130˚C. This is not a problem if the ambient tempera-ture is kept to a maximum of +85˚C as specified in theOperating Ratings section.

Please note that the following are general recommendationsfor mounting exposed pad devices onto a PCB. This shouldbe considered the starting point in PCB and assembly pro-cess development. It is recommended that the process bedeveloped based upon past experience in package mount-ing.

The package of the ADC081500 has an exposed pad on itsback that provides the primary heat removal path as well asexcellent electrical grounding to the printed circuit board.The land pattern design for lead attachment to the PCBshould be the same as for a conventional LQFP, but theexposed pad must be attached to the board to remove themaximum amount of heat from the package, as well as toensure best product parametric performance.

To maximize the removal of heat from the package, a ther-mal land pattern must be incorporated on the PC boardwithin the footprint of the package. The exposed pad of thedevice must be soldered down to ensure adequate heatconduction out of the package. The land pattern for thisexposed pad should be at least as large as the 5 x 5 mm ofthe exposed pad of the package and be located such that theexposed pad of the device is entirely over that thermal landpattern. This thermal land pattern should be electrically con-nected to ground. A clearance of at least 0.5 mm shouldseparate this land pattern from the mounting pads for thepackage pins.

Since a large aperture opening may result in poor release,the aperture opening should be subdivided into an array ofsmaller openings, similar to the land pattern of Figure 16.

To minimize junction temperature, it is recommended that asimple heat sink be built into the PCB. This is done byincluding a copper area of about 2 square inches (6.5 squarecm) on the opposite side of the PCB. This copper area maybe plated or solder coated to prevent corrosion, but shouldnot have a conformal coating, which could provide somethermal insulation. Thermal vias should be used to connectthese top and bottom copper areas. These thermal vias actas "heat pipes" to carry the thermal energy from the deviceside of the board to the opposite side of the board where itcan be more effectively dissipated. The use of 9 to 16thermal vias is recommended.

The thermal vias should be placed on a 1.2 mm grid spacingand have a diameter of 0.30 to 0.33 mm. These vias shouldbe barrel plated to avoid solder wicking into the vias duringthe soldering process as this wicking could cause voids inthe solder between the package exposed pad and the ther-mal land on the PCB. Such voids could increase the thermalresistance between the device and the thermal land on theboard, which would cause the device to run hotter.

If it is desired to monitor die temperature, a temperaturesensor may be mounted on the heat sink area of the boardnear the thermal vias. Allow for a thermal gradient betweenthe temperature sensor and the ADC081500 die of θJ-PAD

times typical power consumption = 2.8 x 1.2 = 3.4˚C. Allow-ing for a 5˚C temperature drop (including an extra 1.6˚Cmargin) from the die to the temperature sensor, then, wouldmean that maintaining a maximum pad temperature readingof 125˚C will ensure that the die temperature does not ex-ceed 130˚C, assuming that the exposed pad of theADC081500 is properly soldered down and the thermal viasare adequate. (The inaccuracy of the temperature sensor isin addtion to the above calculation).

2.7 LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are es-sential to ensure accurate conversion. A single ground planeshould be used, instead of splitting the ground plane intoanalog and digital areas.

Since digital switching transients are composed largely ofhigh frequency components, the skin effect tells us that totalground plane copper weight will have little effect upon thelogic-generated noise. Total surface area is more importantthan is total ground plane volume. Coupling between thetypically noisy digital circuitry and the sensitive analog cir-cuitry can lead to poor performance that may seem impos-sible to isolate and remedy. The solution is to keep theanalog circuitry well separated from the digital circuitry.

High power digital components should not be located on ornear any linear component or power supply trace or planethat services analog or mixed signal components as theresulting common return current path could cause fluctuationin the analog input “ground” return of the ADC, causingexcessive noise in the conversion result.

Generally, we assume that analog and digital lines shouldcross each other at 90˚ to avoid getting digital noise into theanalog path. In high frequency systems, however, avoidcrossing analog and digital lines altogether. The input clocklines should be isolated from ALL other lines, analog ANDdigital. The generally accepted 90˚ crossing should beavoided as even a little coupling can cause problems at highfrequencies. Best performance at high frequencies is ob-tained with a straight signal path.

The analog input should be isolated from noisy signal tracesto avoid coupling of spurious signals into the input. This isespecially important with the low level drive required of theADC081500. Any external component (e.g., a filter capaci-tor) connected between the converter’s input and groundshould be connected to a very clean point in the analogground plane. All analog circuitry (input amplifiers, filters,etc.) should be separated from any digital components.

2.8 DYNAMIC PERFORMANCE

The ADC081500 is a.c. tested and its dynamic performanceis guaranteed. To meet the published specifications andavoid jitter-induced noise, the clock source driving the CLK

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FIGURE 16. Recommended Package Land Pattern

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input must exhibit low rms jitter. The allowable jitter is afunction of the input frequency and the input signal level, asdescribed in Section 2.3.

It is good practice to keep the ADC input clock line as shortas possible, to keep it well away from any other signals andto treat it as a transmission line. Other signals can introducejitter into the input clock signal. The clock signal can alsointroduce noise into the analog path if not isolated from thatpath.

Best dynamic performance is obtained when the exposedpad at the back of the package has a good connection toground. This is because this path from the die to ground is alower impedance than offered by the package pins.

2.9 USING THE SERIAL INTERFACE

The ADC081500 may be operated in the Normal controlmode (using control pins) or in the Extended control mode(using a serial interface and register set). Table 5 and Table6 describe the functions of pins 3, 4, 14 and 127 in theNormal control mode and the Extended control mode, re-spectively.

2.9.1 Normal Control Mode Operation

Normal control mode operation means that the Serial Inter-face is not active and all controllable functions are controlledwith various pin settings. That is, the full-scale range, single-ended or differential input and input coupling (a.c. or d.c.) areall controlled with pin settings. The Normal control mode isused by setting pin 14 high or low, as opposed to letting itfloat. Table 5 indicates the pin functions of the ADC081500 inthe Normal control mode.

TABLE 5. Normal Control Mode Operation (Pin 14 Highor Low)

Pin Low High Floating

30.50 VP-P

Output0.70 VP-P

Outputn/a

4OutEdge =

NegOutEdge =

PosDDR

127 CalDly Low CalDly High n/a

14650 mVP-P

input range870 mVP-P

input range

ExtendedControlMode

Pin 3 can be either high or low in the Normal control mode.Pin 14 must not be left floating to select this mode. SeeSection 1.2 for more information.

Pin 4 can be high or low or can be left floating in the Normalcontrol mode. In the Normal control mode, pin 4 high or lowdefines the edge at which the output data transitions. SeeSection 2.4.3 for more information. If this pin is floating, theoutput clock (DCLK) is a DDR (Double Data Rate) clock (seeSection 1.1.5.3) and the output edge synchronization is irrel-evant since data is clocked out on both DCLK edges.

Pin 127, can be high or low in the Normal control mode, andsets the calibration delay. Pin 127 is not designed to remainfloating.

TABLE 6. Extended Control Mode Operation (Pin 14Floating)

Pin Function

3 SCLK (Serial Clock)

4 SDATA (Serial Data)

127 SCS (Serial Interface Chip Select)

2.10 COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the powersupply rails. For device reliability, no input should go morethan 150 mV below the ground pins or 150 mV above thesupply pins. Exceeding these limits on even a transient basismay not only cause faulty or erratic operation, but mayimpair device reliability. It is not uncommon for high speeddigital circuits to exhibit undershoot that goes more than avolt below ground. Controlling the impedance of high speedlines and terminating these lines in their characteristic im-pedance should control overshoot.

Care should be taken not to overdrive the inputs of theADC081500. Such practice may lead to conversion inaccu-racies and even to device damage.

Incorrect analog input common mode voltage in the d.c.coupled mode. As discussed in section 1.3 and 3.0, theInput common mode voltage must remain within 50 mV ofthe VCMO output , which has a variability with temperaturethat must also be tracked. Distortion performance will bedegraded if the input common mode voltage is more than 50mV from VCMO .

Using an inadequate amplifier to drive the analog input.Use care when choosing a high frequency amplifier to drivethe ADC081500 as many high speed amplifiers will havehigher distortion than will the ADC081500, resulting in over-all system performance degradation.

Driving the VBG pin to change the reference voltage. Asmentioned in Section 2.1, the reference voltage is intendedto be fixed to provide one of two different full-scale values(650 mVP-P and 870 mVP-P). Over driving this pin will notchange the full scale value, but can be used to change theLVDS common mode voltage from 0.8V to 1.2V by tying theVBG pin to VA.

Driving the clock input with an excessively high levelsignal. The ADC input clock level should not exceed thelevel described in the Operating Ratings Table or the inputoffset could change.

Inadequate input clock levels. As described in Section 2.3,insufficient input clock levels can result in poor performance.Excessive input clock levels could result in the introductionof an input offset.

Using a clock source with excessive jitter, using anexcessively long input clock signal trace, or havingother signals coupled to the input clock signal trace.This will cause the sampling interval to vary, causing exces-sive output noise and a reduction in SNR performance.

Failure to provide adequate heat removal. As described inSection 2.6.2, it is important to provide adequate heat re-moval to ensure device reliability. This can either be donewith adequate air flow or the use of a simple heat sink builtinto the board. The backside pad should be grounded forbest performance.

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Physical Dimensions inches (millimeters) unless otherwise noted

NOTES: UNLESS OTHERWISE SPECIFIED

REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB.

128-Lead Exposed Pad LQFPOrder Number ADC081500CIYBNS Package Number VNX128A

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reservesthe right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

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1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into the body, or(b) support or sustain life, and whose failure to perform whenproperly used in accordance with instructions for useprovided in the labeling, can be reasonably expected to resultin a significant injury to the user.

2. A critical component is any component of a life supportdevice or system whose failure to perform can be reasonablyexpected to cause the failure of the life support device orsystem, or to affect its safety or effectiveness.

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