Digital’Logic’Review - California State University...

32
Digital Logic Review Lecture 2 ECE 3220 Digital Design with VHDL

Transcript of Digital’Logic’Review - California State University...

Digital  Logic  ReviewLecture  2

ECE  3220    Digital  Design  with  VHDL

California State University

Lecture Topics

n Basic Logic ReviewBasic GatesBoolean AlgebraDe Morgan’s LawStandard Forms of Boolean Expressions

§ Sum of Products§ Product of Sums

Synthesis using NAND / NOR Gates

California State University

Textbook References

n Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd or 3rd Edition

Chapter 2 Introduction to Logic Circuits

California State University

x 1 = x 0 =

(a) Two states of a switch

S

x

(b) Symbol for a switch

Switch or Relay Logic

n A Binary Switch

(c) Simple connection to a battery

S

Battery Light x

California State University

(a) The logical AND function (series connection)

S Power supply

S

S

Power supply S

(b) The logical OR function (parallel connection)

Light

Light x1 x2

x1

x2

Let y represent the state of the light (y=0 means off, y=1 means on).

y = x1. x2

y = x1+x2

Basic Logic Gates

California State University

S

Power supply S Light

S X1

X2

X3

L(x1, x2, x3) = (x1 + x2) x3

Basic Logic Gates

n A serial to parallel connection

California State University

S Light Power supply

R

x

Basic Logic Gates

n An inverting circuit

L(x) = x’

This is a perfectly valid way to implement a Boolean function, and is effectively how NMOS circuits work (with N-channel transistors acting as the switch).

The switch when closed short circuits the light. The resistor plays two roles here, 1) it provides a path for the current to flow to the light when the switch is open, and 2) limits the current that flows through the switch when it is closed. The resistor is called a pullup.

California State University

Basic Concepts

n Simple logic gates§ AND à 0 if one or more inputs is 0§ OR à 1 if one or more inputs is 1§ NOT§ NAND = AND + NOT 1 if one or more inputs is 0§ NOR = OR + NOT 0 if one or more input is 1§ XOR implements exclusive-OR function

n NAND and NOR gates require fewer transistors than AND and OR in standard CMOS (Inverters  =  2  transistors,  2-­input  NAND/NOR  =  4  transistors,  2-­input  AND/OR  =  6  transistors)

n Functionality can be expressed by a truth tableA truth table lists output for each possible input combination

California State University

Basic Logic Gates

California State University

Complete Set of Gates

n Complete setsA set of gates is complete

if we can implement any logical function using only the type of gates in the set

Some example complete sets{AND, OR, NOT} Not a minimal complete set{AND, NOT}{OR, NOT}{NAND}{NOR}

Minimal complete setA complete set with no redundant elements.

California State University

NAND as a Complete Set

n Proving NAND gate is universal

California State University

Logic Functions

n Logical functions can be expressed in several ways:Truth tableLogical expressionsGraphical formHDL code

n Example:Majority function

Output is one whenever majority of inputs is 1We use 3-input majority function

California State University

Logic Functions (cont’d)

Truth table

A B C F0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1

Logical expression formF = A B + B C + A C

Graphical schematic form

California State University

Boolean Algebra

Name AND version OR versionIdentity x.1 = x x + 0 = xComplement x. x’ = 0 x + x’ = 1Commutative x.y = y.x x + y = y + xDistribution x. (y+z) = xy+xz x + (y. z) = (x+y) (x+z)Idempotent x.x = x x + x = xNull x.0 = 0 x + 1 = 1

n Boolean identities

California State University

Boolean Algebra (cont’d)

n Boolean identities (cont’d)

Name AND version OR versionInvolution x = (x’)’ ---Absorption x. (x+y) = x x + (x.y) = xAssociative x.(y. z) = (x. y).z x + (y + z) = (x + y) + z

California State University

De Morgan’s Theorem

x 1 x 2

x 1

x 2

x 1 x 2

x 1 x 2

x 1

x 2

x 1 x 2

(a)

(b)

(x. y)’ = x’ + y’

(x + y)’ = x’ . y’

California State University

There are two standard forms in which all Boolean expressions can be written:

1. Sum of Products (SOP)2. Product of Sums (POS)

Standard Forms of Boolean Expressions

California State University

Sum of Products (SOP)

n Product Termn Logical  product  =  AND  operationn A  product  term is  the  ANDing  of  literalsn Examples:    A.B,  A'.B.C,  A.C',  B.C'.D',  A.B.C.D

n “Sum  of”n Logical  sum  =  OR  operationn The  sum  of products  is  the  ORing  of  product  terms.

California State University

Sum of Products (SOP)

n The distributive laws are used to multiply out a general Boolean expression to obtain the sum of products (SOP) form.

n The distributive laws are also used to convert a Boolean expression in POS form to one in SOP form.

n A SOP expression is realized using a set of AND gates(one for each product term) driving a single OR gate (for the sum).

California State University

Example of SOP

Designing a SOP form from the following truth table

California State University

Example of SOP

f = (x1’.x2’. x3) + (x1.x2’.x3’) + (x1.x2’.x3) + (x1.x2.x3’)

u There are 4 rows in the truth table where the function takes on the value 1.

u Thus, the SOP representation will contain 4 minterms.

California State University

Sum of Products (SOP)

n SOP  form  expressions  are  often  written  using  the  following   shorthand  notation:

n Direct  implementation   of  the  SOP  form  expressions  result  in  AND-­OR  circuits:  

f (x1, x2, x3) = Σ m(1, 4, 5, 6)

A B

F(A,B)=A’B + AB’

California State University

Product of Sums (POS)

n SumTermn Logical  sum  =  OR  operationn A  sum  term is  the  ORing  of  literalsn Examples:    A+B,  A'+B+C,  A+C',  B+C'+D'

n “Product  of”n Logical  product  =  AND  operationn The  product  of sums  is  the  ANDing  of  sum  terms.

California State University

Product of Sums (POS)

n The distributive laws are used to factor a general Boolean expression to obtain the product of sums (POS) form.

n The distributive laws are also used to convert a Boolean expression in SOP form to one in POS form.

n A POS expression is realized using a set of OR gates (one for each sum term) driving a single AND gate (for the product).

California State University

Example of POS

Designing a POS form from the following truth table

California State University

Example of POS

f = (x1+ x2+ x3) (x1+ x2’ + x3) (x1 + x2’ + x3’) (x1’ + x2’ + x3’)

u There are 4 rows in the truth table where the function takes on the value 0.

u Thus, the POS representation will contain 4 maxterms.

California State University

Product of Sums (POS)

n POS  form  expressions  are  often  written  using  the  following   shorthand  notation:

f  (x1,  x2,  x3)  =  Π M(0,  2,  3,  7)

n Direct  implementation   of  the  POS  form  expressions  result  in  OR-­AND  circuits:  

A B

F(A,B)=(A’+B) (A+B’)

California State University

Synthesis  using  NAND  /  NOR  Gates  

n NAND  /  NOR  gates  are  simpler   to  realize  in  CMOS  technology   than  AND/OR  gates  

A B Z 0 0 1 0 1 0 1 0 0 1 1 0

A B Z 0 0 1 0 1 1 1 0 1 1 1 0

NOR NAND

NAND / NOR gates are simpler to realize in CMOS technology than AND/OR gates

California State University

Synthesis  using  NAND  /  NOR  Gates  

n Using  NAND  gates  to  implement  a  SOP:

Using NAND gates to implement a sum-of-products.

x 1x 2x 3x 4x 5

x 1x 2x 3x 4x 5

x 1x 2x 3x 4x 5

NAND-NAND network

California State University

Synthesis  using  NAND  /  NOR  Gates  

f

f

(a) SOP implementation

(b) NAND implementation

x1

x3

x2

x3

x2

x1

California State University

Synthesis  using  NAND  /  NOR  Gates  

n Using  NOR  gates  to  implement   a  POS:

Using NOR gates to implement a product-of sums.

x 1x 2

x 3x 4x 5

x 1x 2

x 3x 4x 5

x 1x 2

x 3x 4x 5

NOR-NOR network

California State University

Synthesis  using  NAND  /  NOR  Gates  

x1

f

(a) POS implementation

(b) NOR implementation

NOR gate logic was used in building the Apollo spacecraft guidance system in the 1960’s. (see http://klabs.org/history/ech/agc_schematics/index.htm)

f

x3

x2

x1

x3

x2