DIGITAL VIDEO BROADCASTING (DVB) MODULATORFPGA IMPROVES MARKET POSITION

FUSE 25880 DEMOSTRATOR

TTN: CONSORZIO ROMA RICERCHE

AE Abstract

The main activity of the Italian Company ITELCO s.r.l. (150 employees, turnover 4000 KEUR) isthe design manufacture and the test of TV and radio broadcasting equipment (Industrial sector:Electronic components and Tele, Audio and Video Equipment; PRODCOM code: 3230).

Since 1961 ITELCO has installed more than 5000 items of equipment in over 60 different countries.Its equipment is approved by several national broadcasting organisations such as RAI Italy,Telecom-Germany, PTT- Switzerland, Telecom-Poland, Sweden and Finland BroadcastingCorporation and the US Federal Communications Commission (FCC).

On the 30th August 1996 ITELCO got the UNI EN ISO 9001 compliance certification issued byCSQ, the Italian body responsible for quality systems.

Thanks to the experience gained from installing its products all over the world ITELCO hasacquired extensive knowledge in all branches of broadcasting transmission, from Radio Frequencydesign to broadcasting station maintenance.

With this AE the company intends to introduce the Field Programmable Gate Array (FPGA)technology for the development of a Digital Video Broadcasting (DVB) Modulator. This aims atupgrading the existing modulator -at present implemented with discrete (and analogue) logic- andallows Itelco to maintain and raise its market position, since the whole industry sector is moving todigital rather than analogue transmission. Moreover the new modulator will be compliant with thenew European ETSI standard for digital broadcasting transmission.

The new technology will ensure the following advantages:

- High flexibility during design- Reduced dimensions of the board- High market availability- Inbuilt cost improvement due to reducing FPGA costs.

The experiment duration was 10 months with a budget of 52KECU. The estimated return oninvestment is 1000%. over the product life 00of 4 years. (an incremental profit of about 532 KECU). The foreseen payback period is about sixmonths.

A very short “time to market” was the primary motivation that led to the choice of FPGAtechnology since an instantaneous response can be made to product change requirements.

The A.E. is of interest to every company that works in the telecommunications area and those ofsimilar characteristics to Itelco who need to exploit digital technology or increase level ofintegration.

Keywords and Signature:

Keywords: FPGA, Radio broadcasting equipment, ETSI standard, DVB Modulator, Transmitter,Time to market

Signature: 3 0410 541 0174 2 3230 2 32 I

1. 1. Company name and address

Itelco S.p.A.Loc. Sferracavallo 19/A05019 Orvieto (TR) ItalyTel. +39 0763 3961Fax +39 0763 391464 Contact person: dott.ssa Anna Achino/

BacchioTel.: 0763/396(1)-325Bacchio 0774357400

Fax: 0763/393207

2. Company size

The current number of employees is 150. The Technical Department is constituted of 57 people (15graduates in electronic engineering).The company turnover is 4000 KEUR.

3. Company business description

The main activity of ITELCO is the design, manufacture and test of TV and radio broadcasttransmission equipment (more than thirty years of experience in this field):Among its services, Itelco supplies both single and in-system configuration equipment , includingthe planning, design and installation of national networksThe setting-up of the first private Portuguese TV network "La Quatro" is an example of turn-keyproject experience of the ITELCO Company.Itelco has the advantage to be concentrated on this particular market, and to be very flexibleaccording to the continuous market variations and to the market needs of very specialised productsin small quantities (Radio and TV Receivers).On the other side, Itelco has the disadvantage of being a small company compared to othercompetitors with an historical presence in international markets. Its headquarters and singleproduction plant are located in Orvieto (Italy). Industrial sector: Electronic components and Tele, Audio and Video Equipment; PRODCOM code:3230.

4. Company markets and competitive position at the start of the AE

During the period 1996-1997 the potential world market for TV/Radio broadcasting instrumentswas roughly 250 – 300 MEUR and Itelco S.p.A. got a global market share around 7 % selling afully analogue technology product complying with radio and TV transmission standards.

Here are described some of the most important competitors :

Competitor A) -(USA)- with a large American market share, slightly less in Asia andAustralia, and not so big in Europe. Overall their global market share is of 20%.

Competitor B) -(Germany)- is well known in Western and Eastern Europe but not so muchin Asia and America. Their global share is 8 % .

Competitor C) -(Japan)- has a large share of the market in Asia and reasonable in USA andEurope but overall world-wide they have 5 % market share.

Competitor D) -(France)- has strong market position in Europe and Africa and a reasonablein share in Asia. Their total share is approximately 15% of the global market.

Starting from mid-1996, the availability of the new digital scheme for broadcasting transmission,would have caused a gradual but certain loss of competitiveness for the companies unable to begin astrong technical up-date towards the new digital technology. This is confirmed by the commontrend of all the main competitors mentioned above, easily moving to digital in order not to loosetheir competitiveness. Itelco at the start of the AE focused on the transition to digital for their keyTV modulator product, whose market share in 1997 was 8% ; and its pricing approximately 50-100KEUR.The product market opportunities outside Europe range from Africa to East Europe and SouthAmerica, not excluding replacements all over the world.

Itelco, by means of a fast introduction of the FPGA technology by FUSE, is a leader in the digitalmarket.

Economic History of AE product:

Sales figure 1996 1997 1998( KECU)

Turnover product 11000 10340 8250Cost product (per unit) 73,3 73,9 73,7Profit product (per unit) 22,0 22,2 22,1Number of products sold 150 140 112

The main features of the old product were:• Compactness• High modularity• Easy to repair

MARKET EVOLUTION (products sold)

5. Product to be improved and the reasons to innovate

The core of a TV transmitter is the modulator; it is used in all Itelco TV transmitters for VHF andUHF bands. Before the AE, the TV modulator performed the analogue processing of the TV signal,such as modulation, up-conversion using AM-VSB scheme and up- conversion with mixing andfiltering. This processing is carried out by means of discrete electronic circuits packaged on amulti-layer PCB.

The component specification were:• Channel Bandwidth (7.61 MHz)• Symbol Rate (64/7 MSps)• Modulation (QPSK; 16-QAM; 64-QAM)• OFDM Symbol (1705; 6817 carriers)• Useful data (1512; 6408 carriers)

A block diagram of a typical TV transmitter is shown here, the existing and improved version ofthis is also compared (see next paragraph).

ANALOGUE TV MODULATOR Video Audio

Video Input

Audio Input

IF MODULATOR IF / RF Converter

RF Amplifier

RF FILTER

UHF or VHF bandOutput ( to antenna)

Local Oscillator

0

50

100

150

200

250

300

350

400

1996 1997 1998

A

B

C

D

ITELCO

The typical end-user is the terrestrial broadcaster, usually a company charged by the Authority tobroadcast the TV signal all over the country. The reason to innovate was that the actual product was short of important characteristics as follows: - Possibility of using the same frequency band employed in the analogue television, to

transmit more channels (a quantity 6-7 times bigger). This situation will make possible todecongest the crowding of UHF/VHF spectrum for the transmission of video signal openingnew opportunities for the operators of this field (pay-tv, pay-per-view, thematic channels).

- The quality, with which it will be possible to receive the signal, is extremely high comparedto the one of the analogue TV (comparable with the film quality).

- Possibility of receiving the TV by users on the move (as an example by a receiver placedinside a bus).

Power and weight was not the main issue, since the new product is radically different from the oldone (channel number 6-7 times bigger, full digital… ). For this reasonTherefore a comparativepower/performance and weight/performance ratio is not representative(??).pertinent.

6. Description of the technical product improvements

DIGITAL DVB-T MODULATOR MPEG-2 Stream In the new digital modulator the channing coding digital functions like Reed-Solomon encoder,time interleaver, Viterbi encoder and signal processing will be implemented by FPGA technology. The new product is completely different and improved respect to the old one. The old productperforms a 30 years-old modulation scheme for video and audio signal; the improved one performsstate-of-art digital modulation and processing. On the above basis, performance is vastly improved; that is, all the advantages of digital processingwith respect to analogue are taken. In addition reduction in power consumption (relative to channelnumber) and efficiency use of the frequency spectrum are improved. The channel encoder and theCOFDM modulator compose the new modulator. The channel encoder was developed using FPGAchips; the objective was to use 14 FPGA containing up to 75000 gates and 6 bootstrap EPROMs toprovide the required functionality. Energy dispersal, time interleaving, convolution encoding, puncturing, bit and symbol interleaving,mapped with pilot signal & TPS insertion are the digital processing functions implemented on theboard by means of FPGAs. Specifications were taken from European standard ETSI 300744 for Digital Video Broadcasting;framing structure, channel coding and modulation for digital Terrestrial television (DVB-T).

UHF or VHF bandOutput ( to antena)

Local Oscillator

Interface & Sync.

Channel Encoder

COFDM Modulation

IF / RF Converter

RF Amplifier

RF FILTER

As far as design methodologies are concerned, we used graphic capture of the electrical schematicrather than a VHDL graphic language. Some of the DVB-T modulator technical characteristics are:- 9.5 inches x 4HE;- 14 FPGAs for channel encoding functions;- different FPGAs package;- different FPGAs size;- up to 75000 gates;- modular design with plug-in boards- Transport Stream MPEG-2 digital input and IF analogue output. 7. Choices and rationale for the selected technologies, tools and methodologies

The basic requirements considered were: - Shortest time to market shortest.- Total digital gate number (close to 80,000)- Processing requirements- High flexibility thatin order to guarantees the possibility of inserting corrections or up-grading,

thus reducing design risks and assuring an efficient maintainability - Reduced design NRE costs- Reduced dimensions of the board- Manufacturing costs. - Easy evaluation of the compliance with EMC requirements- High flexibility that guarantees the possibility of inserting corrections or up-grading during

design- Reduced dimensions of the board- Easy evaluation of the compliance with EMC requirements- Reduced design costs- Reduced manufacturing costs due to the employment of general purpose components

We went trough different technology options:1. Commercial ‘off-the-shelf’ dedicated components.1.2. DSP2.3. ASIC3.4. FPGA

1) Since the DVB-T standard is a very recent one, 'off-the-shelf' components able to realise all thefunctions that the DVB-T channel codification needs are not yet available.

2) DSP is normally used for general-purpose applications when the required computationalcalculation is not too high compared to the operating frequency. The requested high processingrequirements for the digital functions do not allow the use of DSP products.

3) The ASIC technology has been avoided because of its high costs of design and prototyping.Non recurring engineering charges can only be recovered through amortising over large-scaleproduction, which is not the case at Itelco. The reduced number of pieces (seehown in themarket analysis on the table 1) does not justify ASIC technology. Main selection parameters arerepresented in a synthetic form in the following table.

Requirements Value

Time to market longGate number Very highProcessing capability Very highDesign risks Very highMaintenance Very complexNRE costs Very high

4) The short “time to market” has reduced the choice of technology to be used for the project to theFPGAs. Since the FPGAs re-programmable in the product, any possible mistake inprogramming can be solved and, furthermore, the gate capacity is very high. In this way, severalfunctions can be stored into an FPGA instead of into discrete components that would need largequantity of space. Main selection parameters are represented in a synthetic form in the followingtable.

Requirements ValueTime to market Very shortGate number HighProcessing capability HighDesign risks Very lowMaintenance Very easyNRE costs Very low

Other parameters:- Dimension constrains are not too strengthso strict to justify a full integrated solution (ASIC) and

not so weak ide to allow a discrete component based implementation. FPGA solution is the bestchoice.

- Complexity of EMC requirements evaluation is easier for a full integrated solution (ASIC) butis not high in an FPGA based board.

Power is not a constrain for an FPGA or ASIC based implementation (both solutions fulfilrequirements).

1)DSP is normally used for general-purpose applications when the required computationalcalculation is not too high compared to the operating frequency. Moreover because the DVB-Tstandard is a very recent one, 'off-the-shelf' components able to realise all the functions that theDVB-T channe l codification needs are not yet available. The requested high processingrequirements for the digital functions do not allow the use of DSP products.

2)The ASIC technology has been avoided because of its high costs of design and prototyping. Nonrecurring engineering charges can only be recovered through amortising over large-scaleproduction, which is not the case at Itelco. The reduced number of pieces (see the marketanalysis on the table 1) does not justify ASIC technology;. and the unavailability into themarket of "off-the-shelf components" for our relevant digital functions does not allow the use ofsuch technology;

3)The short “time to market” has reduced the choice of technology t o be used for the project to theFPGAs.Since the FPGAs re-programmable in the product, any possible mistake in programmingcan be solved and, furthermore, the gate capacity is very high. In this way, several functions canbe stored into an FPGA instead of into discrete components that would need large quantity ofspace.

The methodology chosen lies on the following scheme: Two training, one for the new software and the other as a support for University during criticaltimes of the project. A set of well-defined specifications with the support of ETSI, so that it has been minimised theinaccuracies and optimise the time-to-market. Parallel set of design activities for the functions to be implement Evaluation with electrical, functional test of the single board and after integration a test with thetransmission chain like a field test set. Regarding the design methodologies, we used graphic capture of the electrical scheme methodinstead of VHDL language. The main reasons to justify this approach are:- Our internal R&D department is based on engineers with high expertise on schematic capture

(used for circuit design).- Our engineers are not skilled on VHDL.- Project complexity (in term of design and debug) is very high.- “time to market” reduction iswas our main constrain for this project For these reasons it has been decided, taking into consideration the complexity of the project itself,not to use at first the VHDL which will be only be used when the project is realised, for the resultsconversion and control. The tools were CAD Viewlogic tools.

Regarding the design methodologies, we used graphic capture of the electrical scheme methodinstead of VHDL language. In fact in our internal R&D department, there are people able to designemploying capture method, whereas there is not VHDL skilled people and the short time to put intothe market the DVB transmitter does not allow us to spend time for VHDL design language trainingas it would be necessary.

The tools were CAD Viewlogic tools.

We have made use of graphic capture, as it is easier to learn and quicker at ge tting to a layout thanVHDL. In the company the rapid capture technique is widely used for analogue circuit design and,therefore, our human resources involved in the project were quite experienced in this field.

Since the “time to market” reduction is one of the main objectives of the project, it has beendecided, taking into consideration the complexity of the project itself, not to use at first the VHDLwhich will be only used when the project is realised, for the results conversion and control.

8. Expertise and experience in microelectronics of the Company prior the AE. The activity of Itelco Company is the design, manufacturing and testing of TV/radio transmissionequipment.

Since 1961 The Company has installed more than 5000 transmitters for broadcasting in over than 60 countries and items of Itelco equipment are approved by several national broadcasting bodies. The existing know-how before the Application Experiment was in analogue electronic circuitdesign, RF design up to 2 GHz, PCB design and micro controllers implementation for control logicunits. Electronic engineering graduates with 2 years of logic and digital circuit design experiencecompose the staff allocated to the project for the junior, 5 for the senior, and 7 for system designand technical managing experiences of the technical manager. The lack of experience in the design of programmable devices justified the training on the job withthe University and the effort to find a funding opportunity, very important condition most of all foran SME.The human resources allocated to the AE consisted of the technical manager as project leader, asenior design engineer, a junior design engineer and a few technicians involved in assemblyactivities.The technical department consists of 57 persons including 15 electronic engineering graduates. It isdivided into 10 services, 4 of them design (electronic, RF, systems and control systems). Theelectronic design service is divided into an analogue and a digital section.

9. Work plan and rationale Herewith enclosed the original work plan as defined during the preparation of the proposalcompared with the actual followed:

Activities Totals (kECU)

1 2 3 4 5 6 7 8 9 10 Management 9.12 Management(planned)

X X X X X X X X X X 9.12

(actual) X X X X X X X X X X Training X X X X X X X X X X 10.73 (planned) X X X X X X X X X X (actual) X X X X X X X X X X Specification X 1.86 (planned) X (actual) X Design X X X X X X X 26.35 (planned) X X X X X X X (actual) X X X X X X X X Evaluation X X 3.94 (planned) X X (actual) X X Total(kECU) 52

It’s useful at this point to describe the work packages of the project with their rationale:

WORKPACKAGE 1 TECHNICAL MANAGEMENT Objective To guarantee the management of all activities during the Application Experiment Description It carries out project management activities, editing of monthly reports on the tasks process,dissemination and exploitation trhoughthrough advertising and meetings planned with the TTN andother EC organisations. Duration 215 10 monthsdays (all time of the project) Roles and Responsibilities The First User was in charge of all management activities with a Project Manager.

Task 1.1 Project Management Objective To manage all activities of the project Description In this task the workplan was outlined and contacts were carried on with people involved; inparticular with hardware and software suppliers, ViewLogic and University of Perugia assubcontractors and with the TTN. Duration 215days23 labour person days Roles and Responsibilities

The First User dedicated internal high-profile resources (in charge for some project phases) totechnical management.

Task 1.2 Reporting Objective To assure sending of monthly progress report , monitoring of the activities and meetings withsubcontractors. Description The Project Manager fulfilled 10 (ten) Monthly Report on all activities in progress (both technicaland managerial activities). He also provided 3 (three) Cost Statement, the first after three month from the beginning, thesecond after other three months and the last at the end of the program. Duration 16 labour person days195 days Roles and Responsibilities First User guaranteed for the reliability of the Progress Report and the Costs Statements; he was ofcourse expected to explain to the European Commission the progresses in the most clear andconcise way.

Task 1.3 Dissemination and Exploitation of AE results Objective To obtain a widespread dissemination and exploitation of the Application Experiment results. Description Dissemination of our FPGA design and management capability improvement writing articles (onour technical magazine ITELCO PRESS and on European Commission publication FUSENewsletter if requested), and also meeting with our TTN and participating to conferences andexhibition all over the world. Duration 5 labour person days40 days Roles and Responsibilities First User's marketing and advertising people were in charge for the dissemination, since the FirstUser is liable for the modality of the actions that will guarantee the best dissemination andexploitation of the results.

WORKPACKAGE 2 TRAINING Objective To allow us to learn the key points of FPGA technology in the shortest time and with maximumefficiency. Description Two training courses have taken place:- a CAD training carried out by Application Engineer by ViewLogic- a on-the-job training from University of Perugia Electronic Department. Duration 5 days for CAD course and the whole project duration for the other. Roles and Responsibilities In this tasks co-operated: the First User with design engineers, the Subcontractor Viewlogic with anApplication Engineer, the Subcontractor Electronic Department of Perugia University with a skilledperson.

Task 2.1 Management Training

Objective To guarantee the effective development of the training without delay or misunderstanding betweenFirst User and sub-contractors. Description Trough direct contacts it has been possible to arrange meetings during design activities with sub-contractors, in which results were discussed and the solutions to critical problems were found. Duration 215 3 labour person daysdays Roles and Responsibilities One engineer of the ITELCO team was in charge of management of the training activities, bothfrom a logistic and from an economic point of view.

Task 2.2 CAD Training Objective To optimise the use of CAD Viewlogic software. Description The training necessary to begin to design with ViewLogic software was carried out in order tolearn, trough a direct approach supplied by an application engineer, the basic instructions that canguarantee an efficient use of the design software. Duration 5 labour person daysdays Roles and Responsibilities An Application Engineer from Viewlogic with Itelco Design Engineers worked together since thebeginning of the development of the modulator functions.

Task 2.3 on job Training Objective To optimise design times and validate design results. Description The on-the-job training during all the project was carried out through meetings (in ITELCOpremises or at University of Perugia) between ITELCO project team and a delegate from theSubcontractor in order to validate the results of design phases. Duration 184 30 labour person daysdays Roles and Responsibilities A Research Engineer from the Electronic Department of Perugia University worked together withITELCO design engineers during all the project time for the modulator functions.

WORKPACKAGE 3 SPECIFICATION Objective To define a complete and compliant with ETSI DVB standard set of specification for the design of aDVB TV modulator. Description In accordance with ETS 300744 (DVB standard) document, we wanted to establish thespecifications in order to carry out the correct synchronisation, coding and processing of MPEG-2data stream. Duration 12 daysmonth 1 Roles and Responsibilities

ITELCO design engineers got the role and responsibility for defining technical and functionalspecifications for DVB Itelco modulator in accordance with ETSI standard.

Task 3.1 Functional Specification

Objective To identify the type of digital functions that will be developed trough FPGA technology. Description The functions that had to be developed with software development and FPGAs were described,considering the FPGA components available and the functions defined in DVB ETSI standard, Duration 5 dayslabour person days Roles and Responsibilities ITELCO Design engineers took the responsibility to define the functional specifications of thedigital modulator.

Task 3.2 Technical Specification

Objective To define the technical parameters of digital DVB modulator in accordance with ETSI DVBstandard. Description Taking into account the input and output interfaces and the other parts of the DVB transmitter, thedesign engineers defined the correct range of values for what concerns the most important technicalparameters of DVB modulator. Duration 7 labour person days days Roles and Responsibilities Two ITELCO design engineers took the responsibility to define the technical specifications.

WORKPACKAGE 4 DESIGN Objective To design a TV digital modulator compliant with the ETSI standard PR 300744 "Digital VideoBroadcasting" with digital MPEG-2 stream input and IF modulated analogue output. Description In the field of above objective, most of the functions concerning digital signal processing foreseenin the ETSI standard were implemented by Field Programmable Gate Array technology. We can consider that the following sub-units were involved by this design phase: - Interface and Synchronism unit - Channel encoder unit - Up-converter unit - Mechanics unit (frame) - Power supply Unit - Mother board Unit For each of them we considered a complete activity design. Duration 168 days ??????8 months Roles and Responsibilities

The Design Engineers had the responsibility to develop the new digital TV modulator with the helpof the Subcontractor University of Perugia that monitored the critical points of the design (on-the-job training).

Task 4.1 Interface Design Objective To carry out an interface board able to allow the connection between modulator and DVBmultiplexer. Description This interface will be a board containing one or more FPGA and analogue circuits. It will be implemented also with the function able to extract synchronism from received data bymeans Phase Locked Loop (PLL) circuit. Duration 2023 labour person daysdays

Task 4.2 Channel Encoder Design Objective To carry out a board able to implement the channel encoding functions as described in ETSIstandard 300744 for Digital Video Broadcasting. Description The channel encoder will be realised using FPGAs. Since the effort had been very strong; we reliedon our sub-contractors support during the critical phases. The functions of the encoder were: - Energy dispersal - Reed Solomon coding (outer coder) - Outer interleaver - Convolutional coding (inner coder) - Inner interleaver - Mapper & modulator - Frame adaptation Duration 38 labour person days115 days

Task 4.3 Up-converter design Objective To develop a BB-IF converter able to convert without degradation and without spurious (afterfiltering) the Base - Band DVB analogue signal. Description The Up-converter was composed by a mixer and by a filter for mixing products. Again 2monitoring points were fixed: at the BB input and in correspondence to the IF output after filtering. Duration 20 labour person days45 days

Task 4.4 Mechanics Design Objective We wanted to develop a mechanical frame suitable to be a container of the digital modulator boardsand the supplying. Description

The mechanical part consisted of a 3 HE / 19 inch frame with possibility on the front panel ofsignals monitoring. The structure was modular with a motherboard and several single-function boards. During thedesign peculiar attention was paid in order to guarantee rapid access to the boards for a shortermaintenance time. Duration 20 labour person days30 days

Task 4.5 Power Supply Design Objective To develop a power supply able to provide necessary DC voltages for all boards inside themodulator frame. Description The power supply was designed maintaining separate the supply for digital and analogue boards inorder to avoid coupling of the noise produced by digital boards. The DC voltages values will be: + 5V, -5 V, +12V, -12V, +24V. Duration 25 labour person days40 days

Task 4.6 Mother board Design Objective To develop an interconnection board between modulator boards. Description The motherboard had been realised in order to ensure that the connectors will be positioned at asufficient distance from each other to avoid coupling and interference problems. The design wasdone in compliance with EMC requirements. Duration 32 labour person days

WORKPACKAGE 5 EVALUATION Objective Evaluate the performances of the new digital modulator. Description We implemented some tests to evaluate electrical and functional performances, and then we carriedout a test to evaluate the compatibility with demodulator. A testing ground composed by an MPEG-2 source encoder, a multiplexer, the modulator under test, a test receiver and some test instrumentswas carried out. In particular, the performances were evaluated with spectrum analyser and noisegenerator. Duration 35 days2 months Roles and Responsibilities The ITELCO team of design engineers involved in the project will have the responsibility of the testsessions.

Task 5.1 Electrical Testing Objective To find out supplying and soldering problems. Description

We proceeded to verify for each board the electrical continuity of all components connections,between components and supplying and between components and grounds. Again, with supply on,electrical parameters of the signals presents in different test points inside each board have beenassessed. Duration 5 4 labour person days days Roles and Responsibilities One ITELCO Engineer member of the digital team was responsible for the electrical testing.

Task 5.2 Functional Testing Objective To verify that the achievement trough the FPGA of the modulator functions would be coherent withwhat requested during specification phase. Description In this task it has been checked if the implementation with FPGA of the channel encoder andprocessing functions gave the same results of software simulations done before. Duration 10 8 labour person daysdays Roles and Responsibilities One ITELCO Design Engineer, member of the digital team, was liable for the functional testing.

Task 5.3 Final Integration Objective The integration of the boards in order to verify global functionality of the modulator. After that, possible problems didn’t arise during single board testing . Description The integration consisted in boards positioning inside the frame, and in supplying connecting andmodulator functions control in all modality. Duration 5 labour person daysdays Roles and Responsibilities One ITELCO Engineer, member of the digital team, was liable for the final integration.

Task 5.4 Field Testing Objective Verify the correct functioning of all transmission equipment including modulator, up converter andpower RF components in the real environmental conditions and the compatibility with adecoder/demodulator equipment. Description All modulator specifications defined in the design phase were measured and analysed in real timethrough a receiving set. Duration 18.3 labour person days5 days Roles and Responsibilities Two ITELCO Engineers, member of the digital team, were liable for the Field-testing. Cost and effort of Application Experiment: (from the Associated Contract Annex 1)

Labour(persondays -

planned)

Labour(persondays –actual)

Labour Cost

(kECU)

Travel & Subsist.(kECU)

DurableEquip. * (kECU)

Consu-mables (kECU)

Other** (kECU)

Totals

(kECU)

Workpackage 1 49,5 44 8,02 1,1 0 0 0 9,12 Workpackage 2 42,0 38 6,80 0 0 0 3,93 10,73 Workpackage 3 11,5 11.5 1,86 0 0 0 0 1,86 Workpackage 4 140 155 22,68 0 2,97 0,70 0 26,35 Workpackage 5 24,3 24.3 3,94 0 0 0 0 3,94 Totals 267,3 272.8 43,3 1,1 2,97 0,70 3,93 52

* Hardware and Software equipment ** The Other cost represents the sum of the cost of all Subcontractors for each task. Cost and effort of Subcontractors (actual are equal to planned):

Subcontractor 1 Subcontractor 2 Labour

(persondays)

Total Cost

(kECU)

Labour (persondays)

Total Cost

(kECU)

Workpackage 1 0 0 0 0 Workpackage 2 5 2,36 20 1,57 Workpackage 3 0 0 0 0 Workpackage 4 0 0 0 0 Workpackage 5 0 0 0 0 Total 5 2,36 20 1,57

The actual workplan was very similar to the original, the design lasted up to the end of the ninthmonth and the most of the performance evaluations have been done during the tenth. We found difficulties to adhere to the schedule because of unexpected events ( peronnel atechnician had to be substitutedmodification???) during the AE, but trough continuous monitoringwith weekly follow-up meetings the managers was able to take care of issues as they arose. In the project the following FPGA are used: - N. 2 XC2064PC68- N. 1 XC3195APC84- N. 5 XC3190APC84- N. 4 XC3195APP175- N. 1 XC4006EPQ160 Different FPGA types are used in order to utilise the best characteristics of each family in relationto the project requirements of the different functional blocks that constitute the modulator. The knowledge transfer process has developed in a theoretic part form the subcontractor Viewlogic(from which also software packages for FPGA have been purchased) where the use of the new toolswas approached and in a continuos support during the project development. Furthermore, since the first meeting where a specific FPGA type has been chosen, PerugiaUniversity Department of Electronics supported the staff. Training continued with more completecourses and with on –the job-training during the implementation of programmable logic.

10. Subcontractor information Itelco's primary concern was time to market, while the capabilities and costs of the design toolswere significant choice factors. The Company, already having experience with schematic capturetools felt that this was the quickest and safest route for a speedy design cycle.

Itelco has drawn up subcontractor contracts after having verified the real possibility to comply withthe scheduled time, without including specific clauses on this matter. For what concerns IPR, noparticular clause was arranged on it. VIEWLOGIC System Inc. Founded in 1984, Viewlogic Systems Inc. is a worldwide supplier of electronic design automationsoftware. They develop, market and support a comprehensive family of software tools for thedesign of advanced electronic products. The Company’s strategy is to focus on key productivity enhancing software for CAE and segmentof the electronic design automation (EDA) market. This software automate the design entry,analysis and verification of:

- Integrated Circuit (ICs) - Application Specific Integrated Circuit (ASICs) - Field Programmable Gate Arrays (FPGAs) - Programmable Logic Devices (PLDs) - Printed Circuit Boards (PLDs) - Entire Electronic Systems

The Viewlogic support has been chosen after evaluation of costs and quality against otherscompetitors. Its tools were considered suitable as far as cost, availability training time and supportwere concerned. The additional 'on the job training' at the start of the Experiment was seen asparticularly helpful. Moreover, the shortest design time was assured, and this was very relevant tothe company concern about the time to market. UNIVERSITY OF PERUGIA Electronic Department

Moving from analogue to digital, ITELCO needed a high level of support and expertise from asubcontractor skilled in the application of digital techniques in this specific sphere of activity, andwho would be flexible at a competitive cost. The amount of time needed, and the pertinent costswere fairly insignificant so the University of Perugia, with whom Itelco personnel had worked for 4years and who had a proven track record in digital design for broadcasting were chosen. The factthat the Subcontractor was within easy reach of Itelco was an added bonus.

The University of Perugia has in its Electronic Department a research team in the field of electronicdesign who can guarantee a high level support during critical design phases.Itelco co-operates by many years with University of Perugia through global agreements on yearbase

11. Barriers perceived by the Company in the first use of the AE technology

Facing this AE we met the following barriers:

? Experience and expertise shortages in digital processing design, development and test? Ignorance of design software packages available on the market and how they can be utilised? Financial barrier caused by the lack of knowledge of the actual cost of transferring a new

microelectronics technology into the company.

12. Steps ahead to overcome the barriers and arrive at an improved product

• The lack of experience and expertise was overcome with young motivated engineers with a

previous experience in digital processing design.• Through initial meetings and courses the subcontractor VIEWLOGIC explained us the different

possibilities given by the different design software packages and helped us to choose the rightone.

• The financial risk was diminished by a planning approach connected to a strict monitoringactivity.

The TTN continuous support and the sub-contractors contact allowed us to start easily with themethodology introduction and gave us the possibility to keep in touch with the technical evolutionof our business sector. In particular the TTN initial training on technology possibilities and itssupport in the workplan organisation was very helpful. 13. Knowledge and experience acquired:

The Company personnel now know how to

• Design and use FPGA technology to implement several systems• Implement a design in a variety of FPGA gate densities and packages.• Improve the chance of project success through planning and management of R&D activities.• Use FPGA design software effectively.• Work closely and use technical subcontractors.• Select a technology to fit the product needs.• Specify and select a subcontractor for FPGA support.

And this satisfied was more or less coincident with what the FU expected to learnexpectations. Themain objectives of the FU were achieved in terms of approaching the digital equipment market andof acquisition of FPGA technology.

14. Lessons learned What we learned from this AE, and can therefore be useful to other FUs, can be summarised asfollows: • In order to minimise inconveniences during the simulation of the layout and the further test of

the board it is important to dedicate more time to a correct functional simulation before theboard layout development.

• Invest time in choosing the right FPGA manufacturers, depending on the degree of complexityneeded for the application concerned.

• It is also important a deep and well throughout analysis of planning to lower the perceived risk.• Encourage stronger teamwork as the best way to ensure problem identification and solution. 15. Resulting product, its industrialisation and internal replication The DVB modulator, as a result of the AE, is already industrialised as a part of the new Itelcodigital exciter for DVB-T transmission. In order to match with the time-to-market constraints, we

performed in parallel with the design of the digital processing functions using FPGA, the newframe, the new motherboard and the other boards for the complete DVB-T exciter. As an internal replication, nowadays we are performing the final test of the SFN-ASI digital board;with this optional function, the DVB-T Itelco transmitter will be operative in a Single FrequencyNetwork (SFN) environment. The DVB Modulator will be put on the market at the first quarter of 1999. The sub-units involved by industrialisation activities are the following:

Local Oscillator plug-in Description Electrical review activities in order to perform the conversions from the 4,57MHz IF to 36,15MHzIF and to the final RF frequency. The local oscillator can be locked to an external reference (e.g.GPS) to ensure correct SFN operation. Duration 20 days Labour Cost (kEUR) 3,24

RF Driver and Power Amplifier plug-ins

Description Electrical review activities in order to generate a 1W (rms) DVB-T output signal appropriate forsubsequent high power RF amplification. An integrate ALC (Automatic Level Control) circuitguarantees excellent output power stability over time and temperature variations. Duration 22 days Labour Cost (kEUR) 3,564

Frame, motherboard and other boards Description Electrical and mechanical review activities in order to perform the final integration of the completeDVB-T exciter. Duration 25 days Labour Cost (kEUR) 4,05

16. Economic impact and improvement in competitive position

FUSE 25880 - Itelco SpA Table 1

A. MARKET ANALYSIS

EXISTING PRODUCT (UHF ANALOG TX)

Sales figure 1996 1997 1998 1999 2000 2001( KECU)

Turnover product 11000 10340 8250 4950 3960 3170Cost product (per unit) 73,3 73,9 73,7 73,9 72,0 72,0Profit product (per unit) 22,0 22,2 22,1 22,2 21,6 21,6Number of products sold 150 140 112 67 55 44Product Market share 8% 8% 8% 8% 7% 7%

IMPROVED PRODUCT (DVB UHF DIGITAL TX)

Sales figure 1998 1999 2000 2001( KECU)

Turnover product 840 1820 4200 5850Cost product (per unit) 84,0 82,7 75,0 73,1Profit product (per unit) 16,8 16,5 22,5 21,9Number of products sold 10 22 56 80Product Market share 2% 2,5% 5% 7%

B. PAYBACK PERIOD

Improved product Profit up to the end of 1999 532 KECU

Project Cost 172 KECU

Payback Period = 6,1 Months( starting from June 1998)

C. TOTAL PROFIT INCREASE DUE TO AE INNOVATION(improved product profit /existing product profit)%

1998 1999 2000 2001

6.7% 24.4% 106% 184.3%

The estimated return on investment is 1000%. over the product life of 4 years. (an incrementalprofit of about 532 KECU).

Comments to table 1:

The forecast of the existing product market for the next three years (analogue transmitter) is aglobal size reduction, caused by the move to digital technology of a first-class group ofbroadcasters; during this period of time Itelco market share will be more or less the same, even ifthe decrease of the products number sold is quite clear.

The improved product global market will have a considerable increase from 1999, we anticipatereaching the same market share as the analogue during the year 2001.

As you see, in the year 2000, the analogue and digital turnover will be quite similar, the averageprices too, even if the digital market share won’t be as much as the analogue yet.

From the year 2000 on, positive sales and turnover increases are foreseen, a lot of digital productswill be available on the market and the digital terrestrial networks roll-out phase will be going onrapidly.

Main benefits arising from the AE are:

• Improved performance/cost ratio.• Presence in digital broadcasting market• Digital technology introduction• Improvement of the Company’s image all over the world• Introduction of the programmable devices design technique, with benefits in terms of

flexibility and up-grading.

The added value to customer can be summarised as follows:• A product compliant with DVB Digital Television European Standard• Improved signal reception thanks to increased noise to signal ratio.• A digital product, with all its related advantages in terms higher quality of the product

17. Summary of best practice and target audience for dissemination throughout Europe

The enterprises that could benefit from this AE can be described as follows:• High-tech SMEs with business in the telecom field and digital processing area, since the

moving from analogue to digital is becoming a highest priority of the management.• Companies with size, technical-oriented organisation and skills similar to Itelco• In general, all European companies belonging to industrial sectors classified with PRODCOME

code as 3230 Television and Radio receivers. At Italian local level about 300 enterprise in ourregion have been classified under this code.

• About 60% of the targeted industry do not use FPGA. The success of the Itelco project will beused as an example of FPGA realisation to stimulate a technological upgrade in this are. It couldalso be used in our country as an Italian example for the enterprises that belong to the sameindustrial sector.

? ITELCO is a medium enterprise. All the same size industry in Europe could be stimulated toupgrade their electronics capability following the ITELCO example.

• Companies needing a very short time to market.

The best practice of the present AE can be summarised as follows:

1. since the product implements different types of FPGA, this example can help companies willingto learn FPGA technology application.

2. The best target of the project is time to market reduction.3. It can be useful for what concerns the speeding up of the microelectronics design cycle for a

company with telecommunications expertise.4. It shows how good planning decreases drawbacks and prevents delays.5. It’s a clear example of the importance to hold the market share by increasing microelectronics

design skills.All these items confirm that the Itelco demonstrator can be successfully used to stimulatereplication at local and European level.