Digital to Analog Conversion - CppSimDigital to Analog Conversion Digital input consists of bits, D...
Transcript of Digital to Analog Conversion - CppSimDigital to Analog Conversion Digital input consists of bits, D...
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M.H. Perrott
Analysis and Design of Analog Integrated CircuitsLecture 22
Digital to Analog Conversion
Michael H. PerrottApril 22, 2012
Copyright © 2012 by Michael H. PerrottAll rights reserved.
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Outline of Lecture
Basic DAC Specifications Types of DACs (Resistive, Current, Capacitive) Impact of dynamic operation (NRZ, RZ) Sigma-Delta operation for high resolution
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Digital to Analog Conversion
Digital input consists of bits, Dk, with values 0 or 1 Analog output is either voltage or current
Key characteristics- Full scale = Vref- Resolution = Vref/2N = 1 LSB 3
D0
Vout or IoutDACD1
DN-1
Vref34
Vref14
Vref24
Vref44
000 001 111D2D1D0
1 LSB
Vout
Vout =Vref
2N(2N−1DN−1+2N−2DN−2+· · ·21D1+20D0)
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Gain and Offset Errors
Offset is most easily characterized as
Gain error is characterized either as- Error at full scale (in LSBs)- Percentage of full scale
4
Vref78
000 111D2D1D0
Vout
Voffset
Vref78
000 111D2D1D0
VoutOffset Error Gain Error
Voffset = Vout |Dk=0
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Nonlinearity
Integral Non-Linearity (INL)- Maximum deviation from the “ideal line” characterisitic
Typically specified in units of LSBs Differential Non-Linearity (DNL)
- Maximum deviation of all codes from their ideal step size of 1 LSB
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Vref78
000 111D2D1D0
VoutNonlinearity
INL
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Monotonicity
Monotonic behavior requires that stepping any code to the next code yields a step in the output that is always the same sign- Important in systems which utilize the D/A converter as
part of a feedback Non-monotonicity yields changes in the sign of the gain,
which can lead to small signal stability problems6
Vref78
000 111D2D1D0
VoutNon-Monotonic
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Binary Resistor DAC
Relies on accurate resistor ratios for good INL/DNL Issues
- Switches contribute resistance Can impact accuracy without clever design measures
- Resistors require significant area for a high resolution DAC
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Vout
CLVref
R
Vref
Gnd
2R 4R 8R
D0D1D2
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Binary Current DAC
Advantages- Switch resistance does not impact accuracy (to first
order)- Scaled current sources are readily obtained using
current mirror techniques Issues
- Likely to have higher 1/f noise than resistor based DAC- Opamp limits bandwidth, adds noise
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Vout
CLVref
RD0D1D2
Iref2Iref4Iref
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Binary Current DAC with Resistive Load
No opamp required- Useful for high speed applications
Issues- Current sources must now bear the full output range
Much harder to maintain constant current from them Cascoding takes up headroom
Can lead to code dependent nonlinearity (i.e., poor INL, distortion)
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Vout
CLR
D0D1D2
Iref2Iref4Iref
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Binary Versus Thermometer Encoding
Thermometer encoded resistor ladder provides inherently monotonic behavior
Issues for high resolution - Decoding becomes very complex - Area can be quite large
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Vout
CLVref
R
Vref
Gnd
2R 4R 8R
D0D1D2
Vout
CL
R
D0D1D2
Vref
R
R
R
Binary-to-ThermometerDecoder
Binary Thermometer
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Capacitor DAC
Uses charge re-distribution on a capacitor network to realize output voltages- Key advantage is that capacitor matching is quite good
in CMOS processes- Has become the preferred approach for low to modest
speed discrete-time ADCs11
VoutC
Vref
D0D1D2
C2C4C Φ0
DN-2DN-1
2N-1C 2N-2C
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Operational Details of Capacitor DAC
First discharge all capacitors to zero (Dk = 0, 0 = 1) Set P0 = 0 and then set Dk values
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VoutC
Vref
D0D1D2
C2C4C Φ0
DN-2DN-1
2N-1C 2N-2C
Vout =Vref
2NC
³DN−12
N−1C +DN−22N−2CN−2 + · · ·+D12C +D0C´
⇒ Vout =Vref
2N
³DN−12
N−1 +DN−22N−2 + · · ·+D12 +D0´
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Seeking Higher Resolution
Increasing the number of levels in the DAC achieves higher resolution at the cost of complexity and power- At some point, improved resolution becomes
impractical with this approach An alternative approach is to consider dithering
between levels of a coarse DAC- By averaging the output, we can obtain resolution finer
than the LSB of the coarse DAC13
D0
Vout or IoutDACD1
DN-1
000 001 111D2D1D0
1 LSB
Vout
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Sigma-Delta Modulation
Sigma-Delta dithers in a manner such that resulting quantization noise is “shaped” to high frequencies
M-bit Input 1-bitD/A
Analog Output
Input
QuantizationNoise
Digital InputSpectrum
Analog OutputSpectrum
Time Domain
Frequency Domain
Σ−Δ
Digital Σ−ΔModulator
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Linearized Model of Sigma-Delta Modulator
Composed of two transfer functions relating input and noise to output- Signal transfer function (STF)
Filters input (generally undesirable)- Noise transfer function (NTF)
Filters (i.e., shapes) noise that is assumed to be white
x[k] y[k] y[k]x[k]q[k]
r[k]
z=ej2πfT
z=ej2πfT
NTF
STF
Σ−Δ
Hn(z)
Hs(z)
1
Sr(ej2πfT)= 112
Sq(ej2πfT)= |Hn(ej2πfT)|2112
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Example: Cutler Sigma-Delta Topology
Output is quantized in a multi-level fashion Error signal, e[k], represents the quantization error Filtered version of quantization error is fed back to
input- H(z) is typically a highpass filter whose first tap value is 1
i.e., H(z) = 1 + a1z-1 + a2 z-2
- H(z) – 1 therefore has a first tap value of 0 Feedback needs to have delay to be realizable
x[k] u[k]
e[k]
y[k]
H(z) - 1
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Linearized Model of Cutler Topology
Represent quantizer block as a summing junction in which r[k] represents quantization error- Note:
It is assumed that r[k] has statistics similar to white noise- This is a key assumption for modeling – often not true!
x[k] u[k]
e[k]
y[k]
H(z) - 1
x[k] u[k]r[k]
e[k]
y[k]
H(z) - 1
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Calculation of Signal and Noise Transfer Functions
Calculate using Z-transform of signals in linearized model
- NTF: Hn(z) = H(z)- STF: Hs(z) = 1
x[k] u[k]
e[k]
y[k]
H(z) - 1
x[k] u[k]r[k]
e[k]
y[k]
H(z) - 1
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A Common Choice for H(z)
m = 1
m = 2
m = 3
Mag
nitu
de
0Frequency (Hz)
1/(2T)
8
7
6
5
4
3
2
1
0
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Example: First Order Sigma-Delta Modulator
Choose NTF to be
Plot of output in time and frequency domains with input of
00
Am
plitu
de
Mag
nitu
de (d
B)
Sample Number 200 0
1
Frequency (Hz) 1/(2T)
x[k] u[k]
e[k]
y[k]
H(z) - 1
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Example: Second Order Sigma-Delta Modulator
Choose NTF to be
Plot of output in time and frequency domains with input of
x[k] u[k]
e[k]
y[k]
H(z) - 1
Mag
nitu
de (d
B)
0 Sample Number 200 0-1
Am
plitu
de
2
1
0
Frequency (Hz) 1/(2T)
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Example: Third Order Sigma-Delta Modulator
Choose NTF to be
Plot of output in time and frequency domains with input of
x[k] u[k]
e[k]
y[k]
H(z) - 1
Mag
nitu
de (d
B)
0 0Sample Number 200
Am
plitu
de
4
3
2
1
0
-1
-2
-3Frequency (Hz) 1/(2T)
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Observations
Low order Sigma-Delta modulators do not appear to produce “shaped” noise very well- Reason: low order feedback does not properly
“scramble” relationship between input and quantization noise Quantization noise, r[k], fails to be white
Higher order Sigma-Delta modulators provide much better noise shaping with fewer spurs- Reason: higher order feedback filter provides a much
more complex interaction between input and quantization noise
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Warning: Higher Order Modulators May Still Have Tones
Quantization noise, r[k], is best whitened when a “sufficiently exciting” input is applied to the modulator- Varying input and high order helps to “scramble”
interaction between input and quantization noise Worst input for tone generation are DC signals that are
rational with a low valued denominator- Examples (third order modulator with no dithering):
Mag
nitu
de (d
B)
0 Frequency (Hz) 1/(2T)
Mag
nitu
de (d
B)
0 Frequency (Hz) 1/(2T)
x[k] = 0.1 x[k] = 0.1 + 1/1024
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Fractional Spurs Can Be Theoretically Eliminated
See:- M. Kozak, I. Kale, “Rigorous Analysis of Delta-Sigma
Modulators for Fractional-N PLL Frequency Synthesis”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 51, no. 6, pp. 1148-1162
- S. Pamarti, I. Galton, "LSB Dithering in MASH Delta–Sigma D/A Converters", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 4, pp. 779 –790, April 2007.
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MASH topology
Cascade first order sections Combine their outputs after they have passed through
digital differentiators
Advantage over single loop approach- Allows pipelining to be applied to implementation
High speed or low power applications benefit
x[k]
y[k]
r1[k]ΣΔM1[k]
y1[k]
r2[k]ΣΔM2[k]
y2[k]
u[k]
ΣΔM3[k]
y3[k]
M 1 1
1-z-1 (1-z-1)2
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Calculation of STF and NTF for MASH topology (Step 1)
Individual output signals of each first order modulator
Addition of filtered outputs
x[k]
y[k]
r1[k]ΣΔM1[k]
y1[k]
r2[k]ΣΔM2[k]
y2[k]
u[k]
ΣΔM3[k]
y3[k]
M 1 1
1-z-1 (1-z-1)2
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Calculation of STF and NTF for MASH topology (Step 1)
Overall modulator behavior
- STF: Hs(z) = 1- NTF: Hn(z) = (1 – z-1)3
x[k]
y[k]
r1[k]ΣΔM1[k]
y1[k]
r2[k]ΣΔM2[k]
y2[k]
u[k]
ΣΔM3[k]
y3[k]
M 1 1
1-z-1 (1-z-1)2
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The Issue of Intersymbol Interference
Dynamic operation of a non-return-to-zero (NRZ) DAC leads to inaccuracy due to transient effects- Transients only occur when the previous data is
different We refer to this data dependent error as intersymbol
interference Intersymbol interference especially poses a problem
when using the DAC for data communication
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Vout
CLR
D0D1D2
Iref2Iref4Iref
1 1 1 00
Clk(t)
I0I0(t)
I0(t) (ideal)
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Return-to-Zero (RZ) Signaling
Dynamic operation RZ DAC yields consistent results regardless of the pattern- Essentially, it inserts transients into every `1’ value
Issue – half the signal swing is lost
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Vout
CLR
D0D1D2
Iref2Iref4Iref
1 1 1 00
Clk(t)
I0
I0(t)
I0(t) (ideal)
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Summary
DAC structures can be implemented in a variety of ways- Resistors, currents, capacitors are all possible elements- Current-based DACS are the favorite for high frequency
operation- Capacitor-based DACS are the favorite for low to modest
frequency operation Key DAC specifications include offset, gain error, and
non-linearity- Monotonocity is an import specification for DACs used
within feedback loops Sigma-Delta modulators can be used to greatly increase
the effective resolution of a DAC Dynamic operation of the DAC can lead to error due to
intersymbol interference