DIGITAL SYSTEM DESIGN - Oakland Universityllamocca/Tutorials/VHDLFPGA/Unit 7.pdf · Digital system...

Daniel Llamocca

DIGITAL SYSTEM DESIGNVHDL Coding for FPGAs

Unit 7

✓INTRODUCTION TO DIGITAL SYSTEM DESIGN:

▪ Digital System Components

▪ Use of generic map to map parameters.

▪ Example: Digital Stopwatch

▪ Example: Lights Pattern

▪ Embedding counters and registers in ASM diagrams.

Daniel Llamocca

✓ DIGITAL SYSTEM DESIGN▪ Digital System Components:

▪ Finite State Machine, Datapath circuit

▪ Design Steps: Circuit Design, VHDL coding, Synthesis, Simulation, Place and Route (also pin assignment), and FPGA Programming and Testing.

FINITE STATE MACHINE

resetn

clock

Inputs

Outputs

CONTROL CIRCUIT

DATAPATH CIRCUIT

Daniel Llamocca

✓ Parameterized components:▪ Digital systems include a large number of components. The most

common ones are registers, shift registers, and counters. To accelerate development time and to avoid issues with lower-level components, it is strongly recommended to use fully-tested parameterized components (VHDL for FPGAs Tutorial – Unit 5). To indicate parameters, see ‘use of generic map’ in the following slides.

▪ n-bit register with enable and synchronous clear: my_rege

▪ Counter modulo-N (COUNT=N) with enable and synchronous clear: my_genpulse_sclr

▪ n-bit parallel access (right/left) register with enable and synchronous clear: my_pashiftreg_sclr

din

E

sclr

s_l

shiftout

resetn

din

E

sclr

s_l

dout

clock

PARALLEL ACCESS SHIFT REGISTER

D

E

sclr

Q

resetn

D

E

sclr

Q

clock

REGISTER

E

sclr

Q

resetn

E

sclr

Q

clock

COUNTER

zz

Q

D N DIRCOUNT

N

Daniel Llamocca

✓EXAMPLE: STOPWATCH▪ The Stopwatch that counts in increments of 1/100th of a second.

Circuit design and VHDL implementation.

▪ Inputs: pause, resetn, clock

▪ Outputs: Count on four 7-segment displays

▪ Target Board: DIGILENT NEXYS-4 DDR Board

hundredths of a secondseconds

DIGITAL

CIRCUITclock

resetn

pause

Daniel Llamocca

▪ The figure depicts a generic modulo-N counter, where 𝑁

resetn

Q

clock

nCOUNTERmodulo-N0 to N-1 z

E

clock

resetn

Q 0000

z

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001

0 0 1 2 3 4 5 6 7 8 9 0 1

TIMING DIAGRAM - COUNTER MODULO 10 (N=10, n = 4)

✓EXAMPLE: STOPWATCH▪ Datapath design: We need four counters. Tree counters modulo-10

and one counter module-6.

BCD

counter

E

z

BCD

counter

E

z

BCD

counter

E

z

Counter

modulo-6

E

z

4 4 4 4

resetn

clock

0-5 0-9 0-9 0-9

Daniel Llamocca

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity my_bcdcount is

port ( clock, resetn, E: in std_logic;

Q: out std_logic_vector(3 downto 0);

z: out std_logic);

end my_bcdcount;

architecture bhv of my_bcdcount is

signal Qt: std_logic_vector(3 downto 0);

begin

process (resetn,clock,E)

begin

if resetn = '0' then Qt <= "0000";

elsif (clock'event and clock='1') then

if E = '1' then

if Qt = "1001"' then

Qt <= "0000";

else

Qt <= Qt + "0001";

end if;

end if;

end if;

end process;

z <= '1' when Qt = "1001" else '0';

Q <= Qt;

end bhv;

✓ DIGITAL COUNTER DESIGN

▪ Counters are usually designed as State Machines. However, for different counts, we need a different state machine. Moreover, if the count is large, the FSM gets intractable.

▪ More efficient manner: Think of them as accumulators. This way, the VHDL code is easier to read and modify (if we require a different count).

▪ Example: BCD counter

Daniel Llamocca

✓ COUNTER DESIGN: PARAMETRIC CODE

▪ The previous VHDL code allows for easyparameterization of counters with arbitrary counts.

▪ Parametric VHDL code: The following VHDL code has a parameterCOUNT. This is the ‘my_genpulse.vhd’ code (Unit 5).

library ieee;



use ieee.std_logic_arith.all;

use ieee.math_real.log2.all;

use ieee.math_real_ceil.all;

entity my_genpulse is

generic (COUNT: INTEGER:= 10);

port ( clock, resetn, E: in std_logic;

Q: out std_logic_vector(integer(ceil(log2(real(COUNT))))-1 downto 0);

z: out std_logic);

end my_genpulse;

architecture bhv of my_genpulse is

constant nbits:= INTEGER:= integer(ceil(log2(real(COUNT))));

signal Qt: std_logic_vector(nbits - 1 downto 0);

...

Daniel Llamocca

...

begin

process (resetn,clock,E)

begin

if resetn = '0' then Qt <= (others => '0');


if E = '1' then

if Qt = conv_std_logic_vector(COUNT-1,nbits) then

Qt <= (others => '0');

else

Qt <= Qt + conv_std_logic_vector(1,nbits);

end if;

end if;

end if;

end process;

z <= '1' when Qt = conv_std_logic_vector (COUNT-1, nbits) else '0';

Q <= Qt;

end bhv;

✓ COUNTER DESIGN: PARAMETRIC CODE

▪ This parametric counter is not only useful togenerate pulses, but also to generate counters with any arbitrarycounts.

Daniel Llamocca

BCD

counter

E

z

BCD

counter

E

z

BCD

counter

E

z

Counter

modulo-6

E

z

4 4 4 4

resetn

clock

pause

clock

resetn

QA

zA

0 0 1 2 3 4 5 6 7 8 9 0 1

QAQBQCQD

pause

2 3 3 4 5

QB 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1

zAzBzC

✓EXAMPLE: STOPWATCH▪ Datapath design: A cascade interconnection allows the counters to

behave as desired.

Daniel Llamocca

✓ EXAMPLE: STOPWATCH▪ ‘pause’ input: If the user asserts this input, the count must freeze.

This is achieved by using not(pause) to enable all the counters.

▪ Note that it is possible to come up with this circuit by designing an FSM that controls the four enable inputs of the counters.

▪ Timing diagram: note what needs to happen so that the third counter (QC) increments its count.

clock

zA

pause

QB 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 0 0

QA 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

zB

QC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Daniel Llamocca

✓STOPWATCH DESIGN▪ NEXYS-4 Board: 100 MHz clock. Thus, the

counter QA will increment its count every 10 ns.

▪ We want QA to increment its count every 0.01s (10 ms).

▪ Straightforward solution: Change the input clock to 100 Hz (period 10 ms). This can be a hard problem if precise input clock is required. If we modify the frequency using counters, we might have FPGA clock skew since the 100 Hz clock will not go in the clock tree (among other problems).

▪ Efficient solution: We use the counter that generates a pulse every 10 ms. The output ‘z’ is then connected to every enable input of the counters. This way, we get the same effect as modifying the clock frequency to 100 Hz.

▪ The pulse is of duration of the input clock period (10 ns). To generate a pulse every 10 ms, we need a counter that counts up to (10ms/10ns) -1 = 106 -1. Note that our generic counter with COUNT=106 allows for a quick implementation of this circuit.

Daniel Llamocca

✓STOPWATCH DESIGN▪ Datapath circuit: The figure shows the stopwatch with the

counter up to 106 (named 0.01s counter).

▪ Note how the output ‘z’ of the 0.01s counter is now connected to all the enables in the counters. This way we make sure that every transition in the counter only occurs every 0.01 s (10 ms)

BCD

counter

E

z

BCD

counter

E

z

BCD

counter

E

z

Counter

modulo-6

E

z

4 4 4 4

Counter

(0.01s)z

resetn

clock

Epause

z

Daniel Llamocca

✓STOPWATCH DESIGN▪ Datapath circuit: Final system with four 7-segment decoders

so that the counter outputs can be seen in the displays.

BCD

counter

E

z

BCD

counter

E

z

BCD

counter

E

z

Counter

modulo-6

E

z

4 4 4 4

Counter

(0.01s)z

resetn

clock

Epause

z

7-segment

Decoder

7-segment

Decoder

7-segment

Decoder

7-segment

Decoder

7 777

Daniel Llamocca

✓STOPWATCH DESIGN▪ NEXYS-4 Board: It has eight 7-segment displays, but all the

displays share the same inputs. We can also enable (negative logic) a particular 7-segment display via the common anode (see Seven Display section in NEXYS4 datasheet).

▪ Why do we have then eight 7-seg displays, if apparently all of them will display the same pattern?

▪ OUTPUT SERIALIZATION: With an enable for each 7-segment display, we can use one 7-segment display at a time. In order for each digit to appear bright and continuously illuminated, we illuminate each digit for only 1ms every 4 ms.

▪ We need only one 7-segment decoder, a Multiplexor, and an FSM that control the selector of the multiplexor.

▪ If we want the multiplexor selector to transition only 1 ms every 4 ms, we connect the output ‘z’ of a new counter (to 0.001s, COUNT = 105) to the enable input of the FSM.

▪ In our design, we only use four 7-segment displays.

Daniel Llamocca

✓STOPWATCH DESIGN▪ Final Design: Datapath Circuit + FSM

BCD

counter

E

z

BCD

counter

E

z

BCD

counter

E

z

Counter

modulo-6

E

z

4 4 4 4

7 7 7 7

Counter

(0.01s)

z

resetn

clock

Epause

0

2

2-to-4decoder

s

4

EN FSM

7-segment

Decoder

123

EN(3)

z

EN(2) EN(1) EN(0)

Counter

(0.001s)

z

E

1

S1

resetn=0

s 00

s 01

S2

s 10

S3

s 11

S4

E

E

E

E

1

1

1

0

0

0

0

Daniel Llamocca

▪ Xilinx Vivado Project:

▪ VHDL code: Instantiation (port map, generic map). For VHDL code style, see other units in VHDL for FPGAs Tutorial.

▪ Simulation: Testbench. If 0.01s counter is omitted and z = E, we can easily simulate the circuit.

▪ Place-and-Route (pin assignment)

▪ FPGA programming and testing

✓STOPWATCH DESIGN▪ FSM Timing Diagram:

clock

resetn

s 00

E

00 00 01 01 01 01 10 10 10 10 11 11

state S1 S1 S1 S2 S2 S2 S2 S3 S3 S3 S3 S4 S4

➢ Code (.zip file):

dig_stopwatch.vhd, my_genpulse.vhd, sevenseg.vhd, tb_dig_stopwatch.vhd,dig_stopwatch.xdc

http://www.secs.oakland.edu/~llamocca/Tutorials/VHDLFPGA/Vivado/Unit_7/dig_stopwatch.zip

Daniel Llamocca

✓USE OF generic map▪ Digital system design: many VHDL components available, some as

parameterized VHDL code (for re-usability). So, when instantiating these components into a top-level file, we both map the signals (port map) and the parameters (generic map).

▪ StopWatch design: We need to instantiate six counters. Parametric VHDL counter: my_genpulse.vhd. We have 3 counters modulo-10, 1 counter

modulo-6, 1 counter modulo-106, and 1 counter modulo-105.

▪ Here, we must use generic map (see dig_stopwatch.vhd. We first declare my_genpulse.vhd in the top file:

...

architecture struct of dig_stopwatch is

...

component my_genpulse

generic (COUNT: INTEGER:= (10**8)/2);

port (clock, resetn, E: in std_logic;

Q: out std_logic_vector(integer(ceil(log2(real(COUNT))))-1 downto 0);

z: out std_logic);

end component;

...

begin

...

We copy whatis in the entity of my_genpulse.vhd

Daniel Llamocca

✓USE OF generic map▪ The port map statement takes care of interconnecting the signals.

▪ The generic map statement maps the parameters. More than one parameter can be mapped. my_genpulse only has one parameter:

generic map (parameter name in my_genpulse => parameter value in top file).

▪ Here, we map 5 counters, each with a different count.

▪ If parameters are not mapped, the parameter values in the component declaration inside the architecture are assigned. This is a bad coding style: we might need to use a component more than once in the design, each time with different parameters.

...

gz: my_genpulse generic map(COUNT => 10**6) -- modulo-106 counter

port map(clock => clock, resetn =>resetn, E => npause, z => z);

g0: my_genpulse generic map(COUNT => 10) -- BCD counter

port map(clock => clock, resetn =>resetn, E => z, Q=>Q0,z=>z_0);


port map(clock => clock, resetn =>resetn, E =>E_1,Q=>Q1,z=>z_1);



g3: my_genpulse generic map(COUNT => 6) -- modulo-6 counter


...

end struct;

Daniel Llamocca

✓EXAMPLE: LIGTHS PATTERN▪ Configurable lights’ pattern generator: sel: selects pattern, stop:

freezes the pattern. X: selects the rate at which lights’ pattern change (every 1.5, 1.0, 0.5, or 0.25 s)

sel

00

01

10

11

segs[7..0] :

?clock

resetn

28 segs

2

sel

x

stop

7 6

5

4

0

1

2 3

Daniel Llamocca

✓EXAMPLE: LIGTHS PATTERN▪ Entire System:

FINITE STATEMACHINE

resetn

Q

clock

??

counter (1.5s)

z

Q ??

counter (1.0s)

z

Q ??

counter (0.5s)

z

FINITE STATE MACHINE

stop

8

Q ??

counter (0.25s)

z

0

1

2

3

x

2

E

70

1

1-to-2decoder

7

buf buf(1) buf(0)

sel

2

s

x = 00 → Lights change every 1.5 s




On the NEXYS4, only one 7-segmentdisplay can be used at a time

Counter

(0.001s)

z

E

D QE

dseg

7Esg

8

Daniel Llamocca

✓EXAMPLE: LIGTHS PATTERN▪ FSMs:

S1resetn=0

1

0E

sel

S2a

1

0

E

S3a

1

0

E

S4a

1

0

E

S2b

1

0

E

S3b

1

0

E

S4b

1

0

E

S2c

1

0

E

S3c

1

0

E

S4c

1

0

E

S2d

1

0

E

S3d

1

0

E

S4d

1

0

E

00 11

01 10

dseg00000111, Esg1 dseg00000101, Esg1 dseg00010001, Esg1 dseg00110011, Esg1




S5a

1 0

Edseg01110000, Esg1

S6a

10E dseg11100000, Esg1

S7a

1 0

Edseg11000001, Esg1

S5d

1

0

E

S6d

1

0

E

dseg10000111, Esg1

dseg01111000, Esg1S8a

1

0

E

dseg10000011, Esg1

S1

resetn=0

s 0

s 1

S2

E

E

0

0

1

1

➢ lights_pattern.zip:

lights_pattern.vhd,

my_genpulse.vhd,

my_rege.vhd,

tb_lights_pattern.vhd,

lights_pattern.ucf

Daniel Llamocca

✓EMBEDDING COUNTERS ANDREGISTER IN ASM diagrams

▪ FSMs usually require counters and registers for proper control. In VHDL code, this requires integrating the fsm description with port map/generic map to instantiate the counters and registers.

▪ Example: digsys_ex: An FSM, a counter, a register, and a shift register.

▪ Asserting EQ or sclrQ can update the counter output Q, which can only be updated (Q0, QQ+1) at the clock edge. For example: after asserting EQ1, we must wait until the clock edge for QQ+1. For the register, asserting ED 1 means that QD D on the next clock cycle.

Shift Register:

ES 1: After this signal is asserted, the shift register shifts data on the next clock cycle.

ES 1, LS 1: After these 2 signals are asserted, the shift register will load parallel data on the next clockcycle.

resetn=0

0

1

SCLK 0

zQ

S1

S2

EQ 1

EQ, sclrQ 1

ED, ES, LS 1

SCLK 1

0

1

zQEQ 1

ES 1

EQ, sclrQ 1

(Q 0)

(Q Q+1)

(Q Q+1)

(Q 0)

FSM

FSM

SCLK

Q3

LEFT

dout

4

din

E L

D

E

Q4

4

4

ED

0

4

Q

counter

0 to 7

E

sclr z zQ

EQ

sclrQ

QD

QSES

LS

D

S

(shift QS)

(QD D, QS S)

Daniel Llamocca

✓EMBEDDING COUNTERS ANDREGISTER IN ASMs

▪ Timing diagram: digsys_ex.

1000010010101101

clk

resetn

D

S

EQ

sclrQ

Q

zQ

state

SCLK

ED

ES

LS

QD

QS

S1S1 S1 S1 S1 S1 S1 S1 S1 S2 S2 S2 S2 S2 S2 S2 S2 S1 S1

1100 0101 1001 0101 1011

0110 1101 1001 1100 0111

60 0 1 2 3 4 5 7 0 1 2 3 4 5 6 7 0 1

0000 0101

0000 0000

➢ dig_sys_ex.zip: my_digsys_ex.vhd,

my_genpulse_sclr.vhd, my_rege.vhd,

my_pashiftreg.vhd, tb_digsys_ex.vhd.

Daniel Llamocca


▪ Alternative coding style: we can embed counters and registers inside the ASM description in VHDL (no need of port map). Note that the resulting circuit is not technically an FSM, since now some of the outputs are registered. For digsys_ex, only SCLK is now a combinational output.

▪ Procedure: Include the statements to infer counters and registers in the State Transitions process. We need to clear their outputs when resetn=0.

▪ New circuit: It is functionally the same as the previous circuit, but the representation is different.

resetn=0

0

1

SCLK 0

Q=7

S1

S2

Q Q+1

Q 0, QD D,

QS S

SCLK 1

0

1

Q=7Q Q+1

QS QSx2

Q 0

FSMemb

Technically,not an FSM

SCLK4D

4QSFSMemb

These statementsare executed on the

clock edge

4

QD S

4

Updated ASM Diagram (FSMemb): It is a bit misleading. The statements indicating updates to the counter, register, and shift register outputs do not take effect immediately, but rather on the immediate clock edge.

So, even though this representation can be helpful, it can also be confusing.

Daniel Llamocca


▪ VHDL code: Use this coding style sparingly, as it is difficult to debug when there are too many inferred counters and registers.

▪ The output signals QD, QS, sclk, behave exactly the same as in the original digsys_ex circuit (the one with FSM and port map/generic map).

library ieee;



entity digsys_ex is

port ( clock, resetn: in std_logic;

D,S: in std_logic_vector(3 downto 0);

QD,QS: out std_logic_vector(3 downto 0);

sclk: out std_logic);

end digsys_ex;

architecture bhv of digsys_ex is

type state is (S1, S2);

signal y: state;

signal Q: integer range 0 to 7;

signal QSt: std_logic_vector(3 downto 0);

begin

...

Note that Q is defined as an integer to simplify coding.

QSt: we need this auxiliary signal as we cannot feedback the output QS back to the circuit (we need this for shifting).

➢ dig_sys_exp.zip:

my_digsys_ex.vhd,

tb_digsys_ex.vhd.

Daniel Llamocca


Note how easy it is to update a counter, a register, or shift register.

Do not forget to assign the values on reset.

This avoids having to use port map instructions.

...

Transitions: process (resetn, clock)

begin

if resetn = '0' then -- asynchronous signal

y <= S1; QD<="0000"; Q <= 0; QSt<="0000" -- values on reset


case y is

when S1 =>

if Q=7 then y<=S2; Q<=0; QD <= D; QSt <= S;

else y<=S1; Q <= Q+1; end if;

when S2 =>

if Q=7 then y<=S1; Q<=0;

else

y<=S2; Q <= Q+1; QSt(0) <= '0';

QSt(3 downto 1) <= QSt(2 downto 0);

end if;

end case;

end if;

end process;

Q <= QSt;

Outputs: process (y,Q)

begin

sclk <= '0';

case y is

when S1 =>

when S2 => sclk <= '1';

end case;

end process;

end bhv;

DIGITAL SYSTEM DESIGN - Oakland Universityllamocca/Tutorials/VHDLFPGA/Unit 7.pdf · Digital system...

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Transcript of DIGITAL SYSTEM DESIGN - Oakland Universityllamocca/Tutorials/VHDLFPGA/Unit 7.pdf · Digital system...