Digital System Design Lecture 11: Field-Programmable SOC
Transcript of Digital System Design Lecture 11: Field-Programmable SOC
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Modern Systems
Very ComplexLimitations for implementation
HW: high performance, low power SW: flexible
Use mixed HW/SW implementation
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HW/SW
Basic ElementsMicroprocessorASICBus (Interconnection)
Basic ProblemsHW/SW partitioningHW/SW co-simulationDesign trade-offsSeparate design flow for SW and HW
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System on Chip (SoC)
A complex IC that integrates the major functional elements in a single chip using IP (Intellectual Property) blocks
(Programmable) ProcessorsControllersSignal processorsMemory
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Why SoC?
Functional integrationTighter design scheduleLimited product life-cycleBandwidth and performancePower consumptionTechnology scalingCost down
Engineering design perspective:
Shrinking product design schedulesLack of time for product iterationsComplex interoperability standardsDemand for higher performanceDemand for smaller sizesDemand for lower powerMultiple conflicting objectives
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Main Applications
Set-top box: mobile multimedia system, base station for the home local-area network.Digital PCTV: concurrent use of TV, 3D graphics, and Internet services.Set-top box LAN service: wireless home-networks, multi-user wireless LAN.Navigation system: steer and control traffic and/or goods transportation.
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Programmable SoCs
CSoc (Configurable SoC)TriscendAtmelQuickLogic
SoPC (System on Programmable Chip)
AlteraXilinx
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Triscend E5 CSoC
Pioneer in programmable SoCsIntroduced E5 chips in 1999Uses 8032 controller
performance –accelerated 8051 microcontroller
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Triscend E5 CSoC (cont.)
Standalone operation from a single external memory (code + configuration)Up to 64Kbytes of on-chip, dedicated system RAMUp to 3200 Configurable System Logic (CSL) cells (up to 40,000 "ASIC" gates)Power-down and power-management modes (low power mode consumption under 100 µA)Two dedicated DMA ChannelsOn-chip breakpoint unit provides sophisticated debugging capabilityOffers real-time debugging for HW/SW co-verification
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Triscend A7 CSoC (cont.)
Memory interface unitFlexible, glue-less interface to external memories (ROM, EEPROM, FLASH, SRAM, and SDRAM)8-bit, 16-bit and 32-bit support
4-channel DMA controllerIn-system breakpoint/debug unitPower-down and power management modesCSL cells can be configured as memory
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Atmel FPSLIC
Introduced in 1999Equipped with its own 8-bit RISCProvides security by integrating configuration memory in deviceSoftware tool provides HW/SW co-simulation capability.
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QuickLogic QuickMIPS
Based on well-known 32-bit MIPS RISC processorProcessor core runs at 133 to 175MHz (0.25 and 0.15 micron processes)The FPGA block (called “High-performance programmable fabric” by QuickLogic) offers more than 400,000 gates, consisting of:
2000 logic cells83 K bits of dual-port SRAM18 Embedded Computational Unit (ECU)
Contains Configurable Logic Analysis Module (CLAM™), functioning as on-chip logic analyzer to debug hardware implemented on the FPGA part
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Altera Excalibur (Nios Family)
Processor is embedded on an APEX20k device
Takes only 2% of chip area
GNUPro C compiler is used for software programmingQuartus is used for hardware design and implementation
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Altera Excalibur (ARM-Based Family)
Used ARM922T 32-bit RISC processorBuilds upon features of the APEX 20KE family, with up to 1,000,000 gates
Harvard cache architecture with separate 8-Kbyte instruction and 8-Kbyte data cachesInternal single-port SRAM up to 256 Kbytes- Internal dual-port SRAM up to 128 KbytesExternal SDRAM 133-MHz data rate (PC133) interface up to 512 Mbytes External dual data rate (DDR) 266-MHz data rate (PC266) interface up to 512 MbytesExternal flash memory in 4 banks of up to 32 Mbytes eachSeveral on-chip peripherals including ETM9 embedded trace module, interrupt controller, UART, timer, and watchdog timer