Digital System Design by Dr. Shoaib Ahmed khan
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Transcript of Digital System Design by Dr. Shoaib Ahmed khan
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Introduction to programmable devices
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History of programmable logic devices
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Complex Programmable Logic Devices(CPLDs)
Design can run upto 200MHz
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Xilinx devices
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Spartan-3E Family overview
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Spartan 6 family
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Spartan 3e
I/O block
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I/O capabilities
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I/O capabilities
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Input delay functions
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I/O block
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I/O block
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Output DDR
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Input DDR
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BLOCKRAM
One block equals 18Kbits Supports dual port structure Four data paths
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Port aspect ratios
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BLOCKRAM Symbol
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Modes of operation
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Write first
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Read first
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No change
Introduction to programmable devicesHistory of programmable logic devicesSlide Number 3Complex Programmable Logic Devices (CPLDs)Slide Number 5Slide Number 6Xilinx devicesSpartan-3E Family overviewSpartan 6 familySlide Number 10Slide Number 11Slide Number 12Slide Number 13Slide Number 14Spartan 3e I/O blockI/O capabilitiesI/O capabilitiesInput delay functionsI/O blockI/O blockSlide Number 21Output DDRInput DDRBLOCKRAMPort aspect ratiosBLOCKRAM SymbolModes of operationWrite firstRead firstNo change