Digital Radio Receiver Amit Mane System Engineer.
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Transcript of Digital Radio Receiver Amit Mane System Engineer.
![Page 1: Digital Radio Receiver Amit Mane System Engineer.](https://reader036.fdocuments.us/reader036/viewer/2022081506/56649e625503460f94b5d8b2/html5/thumbnails/1.jpg)
Digital Radio Receiver
Amit ManeSystem Engineer
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Introduction
• Virtually all digital receivers perform channel access using DDC
• The desired channel is translated using the digital mixer comprised of multipliers and DDS
• The sample rate is then adjusted to match the channel bandwidth
– CIC filter
– Two poly phase decimators
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Introduction
• The functions performed in the system are – Waveform synthesis (DDS)
– Complex multiplication
– Multirate filtering
• The overall sample rate change of the DDC is 120
• The DDS mixer has a SFDR of 102 dB
• The data rate can be upto 208 MHz
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Introduction
• Innovative DRR System requires – One Quadia
– Two UWBs
• Number of channels implemented = 40
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Complete System
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Block diagram
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Digital Receiver Block Diagram
A
10 channel
s of I/Q @
1.0833MSPS
16-bit
Clock circuitry
A/D12-bit
130/208 MSPS
A/D12-bit
130/208 MSPS
A
B
ClkCIC
30:1
NCO
MixerA/D Mux
RegistersA/D input select
Mixer FreqRev Code
StatusGainTest
20 channels of I/Q @ 4.33 MSPS
32--bit
J4Link
UWB1 of 2
CommandChannel
1 of 20 channels
A/D Intf
A/D Intf
Gain
PCI FPGA
DDR RAM16Mx16
DSP
Quadia Logic1 of 2
DSP
CFIR2:1
Overflowdetect
1 of 20 channels
Interrupts
Interrupts
Triggering
Spectral
invert
Register Spectral Inversion
20-bit
TestMux
TestGenerator
TestMux
RegisterTest Controls
2-bit
Dual QueueVFIFO
FIFO
Register Rev Codes
StatusRegister DCMs locked
Clock DCMIn = DSP1 EMIF Clk
Out = DSP1 EMIF Clk
Clock DCMIn = DSP2 EMIF Clk
Out = DSP2 EMIF Clk
DSP1 Registers
DSP2 Registers DRR FIFO Thresh
J4 link
Reset
Data Flow
Controller
Overflowdetect
FIFO
FIFO
10 channel
s of I/Q @
1.0833MSPS
16-bit
FIFO
PFIR2:1
TestGenerator
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UWB
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Filter Guide
Fs / 2=32500kHz
Fpass= 490kHz
Fstop1= 541.666kHz
Fstop2= 1350kHz
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MATLAB Development System
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DDC Frequency Response
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MATLab SimuLink Development
• MATLab and Simulink used with Xilinx System Generator
• Simulink gateways provide connection to physical hardware and connect with Framework Logic
• End-to-end simulation under MATLab
• JTAG link allows real hardware to be tested from MATLab environment
• System Generator links Xilinx tools for chip design
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Using Simulink and System Generator
• Simulink Block libraries are used to draw the system• Innovative BSP provides blocks for UWB components
• Simulink blocks for DSP, data generation and viewing
• Xilinx System Generator links all blocks
Starting a new design!
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Simulink Libraries
• Board Support Package for CS includes hardware and signal processing components
• A/Ds, J4, DDCs ....
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SimuLink Block Diagram
• The top level design has the Xilinx System Generator block for integration with logic tools
Top Level Design
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Xilinx System Generator Integrates with Simulink
• Compiling and fitting the design is done directly from the Simulink environment
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Design Using Simulink Blocks and Functions
• Large libraries of DSP and logic function may be directly used• Drag-n-drop from Simulink libraries
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Validating the Design
• Validate the design by including the hardware in the Simulink • Hardware in the loop testing using JTAG
• Bit-true and cycle-true testing
The Real Hardware
Observe and analyze real data inside Simulink
Flow data from Simulink through the hardware and back to Simulink
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Design Testing using Simulink
• Run real-time or Simulink test data through the actual design
Execution Control
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VHDL Development Tools Flow
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Quadia Application Logic Simulation
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Multiple Channel on DSP 0
Ten Channels per DSP
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Multiple Channel Operation
DSP 0
DSP 1
DSP 2
DSP 3
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Spectral Inversion Testing
32.51 MHz Input32.52 MHz Tunefs = 129.843 MHz
Before Spectral Inversion...
9.7 kHz
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32.51 MHz Input32.52 MHz Tunefs = 129.843 MHz
After Spectral Inversion...
Spectral Inversion Testing
531 kHz
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Thank you !