Digital Logic & Design Vishal Jethva Lecture 13 SVBITEC.WORDPRESS.COM.
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Transcript of Digital Logic & Design Vishal Jethva Lecture 13 SVBITEC.WORDPRESS.COM.
Recap
Functions having multiple outputs Comparator Quine-McCluskey Method (two variations) Odd-Prime Number checker circuit
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
Odd Prime Number (table1)Minterm A B C D E
1 0 0 0 0 1
3 0 0 0 1 1
5 0 0 1 0 1
7 0 0 1 1 1
11 0 1 0 1 1
13 0 1 1 0 1
17 1 0 0 0 1
19 1 0 0 1 1
23 1 0 1 1 1
29 1 1 1 0 1
31 1 1 1 1 1SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
Odd Prime Number (table2)Minterm A B C D E used
1 0 0 0 0 1 3 0 0 0 1 1 5 0 0 1 0 1 17 1 0 0 0 1 7 0 0 1 1 1 11 0 1 0 1 1 13 0 1 1 0 1 19 1 0 0 1 1 23 1 0 1 1 1 29 1 1 1 0 1 31 1 1 1 1 1 SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
Minterms Variable removed used
1,3 2 1,5 4 1,17 16 3,7 4 3,11 8
3,19 16 5,7 2 5,13 8
Odd Prime Number (table3)
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
Minterms Variable removed used
17,19 2 7,23 16 13,29 16
19, 23 4 23,31 8
29,31 2
Odd Prime Number (table3)
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
Minterms Variable removed used
1,3,5,7 2,4
1,3,17,19 2,16
3,7,19,23 4,16
Odd Prime Number (table4)
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Odd Prime Number (table5)
DECA
EDCA
EDBC
ACDE
ABCE
EBA
ECB
DEB
1 3 5 7 11 13 17 19 23 29 31
x x
x x
x x
x x
x x
x x x x
x x x x
x x x x
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
Combinational Logic
Implementation of SOP using AND-OR Implementation of POS using OR-AND
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
SOP Implementation
NOTGatelevel
ANDGatelevel
OR Gatelevel
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
POS Implementation
NOTGatelevel
OR Gatelevel
ANDGatelevel
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
Design and Implementation of Digital Circuits
Function Table Simplification of Expression Implementation
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
Adjacent 1s Detector Circuit
SOP Implementation Directly from function table
Simplified implementation Implementation using NAND gates
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
Adjacent 1s Detector Function
Input Output Input Output
A B C D F A B C D F
0 0 0 0 0 1 0 0 0 0
0 0 0 1 0 1 0 0 1 0
0 0 1 0 0 1 0 1 0 0
0 0 1 1 1 1 0 1 1 1
0 1 0 0 0 1 1 0 0 1
0 1 0 1 0 1 1 0 1 1
0 1 1 0 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1
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SOP Expression Simplification
AB\CD 00 01 11 10
00 0 0 1 0
01 0 0 1 1
11 1 1 1 1
10 0 0 1 0
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
POS Implementation Directly from function table
Simplified Implementation Implementation using NOR Gates
Adjacent 1s Detector Circuit
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
POS Expression Simplification
AB\CD 00 01 11 10
00 0 0 1 0
01 0 0 1 1
11 1 1 1 1
10 0 0 1 0
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
Operation of Circuit
Represented through a timing diagram Timing diagram of 8 time intervals Each interval representing a new input
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
Operation of Circuit
A
B
C
D
1
2
3
F
t0 t1 t2 t3 t4 t5 t6 t7 t8
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Active low/high inputs/outputs
Active output state represented by 1 or 0 Active input state represented by 1 or 0 A bubble at output represents active low
output A bubble at input represents active low
input
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM
Active low/high inputs/outputs
AND Gate OR Gate
NAND Gate NOR Gate
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Operation of Circuit
A
B
C
D
1
2
3
F
t0 t1 t2 t3 t4 t5 t6 t7 t8
SVBITEC.WORDPRESS.COMSVBITEC.WORDPRESS.COM