Digital Logic Design

Lecture # 3University of Tehran

Outline Review of Lecture #2 Number Systems

1’s Complement System Binary Coded System (BCD) ASCII Code System

Overflow Designing an Overflow Detector Structure of NMOS and PMOS Transistors Designing Logical Gates Using

Transistors

Review of Lecture #2 In the last session, we covered three types of

coding (representation) in our look at different number systems: Binary System, Sign and Magnitude System and 2’s Complement System.

Quote: The 2’s Complement System was preferred due to it’s easier arithmetic:

A – B = A + (-B)

0 0 0 0 1 1 1 0

(+ 52)

(+ 14)

0 0 1 1 0 1 0 0+

0 1 0 0 0 0 1 0

1 1 0 0 1 1 0 0

1 1 1 1 0 0 1 0+

1 0 1 1 1 1 1 01

(- 52)

(- 14)

Review of Lecture #2 (continued…)

Note: The 2’s complement system is unbalanced, meaning that there is always one more negative number represented than the positive numbers. In the 2’s complement system with 4 bits, numbers range from -8 to +7, and there’s no representation for +8.

0 0 1 1 0 1 0 0

1 1 1 1 0 0 1 0+

0 0 1 0 0 1 1 01

(+ 52)

(- 14)

1 1 0 0 1 1 0 0

0 0 0 0 1 1 1 0+

1 1 0 1 1 0 1 0

(- 52)

(+ 14)

Review of Lecture #2 (continued…)

0 0 0 1 1

0 0 1 0 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6

0 1 1 1 71 0 0 1 -71 0 1 0 -61 0 1 1 -51 1 0 0 -41 1 0 1 -31 1 1 0 -21 1 1 1 -1 0 0 0 0 0

1 0 0 0 -8

Number Systems

1’s Complement System Binary Coded System (BCD) ASCII Code

1’s Complement System This system was more widely used historically.

Unlike the 2’s complement system, this system is balanced.

When 1’s complementing a number, we simply change the value of each bit in the representation.

0 0 0 0 0+

0 0 0 0 0-

0 0 0 1 1

0 0 1 0 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6

0 1 1 1 71 0 0 1 -71 0 1 0 -61 0 1 1 -51 1 0 0 -41 1 0 1 -31 1 1 0 -21 1 1 1 -1

1’s Complement System (continued…) It’s main setback is that it doesn’t perform as

well as the 2’s complement system in arithmetic operations. This is because the results need adjusting after addition and subtraction.

In order to adjust the results of addition and subtraction, it is necessary to add carry with the result if the operation has had a carry. Example:00101011

- 00001101 + 1111001000101011

0001110111

00011110

carry

+

negating

Binary Coded System (BCD) Number system are not always used for

arithmetic. Thus a number system such as BCD that could represent digits separately would give a positive state of thought in some cases.

An example for the case mentioned above can be viewed in storage of phone numbers where we may need to have quick looks at some particular digits in an application. Using the number systems mentioned so far to achieve this would be rather unsatisfactory.

BCD (continued…) Here, instead of binary representation of the

whole number, we represent each digit of the decimal number in binary code. Using this process, we can easily distinguish between decimal digits in our finally binary represented number if needed.

The main problems with this system would be in the arithmetic arena which we had overlooked in the first place. We also have easier conversions in the BCD form but are using up more memory to store our numbers.

BCD (continued…) In this number system we need to be able to

represent numbers from 0 through 9 for which we use 4 bit numbers from 0000 through 1001.

ASCII Code System In some application storing text is the most

important of all. The ASCII code is used for this mean.

The digit 0 through 9, lowercase and uppercase letters all have specific codes in this system.

Today, an extended ASCII table is also used alongside the basic one which contains the codes of foreigner letters.

ASCII Code System (continued…) 8 bit codes are used to represent the ASCII

codes, where the leftmost digit specifies which table a specific code belongs to. Codes starting with 1 are from the extended ASCII table and those starting with 0 belongs to the basic one.

Special characters are also included in the ASCII code range. It’s also true about the control characters.

ASCII Code System (continued…) Control characters (first 2 columns) are not

printable and only perform particular actions when used. For instance:

BEL: The printer beeps. BS: A backspace will be made on the printer. LF: Cursor is sent to the next line. FF: Page must be ejected from the printer. CR: The cursor is sent to the beginning of the line.

ASCII Code System (continued…) The control codes used to be used much more

in older systems, and nowadays they are usually recognized with a combination of “ctrl” + “the first uppercase alphabetical letter in the same row” instead of memorizing the related codes.

Overflow We shall show this concept through the following

example: As can be seen above, a negative result has

occurred from the addition of 2 positive numbers. This can not be an acceptable answer. The result could have been shown correctly in 9 bits, but our system has at most 8.

0 0 1 1 0 1 0 0

0 1 1 0 1 0 0 0

1 0 0 1 1 1 0 0

+

Overflow (continued…) Note: Overflowing can be caused by adding

large negative or positive numbers. It’s clear that adding a negative number and a positive one can not cause overflow.

Note: A way for pointing out an overflow occurrence is when the sign bit of the result differs from that of the operands (if the operand’s sign bits are the same).

Overflow (continued…) Diminishing overflows can be accomplished by

extending the space or numbers are stored in, for example to 16 bits. Using this method in the first case shown in the latter slides can be now seen as:

0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0

0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0+

0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0

Overflow (continued…) Extending the size of storage must be done

with consideration of the number’s sign. This is done by the use of the “Sign-Extension Process” where the 8 left most bits (16,32,… left most bits-dependent on the size of our actual number) of our new number are filled with the actual numbers’ sign bit.

Designing an Overflow Detector The circuit we are about to design will need

three inputs for it’s aim. The first and the second operands’ sign bit and also the sign bit of the sum.

A B

O V

A d d e r

va

bs

Designing an Overflow Detector (continued…) The problem, we face, can be solved with the

following insight to it. In words we have: “Overflow occurs when:

a=0 and b=0 and s=1 or a=1 and b=1 and s=0” Changing the sentence above and closing the

gap between the English statement and the math logic, we have:

sbasbav ....

Designing an Overflow Detector (continued…) If we state the equation using the following

symbols, we have:

abs

v

NOT ORAND

Structure of NMOS and PMOS Transistors The structure of a typical transistor is something

like this:

A transistor conducts when the channel between the source and drain is filled with carriers. In a NMOS transistor, the channeling is done by negative carriers (free electrons) and in PMOS transistors, it is done by positive carrier (holes electrons in the capacity band).

channel

DrainSourceGate SiO2

Body

Designing Logical Gates Using Transistors Now we will attempt to put together

combinations of these transistors to serve the needed purpose of the mentioned logical gates.

The gate “NOT” (inverter):

vdd

a w Symbola w

0

1 0

1

Designing Logical Gates Using Transistors (continued…) As it can be obviously seen in the previous

figure, a 0 input will make the PMOS transistor conduct and the NMOS one not conduct, resulting in a 1 output and a 1 input will have the output pulled down to 0 through the NMOS transistor.

Designing Logical Gates Using Transistors (continued…) The gate “NOR”:

If either of the 2 PMOS transistor doesn’t conduct, the supply will not reach the output whereas the output will be 0 if either of the NMOS transistors conducts. This structure of transistors serves the NOR function.

a

b

w

vdd

a b w

0

0

0

0

0

00

1

1 1

1

1Symbol

Designing Logical Gates Using Transistors (continued…) The gate “NAND”:

This structure can serve as NAND, the output being 0 only when the 2 inputs are 1 simultaneously.

aw

b

vdd

a b w

0

1

1

0

0

00

1

1 1

1

1Symbol

Designing Logical Gates Using Transistors (continued…) Note: Using three input in each of the serial or

parallel parts of these circuits will give the structure of a three input NAND/NOR notation.