DEPARTMENT OF EEE – EE6301 – DIGITAL LOGIC CIRCUITS

PSNA COLLEGE OF ENGINEERING & TECHNOLOGY

TUTORIAL – I

Unit I - Number System & Digital Logic Families

1. Convert the following binary numbers to decimal numbers

a) 1100111 b) 111010101 c) 101.1101

2. Convert the following binary numbers to octal and hexadecimal numbers.

a) 101111010111111 b) 110110110111 c) 1111100111110

3. Convert the following octal numbers to binary

a) 57.35 b) 2222 c) 50.25 d) 2765

4. Convert the following hexadecimal to binary numbers.

a) FFAF b) 9BCD6 c) 87D4

5. Convert the following decimal numbers to octal and hexadecimal numbers

a) 27777 b) 9898 c) 5235

6. Determine the 2’s Complement of the following numbers

a) 01101101 b) 11101111 c) 10000011

7. Convert the following decimal numbers into BCD

a) 298 b) 56 c) 99

8. What is the ASCII Code of message “MAY I HELP YOU”?

9. The ASCII Code message 100 0111 100 1111 100 0100 is stored in memory of a computer? What is the message?

10. Determine the XS3 equivalent of the following decimal numbers.

a) 345 b) 698

DEPARTMENT OF EEE – EE6301 – DIGITAL LOGIC CIRCUITS

PSNA COLLEGE OF ENGINEERING & TECHNOLOGY

TUTORIAL - II

UNIT – II – COMBINATIONAL CIRCUITS

1. Reduce the following function using K map:

f = ABC’ + A’B’C + ABC + ABC’ and realize using NAND gates only.

2. Reduce the following switching functions using Karnaugh map:

a. ∑m(0,1,2,6,7,9,12,28,29,31)

b. ∏ M(2,3,7,9,11,12)

3. Reduce the following switching function using Kmap Technique.

F (A, B, C, D) = ∑m (1, 3, 4, 7, 8, 10, 11, 13, 15)

4. Implement F(A,B,C,D) = Σm(0,1,2,3,4,7,9,10 by karnaugh map.

5. Simplify the function F(w,x,y,z) = Σ(2,3,12,13,14,15) using Kmap method.

Implement the simplified function using gates.

6. Find a minimal sum-of-products representation for

F (A,B,C,D,E) = ∑m(1,4,6,10,20,22,24,26) + d(0,11,16,27) using Karnaugh map

method. Draw the circuit of the minimal expression using only NAND gates. 7. Simplify the five variable switching function

f(EDCBA) = ∑m(3,5,6,8,9,12,13,14,19,22,24,25,30) 8. A system of logic is to be designed which has two outputs and three inputs. One

output will be TRUE if only one input alone is TRUE. The other output will be TRUE if only one input alone is TRUE. Draw the truth table and write the corresponding Boolean equations.

9. Implement the following function using suitable MUX F (w, x, y, z) = Σ (0, 2, 6, 7, 11, 13, 15)

10. Design and Implement half adder and full adder using suitable functions

11. Implement the full subtractor using 8: 1 MUX.

12. Design and implement a binary to Gray code converter.

13. Design a BCD to Gray code converter. Use don’t cares condition.

14. Realize F (w,x,y,z) = ∑ (1,4,6,7,8,9,10,11,15) using 4-to-1 MUX.

DEPARTMENT OF EEE – EE6301 – DIGITAL LOGIC CIRCUITS

PSNA COLLEGE OF ENGINEERING & TECHNOLOGY

TUTORIAL – III

UNIT III - SYNCHRONOUS SEQUENTIAL CIRCUITS

1. Convert a D flip-flop into a T flip-flop.

2. Derive T FF from JK FF.

3. Design a mod 6 counter using FFS. Draw the state transition diagram of the same.

4. Design a sequential circuit with 4 JK FF ABCD. The next states of B, C, D are equal to the present states of A, B, C respectively. The next state of A is equal to the EX-OR of the present states of C and D.

5. A sequential circuit with 2D FFs A and B and input X and output Y is specified by

the following next state and output equations. A (t+1) = AX + BX B (t+1) = A’X Y = (A+B) X’

i. Draw the logic diagram of the circuit ii. Derive the state stable

iii. Derive the state diagram.

6. Reduce the number of states in the following state table and tabulate the reduced state

table. Present State Next state Output

x = 0 x = 1 x = 0 x = 1

A f b 0 0

B d c 0 0

C f e 0 0

D g a 1 0

E d c 0 0

F f b 1 1

G g h 0 1

H g a 1 0

Starting from state a, and the input sequence 01110010011, determine the output

sequence for the given and reduced state table.

7. Design a synchronous decade counter using D flips flop.

8. Design and explain the working of a synchronous Mod 3& Mod 4 counter

9. Design a synchronous counter with states 0, 1, 2, 3, 0, 1…….using JK FFs.

DEPARTMENT OF EEE – EE6301 – DIGITAL LOGIC CIRCUITS

PSNA COLLEGE OF ENGINEERING & TECHNOLOGY

UNIT – IV ASYNCHRONOUS SEQUENTIAL CIRCUITS

TUTORIAL – IV- 1. Design an asynchronous sequential circuit with two inputs X and Y and with one

output Z. Whenever Y is 1, input X is transferred to Z. When Y is 0, the output does

not change for any change in X. Use SR latch for implementation of the circuit.

2. Obtain the primitive flow table for an asynchronous circuit that has two inputs x, y and output z. An output z = 1 is to occur only during the input state xy = 01 and then only if the input state xy = 01 is preceded by the input sequence xy = 01, 00, 10, 00, 10, 00.

3. Design a circuit with inputs A and B to give an output Z = 1 when AB = 11 but only

if A becomes 1 before B, by drawing total state diagram, primitive flow table and output map in which transient state is included.

4. Design a circuit with primary inputs A and B to give an output Z equal to 1 when A becomes 1 if B is already 1. Once Z = 1 it will remain so until A goes to 0. Draw waveform diagram, total state diagram, and primitive flow table for designing this circuit.

5. An Asynchronous sequential circuit has two internal states and one output. The

Excitation and output function describing the circuit are as follows.

𝑌1 = 𝑥1𝑥2 + 𝑥1𝑦2 + 𝑥2𝑦1 ; 𝑌2 = 𝑥2 + 𝑥1𝑦1𝑦2 + 𝑥1𝑦1 ; 𝑍 = 𝑥2 + 𝑦1

i) Draw the Logic diagram of the circuit.

ii) Derive the Transition table and output map iii) Derive the behavior of the circuit.

6. An Asynchronous sequential circuit has two internal states and one output. The

Excitation and output function describing the circuit are as follows. Y = X1X2 + (X1+X2) Y ; Z = Y

i) Draw the Logic diagram of the circuit. ii) Derive the Transition table and output map

iii) Derive the behavior of the circuit.

DEPARTMENT OF EEE – EE6301 – DIGITAL LOGIC CIRCUITS

PSNA COLLEGE OF ENGINEERING & TECHNOLOGY

7. An Asynchronous sequential circuit has two internal states and one output.

The Excitation and output function describing the circuit are as follows. 𝐵 = 𝐴1 + 𝐵2 𝐵 + 𝐴1 + 𝐵2 ; 𝐶 = 𝐵

i) Draw the Logic diagram of the circuit. ii) Derive the Transition table and output map iii) Derive the behavior of the circuit.

TUTORIAL – V

UNIT IV -

PROGRAMMABLE LOGIC DEVICES, MEMORY AND LOGIC FAMILIES

1. Show how a PAL is programmed for the following logic function.

X = AB’C + A’ B C’ + A’B’ + AC.

2. Implement the following Boolean function using

ROM.

F1 (A1,A0) = ∑m (1,2)

F2 (A1,A0) = ∑m (0,1,3) 3. Design a combinational using a ROM. The circuit accepts 3-bit binary no. and

generates its equivalent Excess-3 code.

4. Implement the function using PLA A (x,y,z) = ∑m (1,2,4,6) B (x,y,z) = ∑m (0,1,6,7) C (x,y,z) = ∑m (2,6)

5. Design a BCD to Excess-3 code converter and implement using PLA.

6. Implement the fn. Using PAL. A (x,y,z) = ∑m (1,2,4,6) B (x,y,z) = ∑m (0,1,6,7) C (x,y,z) = ∑m (2,6) D (x,y,z) = ∑m (1,2,3,5,7)

DEPARTMENT OF EEE – EE6301 – DIGITAL LOGIC CIRCUITS

PSNA COLLEGE OF ENGINEERING & TECHNOLOGY

7. Implement using PAL. W (A,B,C,D) = ∑m (1,2,5,7,8,10,12,13) X (A,B,C,D) = ∑m (0,2,6,8,9,14) Y (A,B,C,D) = ∑m (0,3,7,9,11,12,14) Z (A,B,C,D) = ∑m (1,2,4,5,9,10,14)

8. Implement using PLA. A (x,y,z) = ∑m (0,1,2,4,6) B (x,y,z) = ∑m (0,2,6,7) C (x,y,z) = ∑m (3,6) D (x,y,z) = ∑m (1,3,5,7)

DEPARTMENT OF EEE – EE6301 – DIGITAL LOGIC CIRCUITS

PSNA COLLEGE OF ENGINEERING & TECHNOLOGY

TUTORIAL – VI

UNIT V VHDL PROGRAMMING

1. Write a VHDL program module listing for a 16:1 Mux based on assign

statement. Use a 4 bit select word S3,S2,S1,S0 to map the selected inputs Pi = (i=0,1,2,….15) to the output.

2. Write the VHDL program to design the arithmetic logic operations using

case statement.

3. Write a VHDL program to design the grade system for the university examinations.

4. Write a VHDL coding for T- Flip-flop.

5. Write the VHDL coding for the following logic gates OR, NOT, NAND,

NOR, XOR, XNOR.

6. Write the VHDL coding to convert the binary number to an equivalent Gray code and vice versa.