Digital Logic: Boolean Algebra and Gates - Courses Textbook Chapter 3 CMPE12 – Summer 2008 Digital...

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Textbook Chapter 3

CMPE12 – Summer 2008

Digital Logic: Boolean Algebra and Gates

CMPE12 – Summer 2008 – Slides by ADB 2

Basic Logic Gates

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Truth TableThe most basic representation of a logic functionLists the output for all possible input combinationsHow many rows of the truth table needed? 2#inputs

X Y …A B …

OutputsInputs

X Y …A B …

OutputsInputs


Truth Table: InverterInverted signals are denoted with an overbarOr with a prime symbol

A’Y = A’A

OutputInput

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Truth Table: AND GateThe result of an AND operation is 1 if and only if all inputs are 1Depict AND by the multiplication symbol

A·BOr by lumping the signals together

ABWe don’t really build these gates…

Y = A · BA B

OutputInputs


Truth Table: OR GateThe result of an OR operation is 1 if and only if any inputs are 1Depict OR by the addition symbol

A+B

Y = A + BA B

OutputInputs

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About the Little Circle…The little circle is what inverts


Sum of ProductsHow do you get from a truth table to a logic expression?Sum of products is standard way of synthesizing simple circuitsProcedure:1. Find the rows with the ‘1’ output2. Write the product-form expression for the inputs

in that row (0=inverted, 1=normal)3. Combine the products in step 2 into a sum (OR

the results of step 2)

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Sum of Products1. Find the rows with the ‘1’

output2. Write the product-form

expression for the inputs in that row (0=inverted, 1=normal)

3. Combine the products in step 2 into a sum (OR the results of step 2)

101

110

000

011

YBA


De Morgan’s Laws“Break the line, change the sign”Two laws:

A’ + B’ = (AB)’A’ B’ = (A+B)’

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De Morgan’s Laws

(A + B)’ = A’B’ conversely (AB)’ = A’ + B’

“Break the line, change the sign”

1 0

A

1 1

0 1

0 0

A·BA BA+BA+B A B


De Morgan’s Laws

(A + B)’ = A’B’ conversely (AB)’ = A’ + B’

“Break the line, change the sign”

1 0

A

1 1

0 1

0 0

A+BA BABAB A B

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De Morgan’s LawsIn other words…Push the bubbles through!


De Morgan’s Laws and SOPGenerate equivalent circuits

NAND/NANDNOR/NOR

We prefer NAND/NAND circuitsSame transistor count as NORNANDs are faster

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MaskingWant to look only at certain bits of a binary wordUse a mask to remove the uninteresting bitsExample:


Axioms of Boolean Algebra0 · 0 = 1 + 1 = 1 · 1 = 0 + 0 =0 · 1 = 1 · 0 = 1 + 0 = 0 + 1 =1 + 0 = 0 + 1 = if x = 0 then x’ = if x = 1 then x’ =

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Single-Variable Theoremsx · 0 =x + 1 = x · 1 =x + 0 =x · x =x + x =x · x’ =x + x’ = (x’)’ =


Properties of Boolean AlgebraCommutative

x · y = x + y =

Associativex · (y · z) = x + (y + z) =

Distributivex · (y + z ) =x + y · z =

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Properties of Boolean AlgebraAbsorption

x + x · y =x · (x + y) =

Combiningx · y + x · y’ = (x + y) · (x + y’) =

De Morgan’s Laws(x · y)’ = (x + y)’ =

Otherx + x’·y =x · (x’ + y) =


Logic Minimization

0111

1011

0101

1001

1110

1010

0100

0000

YCBA Example

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Last time…


More Than Two Inputs?AND and OR gates can take any number of inputs

AND gives 1 if all inputs are 1OR gives 1 if any input is 1

NAND?? NOR??Not associative!

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Two-Way Multiplexer: Logic Symbol


Two-Way Multiplexer: Sum of Products2-way multiplexer: the output is equal to one of the two inputs, based on a selector

0011

1111

1101

0001

1110

1010

0100

0000

YBAS

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Uses of a MultiplexerSelect which input to useSelect which computed value to pass to the next stage of a computation (or to place on bus)

The main point:A multiplexer is a selector


Four-Way Multiplexern-bit selector and 2n inputs, one output

output equals one of the inputs, depending on selector

“Four-to-one mux”

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Two-to-Four Decodern inputs, 2n outputs

exactly one output is 1 for each possible input pattern

Generates a walking-ones pattern


Binary Addition and Half-Adder0 + 0 = 00 + 1 = 11 + 0 = 11 + 1 = ...Bigger addition example:

A half-adder is…

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One-Bit Full Adder

110

001

101

011

Cout

1

1

0

0

B

10

00

1

0

A

1

0

SCin


Four-Bit Full Adder

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Recommended exercises: combinational circuits

Ex 3.5, 3.6, 3.7, 3.8, 3.9Ex 3.11, 3.12, 3.18Ex 3.20, 3.22, 3.23, 3.24 with TA/TutEx 3.30, 3.31, 3.35Ex 3.44


Combinational vs. SequentialTwo types of “combination” locks

4 1 8 430

15

5

1020

25

CombinationalSuccess depends only onthe values, not the order in which they are set.

SequentialSuccess depends onthe sequence of values(e.g, R-13, L-22, R-3).

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Combinational vs. SequentialCombinational circuit

Always gives the same output for a given set of inputsExample: Adder always generates sum and carry, regardless of previous inputs

Sequential circuitRemembers previous inputOutput depends on state and input


Feedback and MemoryWhat if…

You connected an OR gate back to itself?You connected an AND gate back to itself?

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The Set Latch: Set Once


The Reset Latch: Reset Once

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Set-Reset (SR) LatchTwo inputs: Set and ResetStart with both inputs at 1 (memory)Set to 0 one of the two inputs at a time to store a valueThe transition 00 → 11 generates an undefined output


Set-Reset (SR) Latch

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D-LatchD-latch (D for data) is a gated RS latchUsed to store a single data bitTwo inputs: D (data) and WE (write enable)Q follows D when WE=1; when WE=0, Q is the latched value

D Q

E

D Q

WE

Ck

D Q

E

D Q

WE

Ck


D-Latch: Timing Diagram

0

1

timeCk

0

1

timeWE

0

1

timeD

0

1

timeQ

D Q

E

D Q

WE

Ck

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D-Flip-FlopTwo D-latches hooked togetherConnect one latch to the inverted clockD-flip-flop is edge-triggered (changes only on the edge of the clock)Also called “edge-triggered d-latch”

D Q

E

D Q

WE

Ck

D Q

E

D Q

E

D Q

WE

Ck


D-Flip Flop: Timing Diagram

0

1

timeCk

0

1

timeWE

0

1

timeD

0

1

timeQ

D Q

E

D Q

WE

Ck

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Flip-Flops in a Pipeline

D Q

E

D

WE

Ck

D Q

E

D Q

E

D Q

E

D

WE

Ck

D Q

E

D Q

E


D-Flip Flops in a Pipeline: Timing Diagram

0

1

timeCk

0

1

timeWE

0

1

timeD

0

1

timeQ1

Q

D Q

E

D

WE

Ck

D Q

E

0

1

time

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RegisterA register stores a multi-bit valueCommon WE which latches the n-bit value


MemoryNow that we know how to store bits,we can build a memory – a logical k × m array of stored bits.

•••

k = 2n

locations

m bits

Address Space:number of locations(usually a power of 2)

Addressability:number of bits per location(e.g., byte-addressable)

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22 x 3 Memory

addressdecoder

word select word WEaddress

writeenable

input bits

output bits


22 x 3 Memory

0

1

timeCk

0

1

timeWE

0

1

time

0

1

timeA[1:0] 01 0111 00

D[2:0]

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State MachineThe basic type of sequential circuit

Combines combinational logic with storage“Remembers” state, and changes output (and state) based on inputs and current state

State Machine

CombinationalLogic Circuit

StorageElements

Inputs Outputs


Representing Multi-bit ValuesBits are numbered from right (the 0th bit) to left (the n-1th bit)

Just a conventionRange is denoted with brackets

D[a:b] denotes bit a to bit b, inclusive, from left to rightYou may also see A<14:9>, especially in hardware block diagrams

Example:D = 0101001101010101

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Representing Multi-bit ValuesExample:

D = 0101001101010101

D =

bit

0101110101101000

D[3:0]D[14:10]

041015


LC-3 Architecture Sneak Preview

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LC-3 Data Path

CombinationalLogic

State Machine

Storage


Recommended exercises on Sequential Circuits

Ex 3.19Ex 3.21, 3.34, 3.35Ex 3.40, 3.41, 3.43

Digital Logic: Boolean Algebra and Gates - Courses Textbook Chapter 3 CMPE12 – Summer 2008 Digital...

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