Digital Logic: Boolean Algebra and Gates - Course Web · PDF file1 Textbook Chapter 3 Digital...

1

Textbook Chapter 3

Digital Logic: Boolean Algebra and Gates

CMPE12 – Summer 2010 02-2

Basic logic gates

XOR

2


Truth table

The most basic representation of a logic function

Lists the output for all possible input combinations

How many rows of the truth table needed? 2#inputs

X Y …A B …

OutputsInputs

X Y …A B …

OutputsInputs


Truth table: Inverter

Inverted signals are denoted with an overbar

Or with a prime symbol

A‟

Input Output

A Y = A‟

3


Truth table: AND gate

The result of an AND operation is 1 if and only if all inputs are 1

Depict AND by the multiplication symbol

A·B

Or by lumping the signals together

AB

We don‟t really build these gates…

Inputs Output

A B Y = A · B


Truth Table: OR Gate

The result of an OR operation is 1 if and only if any inputs are 1

Depict OR by the addition symbol

A+B

Inputs Output

A B Y = A + B

4


About the little circle…

The little circle is what inverts


5

CMPE12 – Summer 2010 02-10

Sum of products

How do you get from a truth table to a logic expression?

Sum of products is standard way of synthesizing simple circuits

Procedure:1. Find the rows with the „1‟ output2. Write the product-form expression for the

inputs in that row (0=inverted, 1=normal)3. Combine the products in step 2 into a sum (OR

the results of step 2)

CMPE12 – Summer 2010 02-11

Sum of products

1. Find the rows with the „1‟ output

2. Write the product-form expression for the inputs in that row (0=inverted, 1=normal)

3. Combine the products in step 2 into a sum (OR the results of step 2)

A B Y

0 0 0

0 1 1

1 0 1

1 1 0

6

CMPE12 – Summer 2010 02-12

De Morgan’s Laws

“Break the line, change the sign”

Two laws:

A‟ + B‟ = (AB)‟

A‟ B‟ = (A+B)‟

CMPE12 – Summer 2010 02-13

De Morgan’s Laws

(1) A’ + B’ = (AB)’


A B A+B (A+B)’ A·B (A·B)’

0 0

0 1

1 0

1 1

7

CMPE12 – Summer 2010 02-14

De Morgan’s Laws

(2) A’B’ = (A + B)’


A B A’ B’ A’·B’ A+B (A+B)’

0 0

0 1

1 0

1 1

CMPE12 – Summer 2010 02-15

De Morgan’s Laws

In other words…

Push the bubbles through!

8

CMPE12 – Summer 2010 02-16

CMPE12 – Summer 2010 02-17

De Morgan’s Laws and SOP

Generate equivalent circuits

NAND/NAND

NOR/NOR

We prefer NAND/NAND circuits

Same transistor count as NOR

NANDs are faster

9

CMPE12 – Summer 2010 02-19

More Than Two Inputs?

AND and OR gates can take any number of inputs

AND gives 1 if all inputs are 1

OR gives 1 if any input is 1

NAND?? NOR??

Not associative!

CMPE12 – Summer 2010 02-20

NAND is not associative

10

CMPE12 – Summer 2010 02-21

Two-Way multiplexer

2-way multiplexer: the output is equal to one of the two inputs, based on a selector

S A B Y

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

CMPE12 – Summer 2010 02-22

Two-Way multiplexer

11

CMPE12 – Summer 2010 02-23

Four-Way multiplexer

n-bit selector and 2n inputs, one output

output equals one of the inputs, depending on selector

“Four-to-one mux”

CMPE12 – Summer 2010 02-24

Two-to-Four decoder

n inputs, 2n outputs

exactly one output is 1 for each possible input pattern

Generates a walking-ones pattern

12

CMPE12 – Summer 2010 02-25

Masking

Want to look only at certain bits of a binary word

Use a mask to remove the uninteresting bits

Example:

CMPE12 – Summer 2010 02-26

Axioms of Boolean Algebra

0 · 0 =

1 + 1 =

1 · 1 =

0 + 0 =

0 · 1 = 1 · 0 =

1 + 0 = 0 + 1 =

if x = 0 then x‟ =

if x = 1 then x‟ =

13

CMPE12 – Summer 2010 02-27

Single-Variable Theorems

x · 0 =

x + 1 =

x · 1 =

x + 0 =

x · x =

x + x =

x · x‟ =

x + x‟ =

(x‟)‟ =

CMPE12 – Summer 2010 02-28

Properties of Boolean Algebra

Commutative

x · y =

x + y =

Associative

x · (y · z) =

x + (y + z) =

Distributive

x · (y + z ) =

x + y · z =

14

CMPE12 – Summer 2010 02-29


Absorption

x + x · y =

x · (x + y) =

Combining

x · y + x · y‟ =

(x + y) · (x + y‟) =

CMPE12 – Summer 2010 02-30


De Morgan‟s Laws

(x · y)‟ =

(x + y)‟ =

Other

x + x‟·y =

x · (x‟ + y) =

15

CMPE12 – Summer 2010 02-31

Binary addition and half-adder

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = ...

Bigger addition example:

A half-adder is…

CMPE12 – Summer 2010 02-32

One-Bit Full Adder

A B Cin Cout S

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

16

CMPE12 – Summer 2010 02-33

Four-Bit Full Adder

CMPE12 – Summer 2010 02-34

Logic MinimizationA B C Y

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

Example

17

CMPE12 – Summer 2010 02-35

Recommended exercises

Combinational circuits

Ex 3.5, 3.6, 3.7, 3.8, 3.9

Ex 3.11, 3.12, 3.18

Ex 3.20, 3.22, 3.23, 3.24 with TA/Tut

Ex 3.30, 3.31, 3.35

Ex 3.44

CMPE12 – Summer 2010 02-37

Combinational vs. Sequential

Two types of “combination” locks

4 1 8 4

30

15

5

1020

25

Combinational

Success depends only on

the values, not the order in

which they are set.

Sequential

Success depends on

the sequence of values

(e.g, R-13, L-22, R-3).

18

CMPE12 – Summer 2010 02-38

Combinational vs. Sequential

Combinational circuit

Always gives the same output for a given set of inputs

Example: Adder always generates sum and carry, regardless of previous inputs

Sequential circuit

Remembers previous input

Output depends on state and input

CMPE12 – Summer 2010 02-40

Feedback and Memory

What if…

You connected an OR gate back to itself?

You connected an AND gate back to itself?

19

CMPE12 – Summer 2010 02-41

The Set Latch: Set Once

CMPE12 – Summer 2010 02-42

The Reset Latch: Reset Once

20

CMPE12 – Summer 2010 02-43

Set-Reset (SR) Latch

Two inputs: Set and Reset

Start with both inputs at 1 (memory)

Set to 0 one of the two inputs at a time to store a value

The transition 00 → 11 generates an undefined output

CMPE12 – Summer 2010 02-44

Set-Reset (SR) Latch

21

CMPE12 – Summer 2010 02-45

D-Latch

D-latch (D for data) is a gated RS latch

Two inputs: D (data) and WE (write enable)

D Q

E

D Q

WE

Ck

D Q

E

D Q

WE

Ck

CMPE12 – Summer 2010 02-46

D-Latch: Timing Diagram

0

1

time

Ck

0

1

time

WE

0

1

time

D

0

1

time

Q

D Q

E

D Q

WE

Ck

22

CMPE12 – Summer 2010 02-47

D-Flip-Flop

Two D-latches hooked together

Connect one latch to the inverted clock

D-flip-flop is edge-triggered (changes only on the edge of the clock)

Also called “edge-triggered d-latch”

D Q

E

D Q

WE

Ck

D Q

E

D Q

E

D Q

WE

Ck

CMPE12 – Summer 2010 02-48

D-Flip Flop: Timing Diagram

0

1

time

Ck

0

1

time

WE

0

1

time

D

0

1

time

Q

D Q

E

D Q

WE

Ck

23

CMPE12 – Summer 2010 02-49

D-Flip Flops in a Pipeline

0

1

time

Ck

0

1

time

WE

0

1

time

D

0

1

time

Q1

Q

D Q

E

D

WE

Ck

D Q

E

0

1

time

Q2

CMPE12 – Summer 2010 02-50

D-Flip Flops in a Pipeline

0

1

time

Ck

0

1

time

WE

0

1

time

D

0

1

time

Q1

Q

D Q

E

D

WE

Ck

D Q

E

0

1

time

Q2

24

CMPE12 – Summer 2010 02-51

Register

A register stores a multi-bit value

Common WE which latches the n-bit value

CMPE12 – Summer 2010 02-52

Memory

Now that we know how to store bits,we can build a memory – a logical k × m array of stored bits.

•••

k = 2n

locations

m bits

Address Space:

number of locations(usually a power of 2)

Addressability:

number of bits per location(e.g., byte-addressable)

25

CMPE12 – Summer 2010 02-53

22 x 3 Memory

address

decoder

word select word WEaddress

write

enable

input

bits

output bits

CMPE12 – Summer 2010 02-54

State Machine

The basic type of sequential circuit

Combines combinational logic with storage

“Remembers” state, and changes output (and state) based on inputs and current state

State Machine

Combinational

Logic Circuit

Storage

Elements

Inputs Outputs

26

CMPE12 – Summer 2010 02-55

Example of sequential machine

A 2-bit counter:

CMPE12 – Summer 2010 02-56

Representing Multi-bit ValuesNumber bits from right (0) to left (n-1)

just a convention -- could be left to right, but must be consistent

Use brackets to denote range:D[l:r] denotes bit l to bit r, from left to right

A = 0101001101010101

A[2:0] = 101A[14:9] = 101001

015

May also see A<14:9>, especially in hardware block

diagrams.

27

An LC-3 architecture’s sneak preview

CMPE12 – Summer 2010 02-58

LC-3 Data Path

Combinational

Logic

State Machine

Storage

28

CMPE12 – Summer 2010 02-59

Recommended exercises

Sequential circuits

Ex 3.19

Ex 3.21, 3.34, 3.35

Ex 3.40, 3.41, 3.43

Digital Logic: Boolean Algebra and Gates - Course Web · PDF file1 Textbook Chapter 3 Digital...

Documents

Transcript of Digital Logic: Boolean Algebra and Gates - Course Web · PDF file1 Textbook Chapter 3 Digital...