Digital Integrated Circuitshtang/ece4311_doc_F11/... · © Digital Integrated Circuits2nd Inverter...
Transcript of Digital Integrated Circuitshtang/ece4311_doc_F11/... · © Digital Integrated Circuits2nd Inverter...
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© Digital Integrated Circuits2nd Inverter
Digital Integrated
CircuitsA Design Perspective
The Inverter
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Revised from Digital Integrated Circuits, © Jan M. Rabaey el, 2003
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© Digital Integrated Circuits2nd Inverter
Propagation Delay
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© Digital Integrated Circuits2nd Inverter
CMOS Inverter Propagation Delay
VDD
Vout
Vin = VDD
Ron
CL
tpHL = f(Ron.CL)
= 0.69 RonCL
t
Vout
VDD
RonCL
1
0.5
ln(0.5)
0.36
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© Digital Integrated Circuits2nd Inverter
MOS transistor model for simulation
DS
G
B
CGDCGS
CSB CDBCGB
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© Digital Integrated Circuits2nd Inverter
Computing the Capacitances
VDD VDD
VinVout
M1
M2
M3
M4Cdb2
Cdb1
Cgd12
Cw
Cg4
Cg3
Vout2
Fanout
Interconnect
VoutVin
CL
SimplifiedModel
Consider each capacitor individually is almost impossible for
manual analysis. What capacitors count in CL?
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Computing the Capacitances NMOS and PMOS transistor are either in cutoff or
saturation mode during at least the first half (50%) of the
output transient.
So, the only contributions to Cgd are the overlap
capacitance, since channel capacitance occurs between
either Gate-Body for transistors in cutoff region or Gate-
Source for transistors in saturation region.
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© Digital Integrated Circuits2nd Inverter
The Miller Effect
Vin
M1
Cgd1
Vout
V
V
Vin
M1
Vout V
V
2Cgd1
“A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value.”
The lumped capacitor model requires the floating Cgd1
capacitor be replaced by a capacitor to GND using Miller
effect.
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© Digital Integrated Circuits2nd Inverter
The Miller Effect Consider the situation that an impedance is connected
between input and output of an amplifier
The same current flows from (out) the top input terminal if animpedance is connected across the input terminals
The same current flows to (in) the top output terminal if animpedance is connected across the output terminal
This is know as Miller Effect
Two important notes to apply Miller Effect: There should be a common terminal for input and output
The gain in the Miller Effect is the gain after connecting feedbackimpedance
MillerinZ ,
MilleroutZ ,
fZ
Graphs from Prentice Hall
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© Digital Integrated Circuits2nd Inverter
Computing the Capacitances
The capacitance between drain and bulk, Cdb1 and Cdb2, are due to the reverse-biased pn-
junction.
Such a capacitor is, unfortunately, quite nonlinear and depends heavily on the applied voltage.
In Chapter 3 we replaced the nonlinear capacitor by a linear one with the same change in
charge for the voltage range of interest. A multiplication factor, Keq, is introduced to relate the
linearized capacitor to the value of the junction capacitance under zero-bias conditions
(usually in the range of 0.6 to 0.9).
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© Digital Integrated Circuits2nd Inverter
Junction Capacitance
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© Digital Integrated Circuits2nd Inverter
Linearizing the Junction Capacitance
Replace non-linear capacitance bylarge-signal equivalent linear capacitance
which displaces equal charge over voltage swing of interest
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© Digital Integrated Circuits2nd Inverter
Polysilicon
InOut
Metal1
VDD
GND
PMOS
NMOS
9λ/2λ
3λ/2λ
ADp=45 λ2
PDp=19 λ
ADn=19 λ2
PDn=15 λ
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© Digital Integrated Circuits2nd Inverter
Junction Capacitance Ls (from Ch. 3)
Bottom
Side wall
Side wall
Channel
SourceND
Channel-stop implantN A
Substrate NA
W
xj
LS
Junction capacitance per unit area
No channel side
Junction capacitance
per unit length
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© Digital Integrated Circuits2nd Inverter
Computation of all capacitors
Cdb will be slightly different
in L-to-H and H-to-L, why?
(the pn junction reverse bias
voltage range)
Intrinsic
extrinsic
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© Digital Integrated Circuits2nd Inverter
0 0.5 1 1.5 2 2.5
x 10-10
-0.5
0
0.5
1
1.5
2
2.5
3
t (sec)
Vout(V
)
Transient Response
tp = 0.69 CL (Reqn+Reqp)/2
?
tpHLtpLH
Cgd directly couples the steep input change before the circuit can even start
to react to the changes at input (potential forward bias the pn junction)
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© Digital Integrated Circuits2nd Inverter
Low-to-High and High-to-Low delay
It is desired to have identical propagation
delays for both rising and falling inputs.
Equal delay requires equal equivalent on-
resistance, thus equal current IDAST
(neglecting the channel length modulation)
This demands almost the same
requirements for a Vm at VDD/2. Why?
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© Digital Integrated Circuits2nd Inverter
2)()(
2)()(
2)(
'
'
2
'
DSATp
TpDDDSATpppDp
DSATnTnDDDSATnnnDn
DSATDSATTDDDSAT
VVVV
L
WkI
VVVV
L
WkI
VVVV
L
WkI
1)/(
)/(then
2/ Assume
'
'
DSATnn
DSATpp
nDSATnn
pDSATpp
DSATpTpDD
Vk
Vk
LWVk
LWVk
VVV
This is exactly the formerly defined parameter r (last lecture)
Requirements for equal delay
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© Digital Integrated Circuits2nd Inverter
Design for delay performance
Keep capacitances small
• careful layout, e.g. to keep drain
diffusion as small as possible
Increase transistor sizes
• watch out for self-loading! When
intrinsic capacitance starts to
dominate the extrinsic ones
Increase VDD (????)
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© Digital Integrated Circuits2nd Inverter
Delay as a function of VDD
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VDD
(V)
t p(n
orm
aliz
ed)
Recall a range
of low voltage
is able to give
even better
voltage transfer
characteristic
For fixed (W/L)
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© Digital Integrated Circuits2nd Inverter
2 4 6 8 10 12 142
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8x 10
-11
S
t p(s
ec)
Device Sizing
(for fixed load and VDD)
Self-loading effect:Intrinsic capacitancesdominate
W/L
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© Digital Integrated Circuits2nd Inverter
1 1.5 2 2.5 3 3.5 4 4.5 53
3.5
4
4.5
5x 10
-11
b
t p(s
ec)
NMOS/PMOS ratio
tpLH tpHL
tp b= Wp/Wn
Widening PMOS improves the L-H delay by increasing the charge current,
but it also degrades the H-L by giving a larger parasitic capacitance.
Considering average is more meaningful!!
(Average)
Lp=Ln
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© Digital Integrated Circuits2nd Inverter
Delay Definitions
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© Digital Integrated Circuits2nd Inverter
Impact of Rise Time on Delay
t pH
L(n
sec)
0.35
0.3
0.25
0.2
0.15
trise (nsec)
10.80.60.40.20
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© Digital Integrated Circuits2nd Inverter
Custom design
process:
An inverter design
example
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© Digital Integrated Circuits2nd Inverter
1. Schematic design
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© Digital Integrated Circuits2nd Inverter
2. Layout design
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Step 1: define Nwell (for PMOS)
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© Digital Integrated Circuits2nd Inverter
Step 2: define pselect (for PMOS location)
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© Digital Integrated Circuits2nd Inverter
Step 3: define active region (for PMOS)
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Step 4: define poly (gate for PMOS)
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Step 5: define contacts (for PMOS)
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© Digital Integrated Circuits2nd Inverter
Step 6: define Vdd and connect source (of PMOS) to it
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Step 7: make at least one Nwell contact
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© Digital Integrated Circuits2nd Inverter
Step 8: create NMOS (repeat similar steps before
except you do not need make Nwell)
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step9: make input and output connections
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© Digital Integrated Circuits2nd Inverter
2. DRC (Design Rule Check)
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© Digital Integrated Circuits2nd Inverter
Correct error if there is any
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© Digital Integrated Circuits2nd Inverter
After correction
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3. LVS (Layout versus Schematic)
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4. Extract Layout parasitics and post-layout simulation
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© Digital Integrated Circuits2nd Inverter
CMOS Inverter
Polysilicon
In Out
VDD
GND
PMOS2l
Metal 1
NMOS
OutIn
VDD
PMOS
NMOS
Contacts
N Well
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Two Inverters
Connect in Metal
Layout preference:
Share power and ground
Abut cells
VDD
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© Digital Integrated Circuits2nd Inverter
Impact of Process Variations (DFM)
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin
(V)
Vo
ut(V
)
Good PMOSBad NMOS
Good NMOSBad PMOS
Nominal
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Inverter Sizing
for delay
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Inverter with Load
Load
Delay
Cint CL
Delay = kRW(Cint + CL) = kRWCint + kRWCL
= Delay (Internal) + Delay (Load)
= kRW Cint(1+ CL /Cint)
3W
W
W means the size is increased by a factor of W with
respect to the minimum size
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Delay as function of size
• Intrinsic delay is fixed and independent of sizeW
• Making W large yields better performance gain, eliminating the
impact of external load and reducing the delay to intrinsic only. But
smaller gain at penalty of silicon area if W is too large!
))/(1(0 unitLpp WCCtt
RW = Runit / W ; Cint = W Cunit
tp0 = 0.69RunitCunit
Delay = kRW Cint(1+ CL /Cint)
= Delay (Internal) + Delay (Load)
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© Digital Integrated Circuits2nd Inverter
Delay Formula
/1/1
~
0int ftCCCkRt
CCRDelay
pintLWp
LintW
Cint = Cgin with 1 for modern technology(see page199 in book or Slid 14 for an example)
Cgin : input gate capacitance
CL = f Cgin - effective fanout
This formula maps the intrinsic capacitor and load
capacitor as functions of a common capacitor,
which is the gate capacitance of the minimum-size
inverter
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Single inverter versus inverter chain
Gate sizing for an isolated gate is
not really meaningful. Realistic chips
always have a long chain of gates.
So, a more relevant and realistic
problem is to determine the optimal
sizing for a chain of gates.
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Inverter Chain
CL
If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
In Out
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Apply to Inverter Chain (fixed N stages)
CL
In Out
1 2 N
tp = tp1 + tp2 + …+ tpN
jgin
jgin
unitunitpjC
CCRt
,
1,
1~
LNgin
N
i jgin
jgin
p
N
j
jpp CCC
Cttt
1,
1 ,
1,
0
1
, ,
1
Unit size (minimum size) inverter
Size ? Size ?
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Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N
Minimize the delay, find N - 1 partial derivatives equated to 0
Result: Cgin,j+1/Cgin,j = Cgin,j /Cgin,j-1
Size of each stage is the geometric mean of two neighbors
- each stage has the same effective fanout
- each stage has the same delay
1,1,, jginjginjgin CCC
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Optimum Delay for fixed N stages
1,/ ginL
N CCFf
When each stage is sized by f and has same effective
fanout f:
N Ff
Minimum path delay
Effective fanout of each stage:
) / 1(
1 0
1 ,
1,
0
1
,
Np
N
i jgin
jgin
p
N
j
jpp FNtC
Cttt
effective fanout
of the overall
circuit
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Example
CL= 8 C1
In Out
C11 f f2
283 f
CL/C1 has to be evenly distributed across N = 3 stages:
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Optimum Number of Stages
For a given load CL and given input capacitance Cin
Find optimal sizing f
ff
fFtFNtt
pN
pplnln
ln1/
0/1
0
0ln
1lnln2
0
f
ffFt
f
t pp
For = 0, f = e, N = lnF
f
FNCfCFC in
N
inLln
ln with
ff 1exp
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Optimum Effective Fanout fOptimum f for given process defined by
ff 1exp fopt = 3.6 for =1
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Impact of introducing buffers
/10N
pp FNtt fopt = 4
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Buffer Design
1
1
1
1
8
64
64
64
64
4
2.8 8
16
22.6
N f tp
1 64 65
2 8 18
3 4 15
4 2.8 15.3
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© Digital Integrated Circuits2nd Inverter58
Intel Itanium Microprocessor
9-1
Mu
x9
-1 M
ux
5-1
Mu
x2
-1 M
ux
ck1
CARRYGEN
SUMGEN
+ LU
1000um
b
s0
s1
g64
sum sumb
LU : Logical
Unit
SU
MS
EL
a
to Cache
node1
RE
GItanium has 6 integer execution units like this