Digital Integrated Circuits { EECS 312ziyang.eecs.umich.edu/~dickrp//eecs312/lectures/dic-l8.pdf ·...

Digital Integrated Circuits – EECS 312

http://robertdick.org/eecs312/

Teacher: Robert DickOffice: 2417-E EECSEmail: [email protected]: 734–763–3329Cellphone: 847–530–1824

GSI: Shengshou LuOffice: 2725 BBBEmail: [email protected]

HW engineers SW engineers

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30 beats per sample

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Radio Receive for

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Low Power Sleep0.030 - 0.050 mA

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http://robertdick.org/eecs312/

Inverter noise marginsInverter dynamic behavior

Midterm reviewHomework

Review I

2 Robert Dick Digital Integrated Circuits



Review II

How can the transfer curve for an inverter be derived from theI–V curves of the MOSFETs comprising it?

What useful property relevant to the inverter load curve diagramholds in steady state but not when transients are considered?

Is the inverter load curve diagram useful for analyzing dynamicsystems?




Midterm exam

May cover anything up to and including 3 October.

Make sure you did the assigned reading.

Look though all the on-line slides for anything surprising.

Review lab and homework assignments.

If you want to study with other students, please use mailing listto find partners.

Posted old exams to website.

No class on Tuesday.




Lecture plan

1. Inverter noise margins

2. Inverter dynamic behavior

3. Midterm review

4. Homework




VIH and VIL

VIH − VIL = −VOH − VOL

g=

−VDDg

(1)

VIH = VM −VMg

(2)

VIL = VM +VDD − VM

g(3)

NMH = VDD − VIH (4)NML = VIL (5)




Inverter gain

Can find gain by takingσVout/σVin at VM .

g = − 1ID(VM)

knVDSATn + kpVDSATpλn − λp

(1)

g ≈ 1 + r(VM − VTn − VDSATn2

)(λn − λp)

(2)




Change in transfer curve (and gain) with VDD




Subthreshold operation

Higher gain.

Lower current.

Increased sensitivity to intrinsic noise.

Increased sensitivity to fixed external noise.xkTq




Impact of process variation on inverter transfer function




Inverter performance

Recall inverter propagation delay expression: tp = 0.69RC .

Either decrease R or decrease C .

Effective R depends on VDD .




Dependence of inverter delay on VDD I

tpHL = 0.693

4

CLVDDIDSATn

tpHL = 0.52LnWn

CLVDDk ′nVDSATn(VDD − VTn − VDSATn/2)

If VDD � VTn + VDSATn/2

tpHL ≈ 0.52LnWn

CLk ′nVDSATn

.

Why?

Req =1

VDD/2

∫ VDDVDD/2

V

IDSAT (1 + λV )dV ≈ 3

4

VDDIDSAT

(1 − 7

9λVDD

)




Dependence of inverter delay on VDD II

where

IDSAT = k′W

L

((VDD − VT )VDSAT −

VDSAT2

2

).

Ignore channel length modulation factor λ.




Review

Define noise margin and explain why it is a useful concept.

What is VM?

What influence does an asymmetric change in inverter MOSFETresistance have on the Vout–Vin curve?

What is inverter gain and how does it depend on VDD?

What happens to inverter delay with decreasing VDD?




Lecture plan



3. Midterm review

4. Homework




Dependence of delay on width (R)

Fix RLCL and vary W .

Eventually, self-loading dominates.




Impact of Wp/Wn ratio

Warning: Broken concept, especially for short-chain analysis.

β = Wp/Wn.

tp =tpLH+tpHL

2 .




Impact of rise time on delay




Modeling rise time effects in inverter chains

t ip = tistep + ηt

i−1step

t istep: Delay of gate i in response to step input function.

η: Technology-dependent constant, generally near 0.25.




Lecture plan



3. Midterm review

4. Homework




Midterm exam I

1 Uses of digital systems.

2 History of digital computing devices. Impact of technologyimprovements on performance, power consumption, size, andreliability. Bipolar to CMOS move.

3 Power consumption equation and components of total powerconsumption. Check Slide 19 in lecture notes packet 2.

4 Requirements for devices to permit use in digital system.Regeneration/restoration.

5 MOSFET structure and layout.

6 Schematic capture, e.g., using Cadence software.

7 Resistance basics, and their application to MOSFET channelsand metal wires.




Midterm exam II

8 Basic logic gate and transmission gate structures.

9 NMOS, PMOS, and CMOS inverters.

10 Diode structure and operation. Drift and diffusion. Differencebetween charge carriers and stationary ions. Doping.

11 MOSFET operation. Change in conditions (especially ID) withchanging VGS , VDS , and VSB . MOSFET models. Cutoff,pinch-off, and velocity saturation.

12 Subthreshold leakage and subthreshold operation.

13 Process variation definition and influence on circuit behavior.

14 High-level understanding of FinFET structure and reason forimproved k .

15 Steps in fabrication process. Dual damascene process.

16 Understanding what design rules are.




Midterm exam III

17 Packaging, MCMs, and board-level design. Implications ofpackaging and interconnect for performance.

18 Gate leakage. High-κ dielectric. See assigned article.

19 Transient diode and MOSFET behavior. Computing capacitancesbased on MOSFET structure and operating region.

20 Derivation from inverter transfer curve from MOSFET I–Vcurves. Impact of inverter asymmetry on VM .

21 Noise margin definitions and purpose. Gain definition.




Upcoming topics

Inverter chains for driving large loads.

Complex behavior in logic gate.




Lecture plan



3. Midterm review

4. Homework




Homework assignment

3 October: Read sections 5.3, 5.4.1, and 5.4.2 in J. Rabaey,

A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: ADesign Perspective.Prentice-Hall, second edition, 2003.

3 October: Lab 2.

10 October: Homework 2 (which will help in your preparation forthe midterm exam).

10 October: Read sections 5.4, 5.5, 5.6, and 3.5 in J. Rabaey,

A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: ADesign Perspective.Prentice-Hall, second edition, 2003.


Inverter noise marginsInverter dynamic behaviorMidterm reviewHomework

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