Digital Graphic Equalizer Implemented Using an FPGA · 2017-07-25 · G raph ic Equ l ze Nine LED...

Anthony Giardina | 1

Digital Graphic Equalizer Implemented Using an FPGA

by

Anthony Giardina

Senior Project

ELECTRICAL ENGINEERING DEPARTMENT

California Polytechnic State University

San Luis Obispo

2012


Table of Contents List of Figures, Tables, and Equations.................................................................................................................. 4

Abstract: ............................................................................................................................................................ 6

Chapter 1: introduction ...................................................................................................................................... 6

Chapter 2: Requirements and Specifications ....................................................................................................... 7

Chapter 3: Functional Decomposition & Description ........................................................................................... 8

Theory of Operation: ...................................................................................................................................... 8

Top Level Block Diagram: ................................................................................................................................ 8

System Level Block Diagram:........................................................................................................................... 9

Component Identification: ............................................................................................................................ 10

Chapter 4: Hardware Design ............................................................................................................................. 13

Interface Cable ............................................................................................................................................. 13

Peripheral Board........................................................................................................................................... 15

Description ............................................................................................................................................... 15

Schematic ................................................................................................................................................. 15

Layout ...................................................................................................................................................... 15

Components ............................................................................................................................................. 25

Implementation, Testing, and Rework....................................................................................................... 28

Atlys FPGA Development Board .................................................................................................................... 32

Specification ............................................................................................................................................. 32

Implementation Issues .............................................................................................................................. 32

Power Estimation ......................................................................................................................................... 35

Chapter 5: Firmware Design ............................................................................................................................. 36

Firmware Development Toolchain ................................................................................................................ 36

Top level Firmware Overview ....................................................................................................................... 37

Top Level Firmware Block Diagram ........................................................................................................... 37

Top level timing diagram........................................................................................................................... 39

System Level Clock Distribution ................................................................................................................ 39

Firmware Modules ....................................................................................................................................... 40

audioProcessor ......................................................................................................................................... 40

ledDriver................................................................................................................................................... 40

adcDriver .................................................................................................................................................. 41

clockDivider .............................................................................................................................................. 42

interfaceDriver2........................................................................................................................................ 42

cmdBank................................................................................................................................................... 43


frameBuilder............................................................................................................................................. 43

codecDriver .............................................................................................................................................. 43

summer9x2ch ........................................................................................................................................... 45

gainAtten .................................................................................................................................................. 46

lut ............................................................................................................................................................. 47

ledLut ....................................................................................................................................................... 48

multiplier .................................................................................................................................................. 48

clockManager ........................................................................................................................................... 49

f1_48K through f9_48K ............................................................................................................................. 50

Appendix A: VHDL Source Code ........................................................................................................................ 53

Appendix B: Matlab Source Code .................................................................................................................... 100

Appendix C: FIR Filter Coefficients .................................................................................................................. 104

Appendix D: Cost and Scheduling.................................................................................................................... 120

Appendix E: References .................................................................................................................................. 121


List of Figures, Tables, and Equations Figure 1: Top Level Block Diagram ...................................................................................................................... 8

Figure 2: System Level Block Diagram ................................................................................................................. 9

Figure 3: Assembled view of graphic equalizer for component identification .................................................... 10

Figure 4: Disassembled view of graphic equalizer for component identification ................................................ 10

Figure 5: AC-DC Power Supply .......................................................................................................................... 11

Figure 6: Bottom View of assembled graphic equalizer for component identification ....................................... 11

Figure 7: Interface connector, with pin numbers shown ................................................................................... 13

Figure 8: Peripheral Interface Schematic, page 1: Pin header, driver, and linear regulator ................................ 16

Figure 9: Peripheral Interface Schematic, page 2: slide potentiometers, ADC, and analog references ............... 17

Figure 10: Peripheral Interface Schematic, page 3: LED drivers ......................................................................... 18



Figure 13: Peripheral Interface Board Artwork, top layer copper and silkscreen ................................................ 21

Figure 14: Peripheral Interface Board Artwork, bottom layer copper and silkscreen ......................................... 22

Figure 15: Peripheral Interface Board Artwork, top layer solder mask ............................................................... 23

Figure 16: Peripheral Interface Board Artwork, bottom layer solder mask ........................................................ 24

Figure 17: TLC59281 LED Driver serial bus voltage levels................................................................................... 25

Figure 18: TLC541L ADC serial bus voltage levels .............................................................................................. 27

Figure 19: Rework #1: +5V_REG and +5V nets connected with wire .................................................................. 29

Figure 20: Rework #2: Jumper soldered onto slide potentiometers to connect wiper to ADC input ................... 29

Figure 21: Peripheral board, fully populated, top view ...................................................................................... 30

Figure 22: Peripheral board, fully populated, bottom view ............................................................................... 31

Figure 23: Supply noise on LM4550, pin 9, VDD2. CH1 connected to pin 9 of LM4550. ...................................... 33

Figure 24: Rework #3: L1 replaced by solder bridge, and additional capacitor added in parallel to C27 ............. 34

Figure 25: Output of Atlys test program, showing 300kHz noise on LM4550 line-out port. CH1: irrelevant, CH2:

LM4550 line-out, M: FFT of CH2 ....................................................................................................................... 34

Figure 26: Loopback test of LM4550, showing 340kHz noise on line-out port. CH1: Line-in. CH2: line-out. M: FFT

of CH2 .............................................................................................................................................................. 35

Figure 27: Firmware development design flow ................................................................................................. 36

Figure 28: Top level block diagram of firmware ................................................................................................ 38

Figure 29: Top level timing diagram .................................................................................................................. 39

Figure 30: audioProcessor black box ................................................................................................................. 40

Figure 31: ledDriver black box .......................................................................................................................... 40

Figure 32: Timing diagram for the TLC59281 ..................................................................................................... 41

Figure 33: adcDriver black box .......................................................................................................................... 41

Figure 34: Timing diagram for the TLC541 ......................................................................................................... 41

Figure 35: clockDivider black box ...................................................................................................................... 42

Figure 36: interfaceDriver2 black box ............................................................................................................... 42

Figure 37: cmdBank black box .......................................................................................................................... 43

Figure 38: frameBuilder black box .................................................................................................................... 43

Figure 39: codecDriver black box ...................................................................................................................... 44

Figure 40: Timing diagram for LM4550 ............................................................................................................. 44

Figure 41: Block diagram of LM4550 ................................................................................................................. 45

Figure 42: summer9x2ch black box ................................................................................................................... 45


Figure 43: gainAtten black box .......................................................................................................................... 46

Figure 44: Scaled integer multiplication process ............................................................................................... 46

Figure 45: lut black box ..................................................................................................................................... 47

Figure 46: lut module transfer function ............................................................................................................ 47

Figure 47: scaled integer multiplication/division error analysis ......................................................................... 47

Figure 48: error for scaled integer multiplication/division vs. two inputs .......................................................... 48

Figure 49: ledLut black box ............................................................................................................................... 48

Figure 50: multiplier black box .......................................................................................................................... 48

Figure 51: clockManager black box ................................................................................................................... 49

Figure 52: f1-48k through f9-48k black box ....................................................................................................... 50

Figure 53: Magnitude response of FIR filters ..................................................................................................... 52

Equation 1: Wavelength calculation for TLC59281 serial bus ............................................................................. 26

Equation 2: Drive current calculation for TLC59281 programming resistor selection ......................................... 26

Equation 3: ADC precision calculation ............................................................................................................... 26

Equation 4: Wavelength calculation for TLC541L serial bus ............................................................................... 27

Table 1 Graphic Equalizer Requirements and Specifications ............................................................................... 7

Table 2: Description of components ................................................................................................................. 11

Table 3: Interface Cable Pin out ........................................................................................................................ 13

Table 4: PCB Artwork Color Legend ................................................................................................................... 15

Table 5: 3.3V current estimation for peripheral board ...................................................................................... 35

Table 6: 5V current estimation for peripheral board ......................................................................................... 35

Table 7: Software used for the firmware design flow ........................................................................................ 37

Table 8: multiplier IP CORE configuration information ...................................................................................... 49

Table 9: clockManager IP CORE configuration information ............................................................................... 49

Table 10: FIR Filter specifications ...................................................................................................................... 50

Table 11: FIR filter coefficient naming scheme .................................................................................................. 51

Table 12: Bill of Materials and Total Cost ........................................................................................................ 120

Table 13: Gantt chart showing actual project progress ................................................................................... 121


Abstract: A graphic equalizer is a device that adjusts the tonal quality of an audio signal [1]. When sound is converted

from a digital format to analog sound waves, there are amplification and transducing steps in-between the two

formats. Common devices to perform these tasks are speakers, amplifiers, DACs, etc. Many of these devices

exhibit a non-uniform frequency response over the range of human hearing. Thus, it is possible that certain

frequency ranges of the audio signal will be amplified and others will be attenuated. To counteract this, an

audio equalizer can be used to boost and attenuate certain frequency ranges within the signal, to counteract

the undesirable response of the playback equipment. The equalizer can also be used to attenuate or amplify

frequency ranges in the signal that the user finds desirable, such as boosting the bass or attenuating ranges

common to certain instruments. In this way, a graphic equalizer provides the user with a highly customizable

and intuitive audio experience.

Chapter 1: introduction This project seeks to implement the functionality of a graphic equalizer on a physical hardware platform, for

the processing of real time audio signals, using digital signal processing techniques. For this project, there are

four main sections of design: signal processing hardware, signal processing firmware, peripheral hardware, and

peripheral interfacing firmware. The end goal for the project is to implement a hardware system that is capable

of performing an audio equalizing function on real-time signals. It should be able to do this fast enough that the

user cannot hear the delay caused by the signal processing.

The traditional approach to creating consumer-grade audio equalizers is to use a bank of analog FIR filters [2].

Typically, the low and high frequencies are handled by 1st order high and low-pass "shelving filters." The other

bands are each modified by individual band-pass filters. These filters are typically of the second order type. This

requires precision analog components, and component matching. The approach used in this project is to

implement these filters digitally. A digital implementation of these filters will create a system that requires less

tuning, and is less likely to have its performance change over time. This methodology also has the possibility to

reduce cost and system complexity, as the implementation of digital systems becomes cheaper.


Chapter 2: Requirements and Specifications

Most of the requirements for the project were chosen based on existing specifications for entry-level graphic

equalizer systems that are currently being manufactured. Table 1 shows the initial requirements and

specifications for this project.

Table 1 Graphic Equalizer Requirements and Specifications

Marketing

Requirements

Engineering

Specifications Justification

1 The equalizer should have a minimum of nine

frequency bands that can be adjusted.

Typically, graphic equalizers have at least 9

frequency bands that can be adjusted. Many of

the higher scale models have more bands.

Without an adequate number of bands, the user

many not be able to achieve the frequency

response that they desire.

1 The attenuation/amplification of each

frequency band should have a minimum range

of +/-12dB.

+/- 12dB allows for an amplitude amplification

of 4x, or an attenuation of 0.25x. This allows

reasonable manipulation of the signal, without

causing extreme rescaling of the signal.

2 As a user input, the system should have one

physical adjustment knob or slider to adjust

the amplification/attenuation for each

individual frequency band.

Knobs and sliders are quick to operate, and they

are intuitive for users.

3 Each band should have a graphic indicator of

the peak amplitude in that frequency band,

taken as a time average.

Physical displays cannot update fast enough to

display real-time information, and the

calculation of real-time information would take

significant processing power. Thus, a less

frequently updated, time averaged signal is

appropriate.

4 For audio input and output connections,

standard stereo (three conductor) 3.5mm jacks

are to be used.

These connections are available on most

consumer audio equipment, and will make

interfacing easy.

4 The system should use line level signals for

both the audio input and audio output.

This will make interfacing with consumer

devices easy, as most devices output line level

signals, and most amplifiers can accept line

level signals as an input.

1 The system should have a time delay of 45

microseconds or less

This is equivalent to 2 sampling periods of the

audio signal, and should be sufficient to for

real-time audio processing.

Marketing Requirements

1. The system should implement a graphic equalizer functionality for audio signals.

2. The system should have easy to manipulate user controls, to adjust the desired frequency response.

3. The system should have a graphic output that displays the peak amplitude of each frequency band.

4. The system should interface with other standard audio equipment.


Chapter 3: Functional Decomposition & Description

Theory of Operation: This project implements the functionality of a graphic equalizer on a DSP-optimized FPGA. By nature, FPGAs are

able to handle many tasks simultaneously. Thus, in this project the FPGA performs all of the following tasks in

parallel:

Send and receive PCM audio samples to and from the LM4550 audio codec. The codec also must be

configured properly at system startup.

Interface with the ADC to sample the positions of 9 slider switches, which represent the desired

frequency response of the system.

Perform audio filtering, using DSP techniques, to adjust the tonal quality of the audio input signal. This

is accomplished by using nine FIR filters in parallel, one for each frequency band, to adjust the response

of each frequency band. The outputs of these nine filters are then summed up to generate the output

audio signal.

Display an approximation of the spectrum of the output audio signal, by detecting the peak amplitude

in each frequency band, and displaying these values on the LEDs by interfacing with the LED drivers.

A detailed description of each of these tasks is provided later in the report.

Top Level Block Diagram:

Audio Input Signal (left & right channels)

Maximum 0.5Vpk-pk

Mains Power

120VRMS, Max 200mA

User Input

Nine slider switches

Filtered Audio Output Signal (left & right chan)

Maximum 3.5Vpk-pk

Audio Spectrum Visualization

Nine LED bar graph displaysGraphic Equalizer

Figure 1: Top Level Block Diagram

At the most abstracted level, the Graphic Equalizer requires an audio signal as an input, mains power, and user

input from the slider switches, as shown in Figure 1. The audio input signal is the signal to be filtered by the

graphic equalizer. The mains power provides power to the entire system, and the user input from the slider

switches determines the frequency response of the graphic equalizer. The outputs are the filtered audio, which

is potentially larger in magnitude than the input audio, and the LED bar graphs, which represent the spectrum

of the filtered audio signal.


System Level Block Diagram:

Legend:

3.3

V

3.3

V

(to

all

drive

rs)

TLC541L

11-channel, 8-bit ADC

TLC59281

16-channel LED driver

TLV1117-33

3.3V linear regulator

1.2

V, 1

.8V

,

2.5

V, 3

.3V

3.3V

Digilent Atlys Power Supplies

(Switching Regulators)

AC-Link

Serial Interface

TLC59281


TLC59281


TLC59281


TLC59281


LEDs

LEDs

LEDs

LEDs

LEDs

12

0V

AC

60

Hz

+5V120VAC to +5VDC power

supply

+5V

switched

+5

V

sw

itch

ed

Power Switch

TI A

DC

Se

ria

l In

terf

ace

(n

on

-sta

nd

ard

)

TI L

ED

Drive

r S

eria

l In

terf

ace

(n

on

-sta

nd

ard

)

Spartan-6 LX45

FPGA

Slide Pot Position

Bank of 9 slide

potentiometers

Audio Input

Audio Output

LM4550 AC-97

Audio Codec

Atlys FPGA

Development Board

Peripheral Board

Analog Signal

Power

Digital Signal

Analog Voltage References

AD

C R

efe

ren

ce

Vo

lta

ge

s

Figure 2: System Level Block Diagram

The system level block diagram in Figure 2 shows how all of the major components in the system are connected

to each other. All of these components (and others) are identified in Figure 3, Figure 4, Figure 5, Figure 6 and

are briefly described in Table 2. A more in-depth description of these components and associated signals is

provided later in the report.


Component Identification:

Figure 3: Assembled view of graphic equalizer for component identification

Figure 4: Disassembled view of graphic equalizer for component identification

2

3 5

7

2 1

5 6

1

4 6

8

3 4 8

7

13

12

10 14

11 9

17

18


Figure 5: AC-DC Power Supply

Figure 6: Bottom View of assembled graphic equalizer for component identification

Table 2: Description of components

Name Ref Description

Peripheral Board 1 The peripheral board is a custom designed PCB, which supports the human interface peripherals. It contains the 9 LED displays (with 8 LEDs each,) 9 slide potentiometers, and all of the circuitry necessary to interface these devices with the FPGA. It has four mounting holes which match the mounting holes on the Atlys FPGA Development Board, allowing it to be mounted on top.

Atlys FPGA Development board

2 The Atlys FPGA development board provides a platform for the Spartan-6 FPGA, Flash ROM memory, LM4550 Audio Codec, power supplies, and all other supporting circuitry.

Line-In Port 3 The line-in port is a line level audio input port. Voltages should be kept below 500mVPk-Pk to prevent waveform clipping on the output. The line-in port is connected to the LM4550 audio codec, via a DC-blocking filter.

Line-Out Port 4 The line-out port is a line level audio output port. Voltages can be expected as high as 3Vpk-pk. The output level is limited by the analog supply of the LM4550. The line-out port is connected to the LM4550 by a DC-blocking filter.

Power Switch 5 The power switch controls all power to the board. The switch must be in the "on" position for system operation, and "off " position while the system is not operational. These positions are indicated on the Atlys FPGA development board silkscreen.

Power Socket 6 The power socket provides a location for power input to the entire system. +5VDC is expected at this port, and is provided by the AC-DC power adapter.

Interface Cable 7 The interface cable is a custom cable which provides power and signal interfaces between the Atlys FPGA development board and the peripheral board. One end of the cable is a standard 40-pin (20x2) 2.54mm pitch connector, which connects to the interface board, and the other end is a 68-pin VHDC (SCSI-3) connector.

TLV1117-33 8 The TLV1117-33 is used to provide +3.3VDC to peripheral board, from the input voltage of +5VDC. This supply is used to power the LEDs and associated driving circuitry.

15

16


TLC59281 9 The TLC59281 is a 16-channel LED driving IC. It is essentially a serially programmable current sink. 5 of these chips are arranged on one serial bus, so that all 72 of the LEDs on the board can be programmed individually (on or off) by the FPGA.

TLC541L 10 The TLC541L is an 11-channel 8-bit SAR ADC. Channels 0-8 are used for sampling the positions of the 9 slide potentiometers. It is interfaced via a serial bus to the FPGA.

SN74LVCH16244A 11 The SN74LVCH16244A is a 16-bit non-inverting line driver. It is used to interface all digital signals between the FPGA and the peripheral board. It is a 3.3V device, but has 5V tolerant inputs. It is mainly used to interface the TLC541L (which is a 5V part) to the FPGA (which is a 3.3V part) but also provides the added assurance of boosting signal strength across long traces with multiple loads.

LM4550 12 The LM4550 is an AC-97 audio codec. It consists of an 18-bit ADC/DAC pair, which provides the analog input/output for the system. It is interfaced to the FPGA via the Intel standard AC-Link interface.

Spartan-6 LX45 13 The Spartan-6 LX45 CSG324C is the FPGA used to control all of the processing and interfacing on the system.

Atlys Power Supplies 14 The Atlys power supplies reside on the Atlys FPGA development board. They provide regulated power for all of the devices on the Atlys FPGA development board.

AC-DC Power Supply 15 The AC-DC power supply converts 120VRMS, 60Hz mains power to +5VDC power, which is supplied to the Atlys FPGA development board.

Flash ROM Memory 16 The Flash ROM memory, N25Q12, is used to store the configuration file for the FPGA, which is loaded on the FPGA when the system is powered on. By default, the system will boot off of the flash ROM memory, which is programmable by USB.

USB Programming Port

17 The USB programming port is used to configure the FPGA or flash ROM memory form a PC, using the Digilent Adept application. It is a micro-USB type port.

ADC Voltage References

18 The ADC voltage references are resistor divider circuits, which provide high and low reference voltages for the TLC541L ADC. These references represent the expected highest and lowest voltages from the slide potentiometers.


Chapter 4: Hardware Design This chapter describes the hardware that was specified, designed, and implemented for this project. This

includes the peripheral board and everything on it, the interface cable, the Atlys FPGA development board, and

some FPGA specifics. Firmware implementations, timing diagrams, and other firmware related topics are

covered in Chapter 5: Firmware Design.

Interface Cable The interface cable is made from a LVD Fast 40 SCSI cable, manufactured by Madison Cable Corp, type 20276,

with 30AWG wires. One end of the cable was cut off, and the jacketing removed, to allow the connection of a

standard 2.54mm pitch female header connection manufactured by FCI, part number 71600-040LF, "quickie"

series, which mates to the Assmann AWHW40G-0202-T-R pin header on the peripheral board. The connector is

shown in Figure 7, and it's pin out is shown in Table 3. The cable was fully tested for continuity and short

circuits using an ohmmeter.

Figure 7: Interface connector, with pin numbers shown

Table 3: Interface Cable Pin out

68-pin conn Pri color Sec color FPGA Pin 40-pin conn Signal

1 brn blu

2 brn yel GND 1 GND

3 brn orn U15 2 LED_SIN

4 brn pnk

5 brn grn GND 5 GND

6 brn ppl M11 6 LED_BLANK

7 brn gry

8 tan gry GND 9 GND

9 orn ppl T12 10 LED_LAT2

10 orn blu

11 orn grn GND 13 GND

12 orn yel

13 pnk orn

14 pnk yel GND 17 GND

15 tan brn

16 pnk tan VCC +3V3

17 tan orn VU 12 +5V

1 2

39 40

1 35

34 68


18 tan grn VU 14 +5V

19 tan ppl VCC +3V3

20 tan yel CLKIN

21 wht yel GND 21 GND

22 wht blu R8 22 LED_LAT4

23 tan blu

24 wht orn GND 25 GND

25 wht pnk U8 26 ADC_CS

26 wht gry

27 wht ppl GND 29 GND

28 wht tan N7 30 ADC_IOCLK

29 wht brn

30 wht grn GND 33 GND

31 pnk blu R7 34 ADC_OUTPUT_BUF

32 pnk grn

33 pnk ppl GND 37 GND

34 pnk gry U5 38 NC

35 blu brn

36 yel brn GND 3 GND

37 orn brn V15 4 LED_SCLK

38 pnk brn

39 grn brn GND 7 GND

40 ppl brn N11 8 LED_LAT1

41 gry brn

42 gry tan GND 11 GND

43 ppl orn

44 blu orn

45 grn orn GND 15 GND

46 yel orn

47 orn pnk

48 yel pnk GND 19 GND

49 brn tan T10 20 LED_LAT3

50 tan pnk VCC +3V3

51 orn tan VU 16 +5V

52 grn tan VU 18 +5V

53 ppl tan VCC +3V3

54 yel tan CLKIN

55 yel wht GND 23 GND

56 blu wht T8 24 LED_LAT5

57 blu tan

58 orn wht GND 27 GND

59 pnk wht V8 28 ADC_INPUT

60 gry wht

61 ppl wht GND 31 GND


62 tan wht P8 32 ADC_SYSCLK

63 brn wht

64 grn wht GND 35 GND

65 blu pnk T7 36 NC

66 grn pnk

67 ppl pnk GND 39 GND

68 gry pnk V5 40 NC

Peripheral Board

Description

The peripheral board serves two purposes: to display the spectrum of the output audio signal on the LED

displays, and to capture the user input from the nine slide potentiometers.

Pins 12, 14, 16 and 18 on the 40-pin connector (J1) provide +5V power to the entire board. This +5V supply is

used directly to power the slide potentiometers, ADC, and analog voltage references. The LED display portion

of the board requires +3.3V, so a linear regulator is used to provide +3.3V to the LEDs and LED driver ICs.

There are two serial busses on the peripheral board, the LED serial bus and the ADC serial bus. The timing

diagrams for these busses are shown in detail in Chapter 5. For signal integrity and interfacing purposes, a line

driver IC is used between all devices on the peripheral board and the FPGA. For more detail, see the

"components" section.

Schematic

The schematic for the peripheral board was entered using PCB Artist, supplied by Advanced Circuits. It is shown

in Figures 8-12. Unfortunately, due to the limitations of the schematic entry software, some of the text on the

schematic cannot be enlarged, and the schematic cannot be exported to another format. Because of this, it is

best that the schematic is viewed in the PCB Artist program, or in the separate PDF documents.

Layout

The PCB layout for the peripheral board was also done using PCB Artist, supplied by Advanced Circuits. The top

and bottom copper layers are shown, with silkscreen information, in Figure 13 and Figure 14. The

accompanying silkscreen for the top and bottom layers are shown in Figure 15 and Figure 16. Note that for the

solder mask images, any white area receives the solder mask, and the non-white areas are exposed copper for

soldering. A color legend for the PCB artwork is given in Table 4.

Table 4: PCB Artwork Color Legend

Layer Artwork Color Via

Through Hole Pad

Top Silkscreen

Top Copper

Top Solder Mask

Top SMT Pads

Bottom Silkscreen

Bottom Copper

Bottom Solder Mask

Bottom SMT Pad

Board Outline


Figure 8: Peripheral Interface Schematic, page 1: Pin header, driver, and linear regulator


Figure 9: Peripheral Interface Schematic, page 2: slide potentiometers, ADC, and analog references


Figure 10: Peripheral Interface Schematic, page 3: LED drivers


Figure 13: Peripheral Interface Board Artwork, top layer copper and silkscreen


Figure 14: Peripheral Interface Board Artwork, bottom layer copper and silkscreen


Figure 15: Peripheral Interface Board Artwork, top layer solder mask


Figure 16: Peripheral Interface Board Artwork, bottom layer solder mask


Components

This section describes the reasons for selecting certain components, and their implementation details. Detailed

timing diagrams, serial bus information, and power consumption information is presented later in this report.

TLC59281 16-Channel, Constant-Current LED Driver

LED driver ICs are necessary for this design. Driving all 72 LEDs directly from the FPGA would require more pins

than are available on the Atlys FPGA development board [3], and would require the FPGA to sink a large

amount of current [4]. The TLC59281 was chosen for the following reasons:

Ability to drive a large number (16) of LEDs per IC [5]. This reduces the total number of drivers required,

and thus reduces board complexity.

Simple serial bus, supporting multiple devices on a single bus [5]. This reduces the number of pins

required on the FPGA, and also reduces board complexity because fewer traces are required for the

serial bus.

LEDs are driven using a constant current source. All of the LEDs on one IC are driven with the same

current, which is programmed by a single resistor [5]. This reduces the total part count by not requiring

one resistor per LED.

Analysis of the TLC59281 serial interface bus voltage levels is shown in Figure 17. This shows that the device will

be able to properly interface with the SN74LVCH16244A and the FPGA, since all of the VOH(min) values are larger

than the corresponding VIH(min) values, and all of the VIL(max) values are larger than the VOL(max) vales. The "BUS"

signal is a 3-bit bus that includes the signals LED_SCLK, LED_SIN and LED_BLANK. These signals are connected to

each TLC59281. Each TLC59281 is connected to its own unique latch signal, LED_LAT1 for driver #1, LED_LAT2

for driver #2, etc. There are 5 drivers and 5 latch signals.

Figure 17: TLC59281 LED Driver serial bus voltage levels


Traces for the TLC59281 serial bus were not routed as transmission lines. The longest trace for this bus is

approximately 20cm, and the maximum clock frequency used is 1.024MHz. Equation 1 shows the calculation of

the wavelength of a 1.024MHz signal on FR-4 PCB, where λ is the wavelength, c is the speed of light, εr is the

relative permittivity, and f is the frequency. Since the wavelength of the signal is greater than 10 times the

longest trace length, arbitrary trace routing is acceptable [6].

𝜆 =𝑐

𝜀𝑟 ∗ 𝑓=

3𝑥108

4.8 ∗ 1.024𝑥106≅ 61𝑚

Equation 1: Wavelength calculation for TLC59281 serial bus

To program the drive current for each LED, the resistor RIREF is chosen using Equation 2 [5]. A drive current of

2mA was experimentally determined to be acceptable (see section on passive/discrete components and

connectors,) so a 24.9KΩ resistor is used for RIREF.

𝐼𝑂𝑈𝑇 (𝐼𝐷𝐸𝐴𝐿 ) = 42 ∗ 1.20

𝑅𝐼𝑅𝐸𝐹= 42 ∗

1.20

24900= 2.02𝑚𝐴

Equation 2: Drive current calculation for TLC59281 programming resistor selection

TLC541L 8-Bit Analog-To-Digital Converter with 11 Inputs

The TLC541L is used to sample the positions of the nine slide potentiometers. An external ADC is required,

because neither the Atlys FPGA development board, nor the Spartan-6 FPGA contain a single ADC. The TLC541L

was chosen for the following reasons:

8-bit precision is sufficient to approximate a continuous scale of movement on the slide

potentiometers (see Equation 3.)

Simple serial interface facilitates ease of integration with the FPGA.

High and low voltage references can be set independently of each other, at any voltage between -0.1V

and 2.5V (for the low voltage reference) and 2.5V to VCC+0.1V (for the high voltage reference. [7]) This

allows for easy dynamic range calibration.

A single TLC541L can sample all nine potentiometers. This dramatically decreases the system

complexity, since only a single ADC and corresponding serial bus is required.

The slide potentiometers have a sliding range of 30mm [8]. Assuming that every ADC PCM value is used over

the range of potentiometer settings, Equation 3 shows that there is one PCM code for each 0.12mm of

potentiometer movement. It is unlikely that a user would be able to discriminate the difference in

potentiometer position of 0.12mm.

𝐴𝐷𝐶 𝑃𝑟𝑒𝑐𝑖𝑠𝑖𝑜𝑛 =𝑆𝑙𝑖𝑑𝑒 𝑝𝑜𝑡𝑒𝑛𝑡𝑖𝑜𝑚𝑒𝑡𝑒𝑟 𝑟𝑎𝑛𝑔𝑒

𝑃𝑜𝑠𝑠𝑖𝑏𝑙𝑒 𝐴𝐷𝐶 𝑃𝐶𝑀 𝑐𝑜𝑑𝑒𝑠=

30𝑚𝑚

28 𝑃𝐶𝑀 𝑐𝑜𝑑𝑒𝑠≅

0.12𝑚𝑚

𝑃𝐶𝑀 𝑐𝑜𝑑𝑒

Equation 3: ADC precision calculation

Analysis of the TLC541L is especially important, because the TLC541L has a supply voltage of +5V, and is

interfacing to components with supply voltages of +3.3V. The analysis of the TLC541L interface bus in Figure 18

shows that even though the supply voltages differ between the TLC541L and the SN74LVCH16244A, they can

still interface with each other.


Figure 18: TLC541L ADC serial bus voltage levels

The traces for the TLC541L serial bus are not routed as transmission lines. Since the serial bus uses a maximum

clock speed of 2.048 MHz, the wavelength on the bus is about 30.5m, as shown in Equation 4. This is much

greater than the longest trace length of approximately 13cm, so arbitrary trace routing is acceptable [6].

𝜆 =𝑐

𝜀𝑟 ∗ 𝑓=

3𝑥108

4.8 ∗ 2.048𝑥106≅ 30.5𝑚

Equation 4: Wavelength calculation for TLC541L serial bus

SN74LVCH16244A 16-Bit Buffer/Driver

The main purpose of the SN74LVCH16244A is to provide proper interfacing between the TLC541L and the

Spartan-6. The Spartan-6 operates on a 3.3V voltage supply [9] [10], and it's inputs are not tolerant of +5V [10].

Thus, the TLC541L could damage the Spartan-6 if they were directly interfaced together. The SN74LVCH16244A

is a 3.3V part, but has 5V tolerant inputs, and the proper voltage levels to facilitate interfacing between the

TLC541L and the Spartan-6. Since the SN74LVCH16244A IC is already on the board, all of the other digital

signals are buffered with it, for added signal integrity.

TLV1117-33 3.3V Linear Regulator

The TLV1117-33 linear voltage regulator is used to generate 3.3V supply voltages for the LEDs and driving

circuitry. It is simple, requires a small number of external components, and provides sufficient output current

for all the devices it powers (see power estimation section.)


Passive/Discrete Components and Connectors

Resistors

For all of the resistors on the peripheral board, Yageo RC series chip resistors are used. These resistors have a

±1% tolerance, 1/8W power rating, wide range of values, and come in the 0805 package, so that they are easy

to solder by hand. They are also inexpensive, at $0.019/each when priced at the quantities used for this

project.

Capacitors

For decoupling capacitors, the Murata GRM219R71C104KA01D 0.1uF ceramic capacitor is used. It has a 16V

rating, which is more than 3 times the largest supply voltage of +5V.

Two different types of capacitors were used for bulk capacitance. When a ceramic capacitor is required, the

Murata GRM21BF51A106ZE15L 10uF capacitor is used. For applications requiring low ESR, the AVX

TPSB107K006R0250 100uF tantalum capacitor is used, because of its low ESR value of 250mΩ.

Diodes

For the TLV1117-33 linear regulator, a 1N914A diode is used as suggested by the datasheet [11]. Although this

diode uses the DO-35 leaded package, it is soldered on to surface mount pads to reduce board complexity. This

diode was used instead of a surface mount part because it was freely available, and would not add cost to the

project.

For the LED displays, Kingbright WP710A10SRC/E red LEDs were chosen, because of their low cost and small

size. The LEDs were experimentally determined to have acceptable brightness at 2mA of supply current.

Connectors

The only connector on the board is the Assmann AWHW40G-0202-T-R pin header. This connector was chosen

because it is an industry standard, and mating connectors are readily available.

Implementation, Testing, and Rework

The board was built and tested in two steps. First, the connector J1 and the power supplies were populated

onto the board. Passive loads were soldered onto the output terminals of the power supplies, to simulate the

loads that they would be driving. The board was then powered on, and the supply voltages were checked. The

+5V supply coming onto the board (J1, pins 12,14,16,18) was good, and the +3.3V supply from the TLV1117-33

was good. However, the +5V supply coming from U14 was very low, and U14 was too hot to touch. After

multiple debugging attempts of U14, it was removed from the board, and the +5V_REG net was jumped directly

to the +5V net, shown in Figure 19. There were no further problems using the +5V net as a supply voltage for

the ADC circuit. Another problem found during board testing was in incorrect connection to the slide

potentiometers. The nine ADC inputs were supposed to be connected to the potentiometer wiper, pin 2.

Instead, they were connected to a NC body pin, resulting in a constant voltage at the ADC inputs, regardless of

wiper position. This situation was remedied by placing a jumper between pin 2 of the slide potentiometers, and

the incorrectly connected body pin, as shown in Figure 20. After this rework, the slide potentiometers worked

as expected.

For a functional test of the board, the entire board was populated. Using a test program written and

programmed onto the FPGA, the slide potentiometer values were read from the ADC, and those values were

displayed on the corresponding LED banks. This proved that the peripheral board functioned as planned.

The fully populated board is shown in Figure 21 and Figure 22.


Figure 19: Rework #1: +5V_REG and +5V nets connected with wire

Figure 20: Rework #2: Jumper soldered onto slide potentiometers to connect wiper to ADC input

Jumper U14 Removed

Jumper (9x)


Figure 21: Peripheral board, fully populated, top view


Figure 22: Peripheral board, fully populated, bottom view


Atlys FPGA Development Board

Specification

The Spartan-6 FPGA was chosen as the FPGA for this project, mainly because of its low cost and rich feature set.

The most important feature of the Spartan-6 is it's DSP48A1 slices, which provide DSP building blocks to make

the implementation of DSP systems much more efficient. At an academic price of $199, the Digilent Atlys was

the least expensive Spartan-6 development board available, and yet still has a multitude of useful features, but

was found to have some drawbacks.

The following specifications were required of the chosen FPGA development board:

Spartan-6 FPGA with at least 54 DSP48A1 slices. The FIR filters used in this project require between 2

and 6 DSP48A1 slices each, depending on their configuration [12]. 54 DSP48A1 slices should provide

sufficient resources to implement the required 9 filters.

External connector to connect to the peripheral interface board, with a minimum of 20 GPIO pins,

ground pins, and power supply pins.

Audio Codec, or ADC and DAC with precise sampling rate of at least 40kHz.

Flash ROM memory, to store FPGA programming file when the power is turned off.

Since the Digilent Atlys FPGA development board met the above specifications, it was chosen for this project.

Implementation Issues

There were some implementation issues with the Atlys FPGA development board, all concerning the LM4550

audio codec. The first problem with the board was noise present at a power supply pin of the LM4550, and the

second was output noise on the line-out channel of theLM4550.

LM4550 Power Supply Noise

The digital supply pin VDD2 (pin 9) of the LM4550 was found to have almost 1VPk-Pk noise, at approximately

25MHz, shown in Figure 23. This is very significant, since the supply voltage is only 3.3V. This noise was caused

by a low-pass LC filter, present on pin 9 [9]. The resonant frequency of this LC filter is approximately 5.8MHz,

which is not the same as the 25MHz noise, but is within the same order of magnitude. To correct this, L1 was

removed from the Atlys FPGA development board, and was replaced with a solder bridge, shown in Figure 24.

An extra 0.01uF ceramic decoupling capacitor was also added in parallel to C27. After this rework, the noise on

pin 9 was approximately 10mVPk-Pk, a significant improvement.

LM4550 Line-Out Noise

When attempting to use the LM4550 to play audio or arbitrary waveforms, there is an unwanted noise source

that is added to the line-out signal. This noise is approximately 800mVPk-Pk, or 121mVRMS (using a σ=6.6.)

Figure 25 shows the default Atlys test program (from Digilent) outputting a constant PCM code of 0 to the

LM4550. Channel 2 (green) shows this output is actually very noisy, and the purple trace shows the FFT of

channel 2. The noise frequency is approximately 300kHz. Figure 26 shows a loopback test of the LM4550.

Channel 1 (orange) is connected to the line-in port, and shows a clean input sine wave. Channel 2 (green)

shows the line-out port, with noise present. The purple trace shows the FFT of channel 2, indicating noise at

about 340kHz. This noise is likely due to improper layout of the LM4550 on the Atlys FPGA development board

and not improper LM4550 configuration/communication, since the test program provided by Digilent shows

the same noise, and the noise is much higher than the Nyquist frequency. A remedy to this problem is outside


of the scope of this project. Thankfully, the noise is far above the range of human hearing, and does not appear

to affect audio quality.

Figure 23: Supply noise on LM4550, pin 9, VDD2. CH1 connected to pin 9 of LM4550.


Figure 24: Rework #3: L1 replaced by solder bridge, and additional capacitor added in parallel to C27

Figure 25: Output of Atlys test program, showing 300kHz noise on LM4550 line-out port. CH1: irrelevant, CH2: LM4550 line-out, M: FFT of CH2

solder

bridge

0.01uF capacitor

added


Figure 26: Loopback test of LM4550, showing 340kHz noise on line-out port. CH1: Line-in. CH2: line-out. M: FFT of CH2

Power Estimation The main areas of concern for power estimation are the amount of power drawn through the four +5V supply

pins of the interface cable, and the amount of power supplied on the peripheral board by the TLV1117-33.

Table 5 shows an estimate of the maximum current drawn from the TLV1117-33, and Table 6 shows an

estimate of the current drawn from the four +5V supply pins of the interface cable. The peripheral board 3.3V

supply only draws a maximum of 345mA, which is less than half of its rated output current of 800mA. The total

amount of current drawn through the four +5V supply pins of the interface cable is 354mA, and it is capable of

supplying 1A.

Table 5: 3.3V current estimation for peripheral board

Part Current @ +3.3V

LEDs, D1-D73 2mA * 72

LED drivers, U2-U6 40mA * 5

Buffer, U1 500uA

Total: 345mA

Table 6: 5V current estimation for peripheral board

Part Current @ +5V

TLV1117-33, U8 345mA

Potentiometer resistor dividers, analog references

543uA * 11

ADC, U13 3mA

Total: 354mA


Chapter 5: Firmware Design

Firmware Development Toolchain Firmware for this project is written entirely in VHDL. It is written in a very modular fashion, so that all of the

individual components can be tested, and reused for another purpose if necessary. A combination of software

tools were used for firmware development. The design flow is shown in Figure 27, and details are given in Table

7.

Xilinx ISE

Matlab

divisionError.m Error Simulation

Results

lut.vhd

Filter coefficient lists

(Xilinx .coe files)

FIR filter cores User created

source code atlysGeneral.ucf

Device programming

file

Spartan-6 FPGA

filters48k.fda

FDATool

CORE Generator

Xilinx Toolchain

Digilent Adept

Figure 27: Firmware development design flow


Table 7: Software used for the firmware design flow

Software Version Vendor Description and Use

Xilinx ISE 13.4 (64-bit) Xilinx The Xilinx ISE software suite is used to perform all of the VHDL synthesis, placement, routing, and programming file generation. In order to target the Spartan-6 device, the free Webpack license is insufficient. For this project, the System Edition Evaluation license was used. In order to properly use this license, the Trial License (which is installed by default with ISE) must be removed.

Matlab R2010a, 7.10.0.499 (64-bit) Mathworks Matlab was used to run FDATool. The Matlab script divisionError.m also generates a lookup table for use in the firmware, and analyzes the error associated with that lookup table.

CORE Generator 13.4 (64-bit) Xilinx The core generator was used to run the Xilinx FIR Compiler 5.0, which uses the coefficient files generated with FDATool to generate filters for VHDL.

FDATool 4.7 Mathworks FDATool is a component of the Matlab Signal Processing Toolkit and is used to generate FIR filter coefficients from filter specifications.

Digilent Adept 2.4.2 Digilent The Digilent Adept program is used in conjunction with the Atlys hardware to configure the FPGA. It is an alternative to direct JTAG programming with the Xilinx system cable.

Top level Firmware Overview

Top Level Firmware Block Diagram

Figure 28 shows how all of the individual firmware modules are arranged within the top level firmware module,

audioProcessor. For more information on how the firmware interfaces with the peripheral board, see Figure 2.

Signals and busses colored in blue represent the audio signal processing chain, from end to end. Audio is

sampled by the LM4550 at a rate of 48KHz. Audio samples from the LM4550 are sent to the audDriver module,

which communicates with the LM4550 using the AC-Link serial bus. Once the audio input samples are read

from the serial bus, they are sent to all nine FIR filters. The filters also sample at 48KHz, and read in a new

sample shortly after a sample is placed on their input by the audDriver module. Each filter separates out a

unique section of the spectrum, which is then sent to the corresponding gainAtten module. The gainAtten

module provides ±12dB of gain/boost based on the slider switch positions, which are decoded form the TLC541

serial bus by the interfaceDriver module. All of the outputs from each gainAtten module, which are still

individual sections of the full spectrum, are recombined into a broad band signal in the summer9x2ch module.

the resulting signal is sent back to the audDriver module, which places the output audio samples on the AC-Link

serial bus, to be sent back to the LM4550 and ultimately to the line-out port.


Peripheral Board

Atlys FPGA Development Board

Spartan-6 LX45 FPGA

f1_48k f2_48k f3_48k f4_48k f5_48k f6_48k f7_48k f8_48k f9_48k

gainAtten gainAtten gainAtten gainAtten gainAtten gainAtten gainAtten gainAtten gainAtten

lut lut lut lut lut lut lut lut lut

ledLut ledLut ledLut ledLut ledLut ledLut ledLut ledLut ledLut

audDriver

frameBuilder

cmdBank

summer9x2ch

interfaceDriver2

multiplier multiplier multiplier multiplier multiplier multiplier multiplier multiplier multiplier

adcDriver ledDriverclockDivider

clockManager

TL

C5

92

81

Se

ria

l B

us

TL

C5

41

Se

ria

l B

us

LM4550

10

0M

Hz S

yste

m C

lock

100MHz

Oscillator

Line-Out

Line-In

LM

45

50

Se

ria

l B

us

Figure 28: Top level block diagram of firmware


Top level timing diagram

Figure 29 shows the timing diagram that a right channel audio signal would follow, as it is filtered by FIR filter

#1. The entire process is synchronous to the AUDSYNC signal, which has a frequency of 48KHz, which is the

sampling rate. Once the audDriver module has extracted a new audio sample from the AC-Link bus, it asserts

the codecDataOk signal, which causes the filters (in the case of this example, filter 1) to begin processing. When

the filter is done processing, it's output is placed on the signal pregam1_r, which is the input to the

gain/attenuation module, which provides gain or attenuation to the signal. The signal is then summed together

with the signals from all other frequency bands, and is placed on the audioOut_r signal. On the next rising edge

of AUDSYNC, the audDriver module latches in the value of audioOut_r, sends it to the LM4550 over the AC-Link

bus, and the process begins all over again.

AUDSYNC

Audio In Sample n-1audioIn_r Audio In Sample n

codecDataOk

Filtered Sample n-1 Filtered Sample npregam1_r

Gain/attenuated Sample n-1 Gain/attenuated Sample ng1out_r ???

Summed Sample n-1 Summed Sample n???audioOut_r

Figure 29: Top level timing diagram

System Level Clock Distribution

The entire system uses the 12.288MHz signal BITCLK, which is generated from the LM4550, as a clock. This

ensures that both the LM4550 and the firmware on the FPGA are running on exactly the same clock. Early

implementations used a divided-down version of the 100MHz system clock to run the FPGA firmware, and

there were problems with phase drift between the LM4550 clock and the FPGA clock. The problem with this

system, however, is that the 12.288MHz clock is not available when the LM4550 is in the reset state. Thus, it

cannot be used as a counter to create a long reset signal. To get around this, the 100MHz system clock is used

to drive a counter, which generates a long reset at system startup.


Firmware Modules

audioProcessor

The audioProcessor module is the top level VHDL module, and contains all of the other modules in this design.

It's black box diagram is shown in Figure 30.

Figure 30: audioProcessor black box

ledDriver

The ledDriver module, shown in Figure 31, communicates with each TLC59281 LED driver IC using the timing

diagram shown in Figure 32, which was adapted from the TLC59281 datasheet from Texas Instruments. It is

controlled by the interfaceDriver2 module.

Figure 31: ledDriver black box


Figure 32: Timing diagram for the TLC59281

adcDriver

the adcDriver module, shown in Figure 33, communicates with the TLC541 ADC, using the timing diagram

shown in Figure 34, which is adopted from the TLC541 datasheet from Texas Instruments. When the CS line is

asserted low, data transmission begins, and 16 clock cycles are sent on the SCLK line. Every communication

consists of sending a 4-bit address, and receiving an 8-bit PCM value. The received PCM value corresponds to

the ADC channel belonging to the address sent during the previous communication.

Figure 33: adcDriver black box

Figure 34: Timing diagram for the TLC541


clockDivider

The clockDivider module, shown in Figure 35, is a simple clock divider that is used in the interfaceDriver2

module. It is necessary because the slowest clock that the Xilinx Clock Management Tile can generate is not low

enough for the needs of the interfaceDriver2 module [13]. The clockDivider module takes in a 2.048MHz clock,

and divides it down to a 1.024MHz clock, and a 4KHz clock.

Figure 35: clockDivider black box

interfaceDriver2

The interfaceDriver2 module, shown in Figure 36, controls the adcDriver and ledDriver modules. The adcDriver

module can only communicate with one ADC channel at a time, and the ledDriver module can only

communicate with one TLC59281 at a time. The interfaceDriver2 module employs a time-division multiplexing

scheme to interface with each TLC59281 and ADC channel every 4KHz.

Figure 36: interfaceDriver2 black box


cmdBank

The cmdBank module, shown in Figure 37, is a basic lookup table, which stores configuration data to configure

the LM4550. This data is used by the frameBuilder module, to assemble data packets for the AC-Link serial bus.

Figure 37: cmdBank black box

frameBuilder

The frameBuilder module, shown in Figure 38, uses data from the cmdBank module to assemble data packets

to place on the AC-Link serial bus.

Figure 38: frameBuilder black box

codecDriver

The codecDriver module, shown in Figure 39, is a device driver for the LM4550 audio codec. It communicates

with the LM4550 using the timing diagram shown in Figure 40. The communication protocol is the AC-Link

serial interface protocol, defined by Intel [14]. It is a bidirectional serial bus, which simultaneously sends and

receives configuration information and audio input/output data. Each data packet is made up of 13 time slots.

12 of the time slots are 20 clock cycles long, and the first time slot is 16 clock cycles long. These data packets

are assembled by the frameBuilder module.


Figure 39: codecDriver black box

Figure 40: Timing diagram for LM4550

The LM4550 has an analog signal chain with adjustable gain/attenuation amplifiers and analog multiplexers to

direct the signal flow through the device. Figure 41 shows the block diagram of the LM4550, which is adapted

from the datasheet from National Semiconductor. The signal path used is shown in yellow, and registers

programmed at configuration have their addresses shown in red.


Figure 41: Block diagram of LM4550

summer9x2ch

The summer9x2ch module, shown in Figure 42, is a 9-input, two channel, twos-compliment summation block.

Its purpose is to recombine all of the signals after they have been separated into individual frequency bands

and adjusted for gain or attenuation.

Figure 42: summer9x2ch black box

1A

1C

18

02


gainAtten

the gainAtten module, shown in Figure 43, is a lookup table implementation of scaled integer multiplication

and division. In order for the gainAtten module to be able to provide both gain and attenuation, it must be able

to perform multiplication and division operations, and these operations must be preformed entirely with

integer math. The initial problem with this is that multiplying/dividing by integers has a finite resolution. For

example, you can only multiply and divide by 1, 2, 3, etc. Multiplication by 1.2, for example, is not possible. In

order to achieve a finer resolution, the product of the multiplication/division containing the decimal value is

scaled by a power of two, so that it can be represented as an integer. It is then multiplied by the data signal,

and the result is divided by the same scaling factor used before. This process, shown in Figure 44, allows a

single multiplier module to perform both multiplication and division. The lut module, which is a lookup table,

performs both scale factor multiplication, and conversion between a linear input scale and logarithmic input

scale. More information on this module is given in the following lut section, along with rounding error analysis.

Figure 43: gainAtten black box

Multiplier

Au

dio

Sa

mp

le

Tw

os-c

om

plim

en

t 18

-bit

lutScaled value

Unsigned 10-bit, 68-954

PCM codes from ADC

Unsigned 8-bit, 0-255

Right shift by 10

Am

plifie

d/A

tten

ua

ted

au

dio

sa

mp

le

Tw

os-c

om

plim

en

t 28

-bit

Am

plifie

d/A

tten

ua

ted

au

dio

sa

mp

le

Tw

os-C

om

plim

en

t 18

-bit

Figure 44: Scaled integer multiplication process


lut

The lut module, shown in Figure 45, is a lookup table which converts 8-bit PCM values from the ADCs to 10-bit

values which are both multiplied by a scale factor and converted to a logarithmic scale. This lookup table is

produced by the script divisionError.m, which is listed in Appendix B. The transfer function for the lut module is

shown in Figure 46, which is produced from divisionError.m. Figure 47 is also produced from divisionError.m,

and shows the maximum error when the multiplication/division operation is preformed, for all input PCM

values. The percent error for very small values is high because these values are very close to zero. However, the

number of high error values is very small compared to the input range of values. Figure 48 is similar to Figure

47, and shows all possible error values. Once again, the largest error occurs at small PCM values, but most of

the possible values have small error associated with them.

Figure 45: lut black box

Figure 46: lut module transfer function

Figure 47: scaled integer multiplication/division error analysis


Figure 48: error for scaled integer multiplication/division vs. two inputs

ledLut

the ledLut module, shown in Figure 49, is a lookup table to convert the twos-compliment PCM codes of each

frequency band to an encoding scheme that can be displayed on the LED banks, representing the approximate

magnitude of the PCM value. It essentially takes the absolute value of the signed PCM code, and assigns one of

eight amplitude values, which are displayed on the LED banks.

Figure 49: ledLut black box

multiplier

The multiplier module, shown in Figure 50, is generated using the Xilinx Multiplier IP CORE. It uses

combinational logic to produce the product of one signed and one unsigned bus. The implementation details

are listed in Table 8. Each multiplier uses approximately 188 LUT6 blocks on the FPGA.

Figure 50: multiplier black box


Table 8: multiplier IP CORE configuration information

Specification Value

IP CORE version Xilinx.com:ip:mult_gen:11.2

Multiplier Type Parallel Multiplier

Port A Data Type Signed

Port A Data Width 18

Port B Data Type Unsigned

Port B Data Width 10

Multiplier Construction Use LUTs

Optimization Options Speed Optimized

Use Custom Output Width Unchecked

Pipeline Stages 0

clockManager

The clockManager module, shown in Figure 51, is an implementation of the Xilinx Clocking Wizard IP CORE. It is

used to convert the BITCLK signal, from the LM4550, from 12.288MHz to 24.576MHz and 2.048MHz. Important

configuration information is shown in Table 9. The Clocking Wizard IP CORE is used because it can take

advantage of FPGA hardware resources to multiply and divide clocks with minimum clock jitter, making it a

better alternative to using combinational logic.

Figure 51: clockManager black box

Table 9: clockManager IP CORE configuration information

Specification Value

IP CORE version Xilinx.com:ip:clk_wiz_3.3

Frequency synthesis Checked

Phase Alignment Checked

Minimize Power Unchecked

Dynamic Phase Shift Unchecked

Mode Auto Selection

Jitter Optimization Balanced

Input Jitter Unit UI

Input Clock Input Frequency 12.288MHz

Input Jitter 0.010

Source Single ended clock capable pin

CLK_OUT1 Output Frequency 12.288MHz

CLK_OUT1 Phase 0.000

CLK_OUT1 Duty Cycle (%) 50.000

CLK_OUT1 Drives BUFG










Reset Checked

Locked Unchecked

Input_clk_stopped Unchecked

Status Unchecked

Clk_valid Checked

Clock feedback source Automatic control on-chip

Allow override mode Unchecked

f1_48K through f9_48K

The FIR filters represent the heart of the signal processing chain. Nine FIR filters are used in parallel, and are

named f1-f9. All of the filters were designed using FDATool, employing the equiripple method. The filter

coefficients created using FDATool were exported both to Xilinx .coe files, and to the Matlab file filterCoe.mat.

The .coe files were used by the FIR Compiler 5.0 Xilinx IP CORE generator to create synthesizable FIR filters.

Each filter has the same inputs and outputs, shown in Figure 52. The .coe files used to generate the filters are

listed in Table 11, and the FIR Compiler 5.0 configuration settings are listed in Table 10. Figure 53 was

generated from the Matlab script filterPlotter.m, and shows the individual magnitude response of each FIR

filter, and the combined response of all of the filters together.

The FIR Compiler is used here because it takes advantage of the DSP48A1 hardware slices contained on the

Spartan-6 FPGA [12]. This allows efficient filter computation.

Figure 52: f1-48k through f9-48k black box

Table 10: FIR Filter specifications

Specification Value

IP CORE version Xilinx.com:ip:fir_complier:5.0

Select source COE File


Coefficient file Various, see Table 11

Number of coefficient sets 1

Filter type Single rate

Number of channels 1

Select format Frequency specification

Input sampling frequency 0.048MHz

Clock frequency 24.576 for f1-f3, 12.288 for f4-f9

Filter architecture Systolic multiply accumulate

Use reloadable coefficients Unchecked

Coefficient structure Inferred

Coefficient type Signed

Coefficient width 16

Number of data paths 2

Input data type Signed

Input data width 17

Input data fractional bits 0

Output rounding mode Non-symmetric rounding down

Output width 18

Registered output checked

Optimization goal Area

SCLR Unchecked

ND Checked

CE unchecked

Data buffer type, coefficient buffer type, input buffer type, output buffer type, performance for other storage

automatic

Table 11: FIR filter coefficient naming scheme

Filter Name Coefficient file Number of Coefficients

f1_48K f1_450pt.coe 451

f2_48K f2_460pt.coe 461

f3_48K f3_400pt.coe 401

f4_48K f4_200pts.coe 201

f5_48K f5_101pt.coe 101

f6_48K f6_101pt.coe 101

f7_48K f7_101pt.coe 101

f8_48K f8_101pt.coe 101

f9_48K f9_101pt.coe 101


Figure 53: Magnitude response of FIR filters


Appendix A: VHDL Source Code audioProcessor.vhd

------------------------------------------------------------------------------- 1 -- audioProcessor.vhd --------------------------------------------------------- 2 -- Author: Anthony Giardina -- 3 -- For: Graphic Audio EQ Senior Project -- 4 -- Last Modified: 5/29/2012 -- 5 -- Purpose: This is the top level module for the audio equalizer project. It -- 6 -- connects all other modules in the project togheter, and interfaces -- 7 -- all of the nessecary signals. -- 8 ------------------------------------------------------------------------------- 9 ------------------------------------------------------------------------------- 10 11 library IEEE; 12 use IEEE.STD_LOGIC_1164.ALL; 13 use IEEE.NUMERIC_STD.ALL; 14 use Ieee.std_logic_unsigned.all; 15 16 entity audioProcessor is 17 Port ( 18 -- System clock from onboard oscillator, 100MHz. 19 sysClk : in STD_LOGIC; 20 -- System reset from switch. Active low. 21 sysReset: in STD_LOGIC; 22 -- Debug connector on Atlys board 23 JB : out std_logic_vector (7 downto 0); 24 -- Debug LEDs on Atlys board 25 led: out std_logic_vector(7 downto 0); 26 27 -- Signals to LM4550 28 BITCLK: in std_logic; 29 AUDSYNC: out std_logic; 30 AUDRST: out std_logic; 31 AUDSDI: in std_logic; 32 AUDSDO: out std_logic; 33 34 -- Signals to peripheral board 35 ADC_DATA_OUT : in std_logic; 36 ADC_SYSCLK : out std_logic; 37 ADC_IOCLK : out std_logic; 38 ADC_ADDR_INPUT : out std_logic; 39 ADC_CS_C : out std_logic; 40 LED_SIN : out std_logic; 41 LED_BLANK : out std_logic; 42 LED_SCLK : out std_logic; 43 LED_LAT : out std_logic_vector (4 downto 0) 44 ); 45 end audioProcessor; 46 47 architecture Behavioral of audioProcessor is 48 -- resetGenerator is a counter used for generating a long reset 49 -- at system startup, or when the reset button is pressed. 50 signal resetGenerator: std_logic_vector (23 downto 0); 51 -- Reset signals, which are toggled at system startup: 52 signal shortReset: std_logic; 53 signal longReset: std_logic; 54 signal notSysReset: std_logic; 55 -- CLK_VALID signal indicates that the clock management tile is 56 -- functioning properly. 57 signal CLK_VALID: std_logic; 58 -- System clocks: 59 signal clk12_288M: std_logic; 60 signal clk12_288M_buf: std_logic; 61 signal clk2_048M: std_logic; 62 signal clk24_576M: std_logic; 63 -- Debug signal between the audioProcessor and interface modules: 64 signal intDebug: std_logic_vector (7 downto 0); 65 -- Debug signal between the audioProcessor and the audio module: 66


signal audDebug : std_logic_vector ( 7 downto 0); 67 -- Buffer signals for internal use 68 signal bufAUDSYNC: std_logic; 69 signal bufAUDSDO: std_logic; 70 signal bufAUDRST: std_logic; 71 -- Syncronization signals: 72 signal codecDataOk: std_logic; 73 signal codecIntfcSync: std_logic; 74 -- PCM signals, left and right, coming from the line-in port 75 signal audioIn_r : std_logic_vector(17 downto 0); 76 signal audioIn_l : std_logic_vector(17 downto 0); 77 -- PCM signals, left and right, going to the line-out port. 78 signal audioOut_r : std_logic_vector(17 downto 0); 79 signal audioOut_l : std_logic_vector(17 downto 0); 80 -- Signals that connect the outputs from the gain/atten modules 81 -- to the summation module. 82 signal g1out_r : std_logic_vector(17 downto 0); 83 signal g1out_l : std_logic_vector(17 downto 0); 84 signal g2out_r : std_logic_vector(17 downto 0); 85 signal g2out_l : std_logic_vector(17 downto 0); 86 signal g3out_r : std_logic_vector(17 downto 0); 87 signal g3out_l : std_logic_vector(17 downto 0); 88 signal g4out_r : std_logic_vector(17 downto 0); 89 signal g4out_l : std_logic_vector(17 downto 0); 90 signal g5out_r : std_logic_vector(17 downto 0); 91 signal g5out_l : std_logic_vector(17 downto 0); 92 signal g6out_r : std_logic_vector(17 downto 0); 93 signal g6out_l : std_logic_vector(17 downto 0); 94 signal g7out_r : std_logic_vector(17 downto 0); 95 signal g7out_l : std_logic_vector(17 downto 0); 96 signal g8out_r : std_logic_vector(17 downto 0); 97 signal g8out_l : std_logic_vector(17 downto 0); 98 signal g9out_r : std_logic_vector(17 downto 0); 99 signal g9out_l : std_logic_vector(17 downto 0); 100 -- Ready, Ready For Data, and Need Data signals. These are useful 101 -- for debugging filter timing, but they are not nessesary for 102 -- the operation of the system. 103 signal rfd1 : STD_LOGIC; 104 signal rdy1 : STD_LOGIC; 105 signal nd1 : std_logic; 106 signal rfd2 : STD_LOGIC; 107 signal rdy2 : STD_LOGIC; 108 signal nd2 : std_logic; 109 signal rfd3 : STD_LOGIC; 110 signal rdy3 : STD_LOGIC; 111 signal nd3 : std_logic; 112 signal rfd4 : STD_LOGIC; 113 signal rdy4 : STD_LOGIC; 114 signal nd4 : std_logic; 115 signal rfd5 : STD_LOGIC; 116 signal rdy5 : STD_LOGIC; 117 signal nd5 : std_logic; 118 signal rfd6 : STD_LOGIC; 119 signal rdy6 : STD_LOGIC; 120 signal nd6 : std_logic; 121 signal rfd7 : STD_LOGIC; 122 signal rdy7 : STD_LOGIC; 123 signal nd7 : std_logic; 124 signal rfd8 : STD_LOGIC; 125 signal rdy8 : STD_LOGIC; 126 signal nd8 : std_logic; 127 signal rfd9 : STD_LOGIC; 128 signal rdy9 : STD_LOGIC; 129 signal nd9 : std_logic; 130 -- LED output signals. Each signal corrosponds to a bank of LEDs: 131 signal led1 : std_logic_vector (7 downto 0); 132 signal led2 : std_logic_vector (7 downto 0); 133 signal led3 : std_logic_vector (7 downto 0); 134 signal led4 : std_logic_vector (7 downto 0); 135


signal led5 : std_logic_vector (7 downto 0); 136 signal led6 : std_logic_vector (7 downto 0); 137 signal led7 : std_logic_vector (7 downto 0); 138 signal led8 : std_logic_vector (7 downto 0); 139 signal led9 : std_logic_vector (7 downto 0); 140 -- ADC input signals. Each signal corrosponds to a slide pot: 141 signal adc1 : std_logic_vector (7 downto 0); 142 signal adc2 : std_logic_vector (7 downto 0); 143 signal adc3 : std_logic_vector (7 downto 0); 144 signal adc4 : std_logic_vector (7 downto 0); 145 signal adc5 : std_logic_vector (7 downto 0); 146 signal adc6 : std_logic_vector (7 downto 0); 147 signal adc7 : std_logic_vector (7 downto 0); 148 signal adc8 : std_logic_vector (7 downto 0); 149 signal adc9 : std_logic_vector (7 downto 0); 150 -- These signals are used to connect the FIR filter outputs to the 151 -- gain/atten module inputs. 152 signal pregam9_l: std_logic_vector(17 downto 0); 153 signal pregam9_r: std_logic_vector(17 downto 0); 154 signal pregam8_l: std_logic_vector(17 downto 0); 155 signal pregam8_r: std_logic_vector(17 downto 0); 156 signal pregam7_l: std_logic_vector(17 downto 0); 157 signal pregam7_r: std_logic_vector(17 downto 0); 158 signal pregam6_l: std_logic_vector(17 downto 0); 159 signal pregam6_r: std_logic_vector(17 downto 0); 160 signal pregam5_l: std_logic_vector(17 downto 0); 161 signal pregam5_r: std_logic_vector(17 downto 0); 162 signal pregam4_l: std_logic_vector(17 downto 0); 163 signal pregam4_r: std_logic_vector(17 downto 0); 164 signal pregam3_l: std_logic_vector(17 downto 0); 165 signal pregam3_r: std_logic_vector(17 downto 0); 166 signal pregam2_l: std_logic_vector(17 downto 0); 167 signal pregam2_r: std_logic_vector(17 downto 0); 168 signal pregam1_l: std_logic_vector(17 downto 0); 169 signal pregam1_r: std_logic_vector(17 downto 0); 170 171 -- The rest of the architecture statement is simply components. Their 172 -- function is described in further detail where they are instantiated. 173 COMPONENT ledLut 174 PORT( 175 bandPcm : IN std_logic_vector(17 downto 0); 176 ledOut : OUT std_logic_vector(7 downto 0) 177 ); 178 END COMPONENT; 179 180 COMPONENT interfaceDriver2 181 PORT( 182 ADC_DATA_OUT : IN std_logic; 183 reset : IN std_logic; 184 clk2ish : IN std_logic; 185 debug: out std_logic_vector (7 downto 0); 186 led1_in : IN std_logic_vector(7 downto 0); 187 led2_in : IN std_logic_vector(7 downto 0); 188 led3_in : IN std_logic_vector(7 downto 0); 189 led4_in : IN std_logic_vector(7 downto 0); 190 led5_in : IN std_logic_vector(7 downto 0); 191 led6_in : IN std_logic_vector(7 downto 0); 192 led7_in : IN std_logic_vector(7 downto 0); 193 led8_in : IN std_logic_vector(7 downto 0); 194 led9_in : IN std_logic_vector(7 downto 0); 195 ADC_SYSCLK : OUT std_logic; 196 ADC_IOCLK : OUT std_logic; 197 ADC_ADDR_INPUT : OUT std_logic; 198 ADC_CS_C : OUT std_logic; 199 LED_SIN : OUT std_logic; 200 LED_BLANK : OUT std_logic; 201 LED_SCLK : OUT std_logic; 202 LED_LAT : OUT std_logic_vector(4 downto 0); 203 adc1_out : OUT std_logic_vector(7 downto 0); 204


adc2_out : OUT std_logic_vector(7 downto 0); 205 adc3_out : OUT std_logic_vector(7 downto 0); 206 adc4_out : OUT std_logic_vector(7 downto 0); 207 adc5_out : OUT std_logic_vector(7 downto 0); 208 adc6_out : OUT std_logic_vector(7 downto 0); 209 adc7_out : OUT std_logic_vector(7 downto 0); 210 adc8_out : OUT std_logic_vector(7 downto 0); 211 adc9_out : OUT std_logic_vector(7 downto 0) 212 ); 213 END COMPONENT; 214 215 COMPONENT codecDriver 216 PORT( 217 BITCLK : IN std_logic; 218 AUDSDI : IN std_logic; 219 in_pcm_r : IN std_logic_vector(17 downto 0); 220 in_pcm_l : IN std_logic_vector(17 downto 0); 221 shortReset : in std_logic; 222 longReset: in std_logic; 223 debug : out std_logic_vector (7 downto 0); 224 AUDSYNC : OUT std_logic; 225 AUDRST : OUT std_logic; 226 AUDSDO : OUT std_logic; 227 out_pcm_r : OUT std_logic_vector(17 downto 0); 228 out_pcm_l : OUT std_logic_vector(17 downto 0); 229 intfcSync : OUT std_logic; 230 dataOk : OUT std_logic 231 ); 232 END COMPONENT; 233 234 component clockManager 235 port 236 (-- Clock in ports 237 CLK_IN1 : in std_logic; 238 -- Clock out ports 239 CLK_OUT1 : out std_logic; 240 CLK_OUT2 : out std_logic; 241 CLK_OUT3 : out std_logic; 242 RESET : in std_logic; 243 CLK_VALID : out std_logic 244 ); 245 end component; 246 247 COMPONENT summer9x2ch 248 PORT( 249 clock : IN std_logic; 250 in1_r : IN std_logic_vector(17 downto 0); 251 in1_l : IN std_logic_vector(17 downto 0); 252 in2_r : IN std_logic_vector(17 downto 0); 253 in2_l : IN std_logic_vector(17 downto 0); 254 in3_r : IN std_logic_vector(17 downto 0); 255 in3_l : IN std_logic_vector(17 downto 0); 256 in4_r : IN std_logic_vector(17 downto 0); 257 in4_l : IN std_logic_vector(17 downto 0); 258 in5_r : IN std_logic_vector(17 downto 0); 259 in5_l : IN std_logic_vector(17 downto 0); 260 in6_r : IN std_logic_vector(17 downto 0); 261 in6_l : IN std_logic_vector(17 downto 0); 262 in7_r : IN std_logic_vector(17 downto 0); 263 in7_l : IN std_logic_vector(17 downto 0); 264 in8_r : IN std_logic_vector(17 downto 0); 265 in8_l : IN std_logic_vector(17 downto 0); 266 in9_r : IN std_logic_vector(17 downto 0); 267 in9_l : IN std_logic_vector(17 downto 0); 268 out_r : OUT std_logic_vector(17 downto 0); 269 out_l : OUT std_logic_vector(17 downto 0) 270 ); 271 END COMPONENT; 272 273


component f1_48k 274 port ( 275 clk: in std_logic; 276 nd: in std_logic; 277 rfd: out std_logic; 278 rdy: out std_logic; 279 din_1: in std_logic_vector(16 downto 0); 280 din_2: in std_logic_vector(16 downto 0); 281 dout_1: out std_logic_vector(17 downto 0); 282 dout_2: out std_logic_vector(17 downto 0)); 283 end component; 284 -- 285 component f2_48k 286 port ( 287 clk: in std_logic; 288 nd: in std_logic; 289 rfd: out std_logic; 290 rdy: out std_logic; 291 din_1: in std_logic_vector(16 downto 0); 292 din_2: in std_logic_vector(16 downto 0); 293 dout_1: out std_logic_vector(17 downto 0); 294 dout_2: out std_logic_vector(17 downto 0)); 295 end component; 296 297 component f3_48k 298 port ( 299 clk: in std_logic; 300 nd: in std_logic; 301 rfd: out std_logic; 302 rdy: out std_logic; 303 din_1: in std_logic_vector(16 downto 0); 304 din_2: in std_logic_vector(16 downto 0); 305 dout_1: out std_logic_vector(17 downto 0); 306 dout_2: out std_logic_vector(17 downto 0)); 307 end component; 308 309 component f4_48k 310 port ( 311 clk: in std_logic; 312 nd: in std_logic; 313 rfd: out std_logic; 314 rdy: out std_logic; 315 din_1: in std_logic_vector(16 downto 0); 316 din_2: in std_logic_vector(16 downto 0); 317 dout_1: out std_logic_vector(17 downto 0); 318 dout_2: out std_logic_vector(17 downto 0)); 319 end component; 320 321 component f5_48k 322 port ( 323 clk: in std_logic; 324 nd: in std_logic; 325 rfd: out std_logic; 326 rdy: out std_logic; 327 din_1: in std_logic_vector(16 downto 0); 328 din_2: in std_logic_vector(16 downto 0); 329 dout_1: out std_logic_vector(17 downto 0); 330 dout_2: out std_logic_vector(17 downto 0)); 331 end component; 332 333 component f6_48k 334 port ( 335 clk: in std_logic; 336 nd: in std_logic; 337 rfd: out std_logic; 338 rdy: out std_logic; 339 din_1: in std_logic_vector(16 downto 0); 340 din_2: in std_logic_vector(16 downto 0); 341 dout_1: out std_logic_vector(17 downto 0); 342


dout_2: out std_logic_vector(17 downto 0)); 343 end component; 344 345 component f7_48k 346 port ( 347 clk: in std_logic; 348 nd: in std_logic; 349 rfd: out std_logic; 350 rdy: out std_logic; 351 din_1: in std_logic_vector(16 downto 0); 352 din_2: in std_logic_vector(16 downto 0); 353 dout_1: out std_logic_vector(17 downto 0); 354 dout_2: out std_logic_vector(17 downto 0)); 355 end component; 356 357 component f8_48k 358 port ( 359 clk: in std_logic; 360 nd: in std_logic; 361 rfd: out std_logic; 362 rdy: out std_logic; 363 din_1: in std_logic_vector(16 downto 0); 364 din_2: in std_logic_vector(16 downto 0); 365 dout_1: out std_logic_vector(17 downto 0); 366 dout_2: out std_logic_vector(17 downto 0)); 367 end component; 368 369 component f9_48k 370 port ( 371 clk: in std_logic; 372 nd: in std_logic; 373 rfd: out std_logic; 374 rdy: out std_logic; 375 din_1: in std_logic_vector(16 downto 0); 376 din_2: in std_logic_vector(16 downto 0); 377 dout_1: out std_logic_vector(17 downto 0); 378 dout_2: out std_logic_vector(17 downto 0)); 379 end component; 380 381 COMPONENT gainAtten 382 PORT( 383 input : IN std_logic_vector(17 downto 0); 384 pcmInput : IN std_logic_vector(7 downto 0); 385 output : OUT std_logic_vector(17 downto 0) 386 ); 387 END COMPONENT; 388 389 begin 390 391 -- Instantiate clock manager. This IP CORE generates and distributes 392 -- the clocks required by the system from the BITCLK signal, which 393 -- comes from the LM4550. 394 masterClock : clockManager 395 port map 396 (-- Clock in ports 397 CLK_IN1 => BITCLK, 398 -- Clock out ports 399 CLK_OUT1 => clk12_288M, 400 CLK_OUT2 => clk24_576M, 401 CLK_OUT3 => clk2_048M, 402 RESET => notSysReset, 403 CLK_VALID => CLK_VALID); 404 405 -- Instantiate the LM4550 driver. 406 audDriver: codecDriver 407 port map( 408 BITCLK => clk12_288M, 409 AUDSYNC => bufAUDSYNC, 410 AUDRST => bufAUDRST, 411


AUDSDI => AUDSDI, 412 AUDSDO => bufAUDSDO, 413 debug => audDebug, 414 in_pcm_r => audioOut_r, 415 in_pcm_l => audioOut_l, 416 out_pcm_r => audioIn_r, 417 out_pcm_l => audioIn_l, 418 shortReset => shortReset, 419 longReset => longReset, 420 dataOk => codecDataOk, 421 intfcSync => codecIntfcSync 422 ); 423 AUDSYNC <= bufAUDSYNC; 424 AUDSDO <= bufAUDSDO; 425 AUDRST <= bufAUDRST; 426 427 -- Instantiate the interfaceDriver, which controls the LED and ADC drivers. 428 Inst_interfaceDriver2: interfaceDriver2 PORT MAP( 429 ADC_DATA_OUT => ADC_DATA_OUT, 430 ADC_SYSCLK => ADC_SYSCLK, 431 ADC_IOCLK => ADC_IOCLK, 432 ADC_ADDR_INPUT => ADC_ADDR_INPUT, 433 ADC_CS_C => ADC_CS_C, 434 LED_SIN => LED_SIN, 435 LED_BLANK => LED_BLANK, 436 LED_SCLK => LED_SCLK, 437 LED_LAT => LED_LAT, 438 reset => longReset, 439 clk2ish => clk2_048M, 440 debug => intDebug, 441 adc1_out => adc1, 442 adc2_out => adc2, 443 adc3_out => adc3, 444 adc4_out => adc4, 445 adc5_out => adc5, 446 adc6_out => adc6, 447 adc7_out => adc7, 448 adc8_out => adc8, 449 adc9_out => adc9, 450 led1_in => led1, 451 led2_in => led2, 452 led3_in => led3, 453 led4_in => led4, 454 led5_in => led5, 455 led6_in => led6, 456 led7_in => led7, 457 led8_in => led8, 458 led9_in => led9 459 ); 460 461 -- Instantiate all 9 of the FIR filters used for audio processing. All of 462 -- these filters are Xilinx FIR Compiler 5.0 Cores. 463 filter1 : f1_48k 464 port map ( 465 clk => clk24_576M, 466 nd => nd1, 467 rfd => rfd1, 468 rdy => rdy1, 469 din_1 => audioIn_l(17 downto 1), 470 din_2 => audioIn_r(17 downto 1), 471 dout_1 => pregam1_l, 472 dout_2 => pregam1_r); 473 474 filter2 : f2_48k 475 port map ( 476 clk => clk24_576M, 477 nd => nd2, 478 rfd => rfd2, 479 rdy => rdy2, 480


din_1 => audioIn_l(17 downto 1), 481 din_2 => audioIn_r(17 downto 1), 482 dout_1 => pregam2_l, 483 dout_2 => pregam2_r); 484 485 filter3 : f3_48k 486 port map ( 487 clk => clk24_576M, 488 nd => nd3, 489 rfd => rfd3, 490 rdy => rdy3, 491 din_1 => audioIn_l(17 downto 1), 492 din_2 => audioIn_r(17 downto 1), 493 dout_1 => pregam3_l, 494 dout_2 => pregam3_r); 495 496 filter4 : f4_48k 497 port map ( 498 clk => clk12_288M, 499 nd => nd4, 500 rfd => rfd4, 501 rdy => rdy4, 502 din_1 => audioIn_l(17 downto 1), 503 din_2 => audioIn_r(17 downto 1), 504 dout_1 => pregam4_l, 505 dout_2 => pregam4_r); 506 507 filter5 : f5_48k 508 port map ( 509 clk => clk12_288M, 510 nd => nd5, 511 rfd => rfd5, 512 rdy => rdy5, 513 din_1 => audioIn_l(17 downto 1), 514 din_2 => audioIn_r(17 downto 1), 515 dout_1 => pregam5_l, 516 dout_2 => pregam5_r); 517 518 filter6 : f6_48k 519 port map ( 520 clk => clk12_288M, 521 nd => nd6, 522 rfd => rfd6, 523 rdy => rdy6, 524 din_1 => audioIn_l(17 downto 1), 525 din_2 => audioIn_r(17 downto 1), 526 dout_1 => pregam6_l, 527 dout_2 => pregam6_r); 528 529 filter7 : f7_48k 530 port map ( 531 clk => clk12_288M, 532 nd => nd7, 533 rfd => rfd7, 534 rdy => rdy7, 535 din_1 => audioIn_l(17 downto 1), 536 din_2 => audioIn_r(17 downto 1), 537 dout_1 => pregam7_l, 538 dout_2 => pregam7_r); 539 540 filter8 : f8_48k 541 port map ( 542 clk => clk12_288M, 543 nd => nd8, 544 rfd => rfd8, 545 rdy => rdy8, 546 din_1 => audioIn_l(17 downto 1), 547 din_2 => audioIn_r(17 downto 1), 548 dout_1 => pregam8_l, 549


dout_2 => pregam8_r); 550 551 filter9 : f9_48k 552 port map ( 553 clk => clk12_288M, 554 nd => nd9, 555 rfd => rfd9, 556 rdy => rdy9, 557 din_1 => audioIn_l(17 downto 1), 558 din_2 => audioIn_r(17 downto 1), 559 dout_1 => pregam9_l, 560 dout_2 => pregam9_r); 561 562 -- Assign all of the "New Data" pins for each FIR filter to the codecDataOk 563 -- signal. This ensures that all of the FIR filters will be syncronized, as 564 -- they will all begin to process data on the first rising clock edge after 565 -- the codecDataOk signal is asserted. 566 nd1 <= codecDataOk; 567 nd2 <= codecDataOk; 568 nd3 <= codecDataOk; 569 nd4 <= codecDataOk; 570 nd5 <= codecDataOk; 571 nd6 <= codecDataOk; 572 nd7 <= codecDataOk; 573 nd8 <= codecDataOk; 574 nd9 <= codecDataOk; 575 576 577 -- Instantiate all of the gain/attenuation modules. These modules adjust the 578 -- gain and attenuation of each audio signal coming out of every FIR filter, 579 -- based on the data received from the ADC. 580 gam1r: gainAtten PORT MAP( 581 input => pregam1_r , 582 pcmInput => adc1, 583 output => g1out_r 584 ); 585 586 gam1l: gainAtten PORT MAP( 587 input => pregam1_l, 588 pcmInput => adc1, 589 output => g1out_l 590 ); 591 592 gam2r: gainAtten PORT MAP( 593 input => pregam2_r , 594 pcmInput => adc2, 595 output => g2out_r 596 ); 597 598 gam2l: gainAtten PORT MAP( 599 input => pregam2_l, 600 pcmInput => adc2, 601 output => g2out_l 602 ); 603 604 gam3r: gainAtten PORT MAP( 605 input => pregam3_r , 606 pcmInput => adc3, 607 output => g3out_r 608 ); 609 610 gam3l: gainAtten PORT MAP( 611 input => pregam3_l, 612 pcmInput => adc3, 613 output => g3out_l 614 ); 615 616 gam4r: gainAtten PORT MAP( 617 input => pregam4_r , 618


pcmInput => adc4, 619 output => g4out_r 620 ); 621 622 gam4l: gainAtten PORT MAP( 623 input => pregam4_l, 624 pcmInput => adc4, 625 output => g4out_l 626 ); 627 628 gam5r: gainAtten PORT MAP( 629 input => pregam5_r , 630 pcmInput => adc5, 631 output => g5out_r 632 ); 633 634 gam5l: gainAtten PORT MAP( 635 input => pregam5_l, 636 pcmInput => adc5, 637 output => g5out_l 638 ); 639 640 641 gam6r: gainAtten PORT MAP( 642 input => pregam6_r , 643 pcmInput => adc6, 644 output => g6out_r 645 ); 646 647 gam6l: gainAtten PORT MAP( 648 input => pregam6_l, 649 pcmInput => adc6, 650 output => g6out_l 651 ); 652 653 654 gam7r: gainAtten PORT MAP( 655 input => pregam7_r , 656 pcmInput => adc7, 657 output => g7out_r 658 ); 659 660 gam7l: gainAtten PORT MAP( 661 input => pregam7_l, 662 pcmInput => adc7, 663 output => g7out_l 664 ); 665 666 667 gam8r: gainAtten PORT MAP( 668 input => pregam8_r , 669 pcmInput => adc8, 670 output => g8out_r 671 ); 672 673 gam8l: gainAtten PORT MAP( 674 input => pregam8_l, 675 pcmInput => adc8, 676 output => g8out_l 677 ); 678 679 gam9r: gainAtten PORT MAP( 680 input =>pregam9_r , 681 pcmInput => adc9, 682 output => g9out_r 683 ); 684 685 gam9l: gainAtten PORT MAP( 686 input => pregam9_l, 687


pcmInput => adc9, 688 output => g9out_l 689 ); 690 691 -- Instantiate the summation block, which sums all of the FIR filter outputs 692 -- together into one signal, which is the filtered audio output. 693 Inst_summer9x2ch: summer9x2ch PORT MAP( 694 clock => clk12_288M, 695 in1_r => g1out_r, 696 in1_l => g1out_l, 697 in2_r => g2out_r, 698 in2_l => g2out_l, 699 in3_r => g3out_r, 700 in3_l => g3out_l, 701 in4_r => g4out_r, 702 in4_l => g4out_l, 703 in5_r => g5out_r, 704 in5_l => g5out_l, 705 in6_r => g6out_r, 706 in6_l => g6out_l, 707 in7_r => g7out_r, 708 in7_l => g7out_l, 709 in8_r => g8out_r, 710 in8_l => g8out_l, 711 in9_r => g9out_r, 712 in9_l => g9out_l, 713 out_r => audioOut_r, 714 out_l => audioOut_l 715 ); 716 717 -- Instantiate all of the LED lookup tables. One lookup table for each 718 -- frequency band. The lookup tables assign an output to the LEDs, based 719 -- on the PCM balues of that band. 720 ledLut1: ledLut PORT MAP( 721 bandPcm =>g1out_r , 722 ledOut => led1 723 ); 724 ledLut2: ledLut PORT MAP( 725 bandPcm =>g2out_r , 726 ledOut => led2 727 ); 728 729 ledLut3: ledLut PORT MAP( 730 bandPcm =>g3out_r , 731 ledOut => led3 732 ); 733 ledLut4: ledLut PORT MAP( 734 bandPcm =>g4out_r , 735 ledOut => led4 736 ); 737 ledLut5: ledLut PORT MAP( 738 bandPcm =>g5out_r , 739 ledOut => led5 740 ); 741 ledLut6: ledLut PORT MAP( 742 bandPcm =>g6out_r , 743 ledOut => led6 744 ); 745 ledLut7: ledLut PORT MAP( 746 bandPcm =>g7out_r , 747 ledOut => led7 748 ); 749 ledLut8: ledLut PORT MAP( 750 bandPcm =>g8out_r , 751 ledOut => led8 752 ); 753 ledLut9: ledLut PORT MAP( 754 bandPcm =>g9out_r , 755 ledOut => led9 756


); 757 758 -- Reset timer generator --------------------------------------------------- 759 -- This is to generate a long reset on system startup, without relying on 760 -- BITCLK from the LM4550. The longReset and shortReset signals both begin 761 -- at the same time, but the longReset signal lasts longer. The purpose of 762 -- this is to give the LM4550 to set up (which is reset with shortReset) 763 -- before the rest of the system is active (which is reset with longReset). 764 ---------------------------------------------------------------------------- 765 process (sysClk, sysReset) begin 766 if rising_edge(sysClk) then 767 if sysReset = '0' then 768 resetGenerator <= "000000000000000000000000"; 769 longReset <= '0'; 770 shortReset <= '0'; 771 elsif resetGenerator = "000000000000000000100000" then 772 shortReset <= '1'; 773 resetGenerator <="000000000000000000100001"; 774 elsif resetGenerator = "111111111111111111111111" then 775 longReset <= '1'; 776 else 777 resetGenerator <= resetGenerator +"000000000000000000000001"; 778 end if; 779 end if; 780 end process; 781 notSysReset <= not(shortReset); 782 ---------------------------------------------------------------------------- 783 784 -- Debug ports, for system development. These control the outputs to the 8 785 -- LEDs and the 8-pin PMOD connector on the Atlys board. 786 led <= "00000000"; 787 JB(0) <= '0'; 788 JB(1) <= '0'; 789 JB(2) <= '0'; 790 JB(3) <= '0'; 791 JB(4) <= '0'; 792 JB(5) <= '0'; 793 JB(6) <= '0'; 794 JB(7) <= '0'; 795 796 end Behavioral;797


codecDriver.vhd

------------------------------------------------------------------------------- 1 -- audDriver.vhd -------------------------------------------------------------- 2 -- Author: Anthony Giardina -- 3 -- For: Graphic Audio EQ Senior Project -- 4 -- Last Modified: 5/29/2012 -- 5 -- Purpose: This module is a driver for the National Semiconductor LM4550 -- 6 -- audio codec. Specifically, the LM4550BVH. It uses the Intel AC-LINK -- 7 -- protocol. It configures registers in the LM4550, and then reads and -- 8 -- writes 18-bit PCM values to the device at 48kHz. -- 9 ------------------------------------------------------------------------------- 10 ------------------------------------------------------------------------------- 11 library IEEE; 12 use IEEE.STD_LOGIC_1164.ALL; 13 use Ieee.std_logic_unsigned.all; 14 use IEEE.NUMERIC_STD.ALL; 15 16 entity codecDriver is 17 Port ( 18 --Communication signals for physical AC-Link connection to codec: 19 BITCLK : in STD_LOGIC; 20 AUDSYNC : out STD_LOGIC; 21 AUDRST : out STD_LOGIC; 22 AUDSDI : in STD_LOGIC; 23 AUDSDO : out STD_LOGIC; 24 debug : out std_logic_vector(7 downto 0); 25 --stereo PCM data stream between codec driver and audio processor: 26 in_pcm_r : in std_logic_vector (17 downto 0); 27 in_pcm_l : in std_logic_vector (17 downto 0); 28 out_pcm_r: out std_logic_vector (17 downto 0); 29 out_pcm_l: out std_logic_vector (17 downto 0); 30 -- Signals for system control and syncronization: 31 shortReset : in std_logic; 32 longReset: in std_logic; 33 intfcSync: out std_logic; 34 dataOk: out std_logic 35 ); 36 end codecDriver; 37 38 architecture Behavioral of codecDriver is 39 40 COMPONENT frameBuilder 41 PORT( 42 pcmL : IN std_logic_vector(17 downto 0); 43 pcmR : IN std_logic_vector(17 downto 0); 44 codecReady : IN std_logic; 45 cmd : IN std_logic_vector(3 downto 0); 46 frame : OUT std_logic_vector(95 downto 0) 47 ); 48 END COMPONENT; 49 50 -- The codecReady bit is set when the LM4550 has signaled that it 51 -- it's power supplies have stabalized, it is internally ready, and 52 -- can accept new data. 53 signal codecReady : std_logic; 54 -- The following two signals are the PCM values which are sent to the 55 -- LM4550, once they are assembled into complete data packets. 56 signal PCM_R : std_logic_vector (17 downto 0); 57 signal PCM_L : std_logic_vector (17 downto 0); 58 -- The following two signals are the PCM values that have been read 59 -- in from the LM4550, from the line-in port. 60 signal PCM_R_IN : std_logic_vector (17 downto 0); 61 signal PCM_L_IN : std_logic_vector (17 downto 0); 62 -- the cmd signal tells the frameBuilder module what frame it should build. 63 -- see where this signal is used for more info: 64 signal cmd: std_logic_vector (3 downto 0); 65


-- the frame signal is the assembled data packet that is sent to the LM4550: 66 signal frame: std_logic_vector (95 downto 0); 67 -- bitCounter is a state machine variable that keeps track of how many clock 68 -- cycles have occured since the beginning of each communication frame 69 -- with the LM4550. 70 signal bitCounter: std_logic_vector (7 downto 0); 71 -- operation counter is a state machine variable that determines the 72 -- value of cmd. 73 signal operationCounter: std_logic_vector (5 downto 0); 74 -- readBackAddr is the address value that is read back from the LM4550 after 75 -- a register is programed. The readBackAddr must match the address that was 76 -- previously written. Same concept for readBackData. 77 signal readBackAddr: std_logic_vector (6 downto 0); 78 signal readBackData: std_logic_vector (15 downto 0); 79 -- lastAddr keeps track of the last address that was written 80 -- for readback verification. Same concept for lastData and lastCodecReady. 81 signal lastAddr : std_logic_vector (6 downto 0); 82 signal lastData: std_logic_vector (15 downto 0); 83 signal lastCodecReady: std_logic; 84 -- This signal exists to complete a case statement, and has no real purpose: 85 signal a: std_logic; 86 -- paddedFrame is the frame signal, with some zeroes padded to the front, 87 -- so that the timing diagram matches properly. 88 signal paddedFrame: std_logic_vector (97 downto 0); 89 -- internal buffer for the AUDSYNC signal: 90 signal sync: std_logic; 91 92 begin 93 94 -- Reset the LM4550. Using the shortReset instead of longReset ensures 95 -- that the LM4550 BITCLK signal, which is required for proper operation 96 -- of most of the firmware, is up and running properly before the rest of 97 -- the firmware comes out of the reset state, since it all uses the 98 -- longReset signal. 99 AUDRST <= shortReset; 100 101 -- Debug connection, for communicating to higher level modules. 102 debug(0) <= '0'; 103 debug(1) <= '0'; 104 debug(2) <= '0'; 105 debug(3) <= '0'; 106 debug(4) <= '0'; 107 debug(5) <= '0'; 108 debug(6) <= '0'; 109 debug(7) <= '0'; 110 111 -- Update the PCM values syncronously, so that they are not accidentally 112 -- read/written when they are being updated/used. 113 process (sync) begin 114 if rising_edge(sync) then 115 116 PCM_R <= in_pcm_r; 117 PCM_L <= in_pcm_l; 118 119 out_pcm_r <= PCM_R_IN; 120 out_pcm_l <= PCM_L_IN; 121 122 end if; 123 end process; 124 125 126 -- Instantiate the frameBuilter module, which assembles the data packets, 127 -- which are then sent to the LM4550. 128 Inst_frameBuilder: frameBuilder PORT MAP( 129 pcmL => PCM_L, 130 pcmR => PCM_R, 131 codecReady => codecReady, 132 cmd => cmd, 133 frame => frame 134


); 135 136 -- Assign values to the AUDSYNC signal and it's buffer: 137 sync <= '1' when (bitCounter >= "00000000" and bitCounter <= "00001111") else 138 '0'; 139 AUDSYNC <= sync; -- buffer so we can use the signal internally. 140 141 -- Assign cmd values, based on the operationCounter state machine. 142 with operationCounter select 143 cmd <= "0000" when "000000", --nothing 144 "0000" when "000001", --nothing 145 "0100" when "000010", --write 146 "1100" when "000011", --request read 147 "0000" when "000100", --read and verify 148 "0110" when "000101", --write 149 "1110" when "000110", --request read 150 "0000" when "000111", --read and verify 151 "0010" when "001000", --write 152 "1010" when "001001", --read 153 "0000" when "001010", --verify 154 "0011" when "001011", --write 155 "1011" when "001100", --read 156 "0000" when "001101", --verify 157 "0000" when others; 158 159 -- This statement places the proper bit of the current frame 160 -- on the AUDSDO pin. 161 AUDSDO <= '0' when longReset = '0' else 162 paddedFrame (96 - to_integer(unsigned(bitCounter))) 163 when bitCounter <= "01011111" else 164 '0'; 165 166 -- Adjust the frame, so that it starts at the proper time. 167 paddedFrame <= "00" & frame; 168 169 -- This process controls the large state machine, which controls the entire 170 -- driver. 171 process (longReset, BITCLK) begin 172 if rising_edge(BITCLK) then 173 if longReset = '0' then 174 -- Syncronous reset: 175 bitCounter <= "11111111"; 176 operationCounter <= "000000"; 177 lastData <= "0000000000000000"; 178 lastAddr <= "0000000"; 179 elsif bitCounter = "11111111" then 180 -- If in the final state, reset the state machine. 181 bitCounter <= "00000000"; 182 -- Latch in the value of codecReady, so we know what to do 183 -- with the PCM values on the next frame. 184 codecReady <= lastCodecReady; 185 if (operationCounter = "000010" or operationCounter = "000101" 186 or operationCounter = "001000" 187 or operationCounter = "001011" ) then 188 -- these are the write operations. 189 -- Proceed to the read/verify operation. 190 lastAddr <= frame(78 downto 72); 191 lastData <= frame(59 downto 44); 192 operationCounter <= operationCounter + "000001"; 193 elsif (operationCounter = "000011" or operationCounter = "000110" 194 or operationCounter = "001001" 195 or operationCounter = "001100" ) then 196 -- Requesting a readback of the previously written 197 -- register. Move along to verification. 198 operationCounter <= operationCounter + "000001"; 199 elsif (operationCounter = "000100" or operationCounter = "000111" 200 or operationCounter = "001010" 201 or operationCounter = "001101") then 202 -- Reading back the previously requested information. 203


-- Make a decision about about the next state, based 204 -- on the validity of the information read back. 205 if (lastAddr = readBackAddr and lastData = readBackData) then 206 -- if the data and address written match the data and address 207 -- read, proceed to the next operation 208 operationCounter <= operationCounter + "000001"; 209 else 210 -- if the read/write data does not match, go to the 211 -- previous state and try again. 212 operationCounter <= operationCounter - "000010"; 213 end if; 214 elsif (operationCounter = "000000" or operationCounter = "000001" ) 215 then 216 -- These are the do nothing operations. 217 -- Just advance to the next operation. 218 operationCounter <= operationCounter + "000001"; 219 end if; 220 else 221 bitCounter <= bitCounter + "00000001"; 222 end if; 223 end if; 224 end process; 225 226 -- This process reads in bits from the AUDSDI pin of rht LM4550 227 -- at the proper time, and also generates syncronization signals 228 -- which are used to syncronize the audio processing filters and 229 -- the interface module. 230 process (longReset, BITCLK) begin 231 if falling_edge(BITCLK) then 232 case bitCounter is 233 --when "00000000" => ; 234 when "00000001" => lastCodecReady <= AUDSDI; 235 --when "00000010" => ; 236 --when "00000011" => ; 237 --when "00000100" => ; 238 when "00000101" => intfcSync <= '1'; 239 when "00000110" => intfcSync <= '0'; 240 --when "00000111" => ; 241 --when "00001000" => ; 242 --when "00001001" => ; 243 --when "00001010" => ; 244 --when "00001011" => ; 245 --when "00001100" => ; 246 --when "00001101" => ; 247 --when "00001110" => ; 248 --when "00001111" => ; 249 --when "00010000" => ; 250 --when "00010001" => ; 251 when "00010010" => readBackAddr(6) <= AUDSDI; 252 when "00010011" => readBackAddr(5) <= AUDSDI; 253 when "00010100" => readBackAddr(4) <= AUDSDI; 254 when "00010101" => readBackAddr(3) <= AUDSDI; 255 when "00010110" => readBackAddr(2) <= AUDSDI; 256 when "00010111" => readBackAddr(1) <= AUDSDI; 257 when "00011000" => readBackAddr(0) <= AUDSDI; 258 --when "00011001" => ; 259 --when "00011010" => ; 260 --when "00011011" => ; 261 --when "00011100" => ; 262 --when "00011101" => ; 263 --when "00011110" => ; 264 --when "00011111" => ; 265 --when "00100000" => ; 266 --when "00100001" => ; 267 --when "00100010" => ; 268 --when "00100011" => ; 269 --when "00100100" => ; 270 when "00100101" => readBackData(15) <= AUDSDI; 271 when "00100110" => readBackData(14) <= AUDSDI; 272


when "00100111" => readBackData(13) <= AUDSDI; 273 when "00101000" => readBackData(12) <= AUDSDI; 274 when "00101001" => readBackData(11) <= AUDSDI; 275 when "00101010" => readBackData(10) <= AUDSDI; 276 when "00101011" => readBackData(9) <= AUDSDI; 277 when "00101100" => readBackData(8) <= AUDSDI; 278 when "00101101" => readBackData(7) <= AUDSDI; 279 when "00101110" => readBackData(6) <= AUDSDI; 280 when "00101111" => readBackData(5) <= AUDSDI; 281 when "00110000" => readBackData(4) <= AUDSDI; 282 when "00110001" => readBackData(3) <= AUDSDI; 283 when "00110010" => readBackData(2) <= AUDSDI; 284 when "00110011" => readBackData(1) <= AUDSDI; 285 when "00110100" => readBackData(0) <= AUDSDI; 286 --when "00110101" => ; 287 --when "00110110" => ; 288 --when "00110111" => ; 289 --when "00111000" => ; 290 when "00111001" => PCM_L_IN(17) <= AUDSDI; 291 when "00111010" => PCM_L_IN(16) <= AUDSDI; 292 when "00111011" => PCM_L_IN(15) <= AUDSDI; 293 when "00111100" => PCM_L_IN(14) <= AUDSDI; 294 when "00111101" => PCM_L_IN(13) <= AUDSDI; 295 when "00111110" => PCM_L_IN(12) <= AUDSDI; 296 when "00111111" => PCM_L_IN(11) <= AUDSDI; 297 when "01000000" => PCM_L_IN(10) <= AUDSDI; 298 when "01000001" => PCM_L_IN(9) <= AUDSDI; 299 when "01000010" => PCM_L_IN(8) <= AUDSDI; 300 when "01000011" => PCM_L_IN(7) <= AUDSDI; 301 when "01000100" => PCM_L_IN(6) <= AUDSDI; 302 when "01000101" => PCM_L_IN(5) <= AUDSDI; 303 when "01000110" => PCM_L_IN(4) <= AUDSDI; 304 when "01000111" => PCM_L_IN(3) <= AUDSDI; 305 when "01001000" => PCM_L_IN(2) <= AUDSDI; 306 when "01001001" => PCM_L_IN(1) <= AUDSDI; 307 when "01001010" => PCM_L_IN(0) <= AUDSDI; 308 --when "01001011" => ; 309 --when "01001100" => ; 310 when "01001101" => PCM_R_IN(17) <= AUDSDI; 311 when "01001110" => PCM_R_IN(16) <= AUDSDI; 312 when "01001111" => PCM_R_IN(15) <= AUDSDI; 313 when "01010000" => PCM_R_IN(14) <= AUDSDI; 314 when "01010001" => PCM_R_IN(13) <= AUDSDI; 315 when "01010010" => PCM_R_IN(12) <= AUDSDI; 316 when "01010011" => PCM_R_IN(11) <= AUDSDI; 317 when "01010100" => PCM_R_IN(10) <= AUDSDI; 318 when "01010101" => PCM_R_IN(9) <= AUDSDI; 319 when "01010110" => PCM_R_IN(8) <= AUDSDI; 320 when "01010111" => PCM_R_IN(7) <= AUDSDI; 321 when "01011000" => PCM_R_IN(6) <= AUDSDI; 322 when "01011001" => PCM_R_IN(5) <= AUDSDI; 323 when "01011010" => PCM_R_IN(4) <= AUDSDI; 324 when "01011011" => PCM_R_IN(3) <= AUDSDI; 325 when "01011100" => PCM_R_IN(2) <= AUDSDI; 326 when "01011101" => PCM_R_IN(1) <= AUDSDI; 327 when "01011110" => PCM_R_IN(0) <= AUDSDI; 328 --when "01011111" => ; 329 -- Assert a signal so that he filters know when to begin processing 330 -- data. dataOk is asserted once the PCM values are finished 331 -- being read in from the LM4550. 332 when "01100010" => dataOk <= '1'; 333 when "01100011" => dataOk <= '0'; 334 when others => a <= a; 335 end case; 336 end if; 337 end process; 338 339 end Behavioral; 340


frameBuilder.vhd

------------------------------------------------------------------------------- 1 -- frameBuilder.vhd ----------------------------------------------------------- 2 -- Author: Anthony Giardina -- 3 -- For: Graphic Audio EQ Senior Project -- 4 -- Last Modified: 5/29/2012 -- 5 -- Purpose: This module assembles data packets, which are sent to the LM4550.-- 6 -- It constructs these packets based on the current requested command, -- 7 -- which could be writing or reading a register, and the desired PCM -- 8 -- values to be sent to the LM4550 for output. -- 9 ------------------------------------------------------------------------------- 10 ------------------------------------------------------------------------------- 11 12 library IEEE; 13 use IEEE.STD_LOGIC_1164.ALL; 14 15 entity frameBuilder is 16 Port ( 17 -- Audio output PCM signals, which are sent to the LM4550: 18 pcmL : in STD_LOGIC_VECTOR (17 downto 0); 19 pcmR : in STD_LOGIC_VECTOR (17 downto 0); 20 -- Status of the LM4550, ready or not: 21 codecReady : in STD_LOGIC; 22 -- Desired command: 23 cmd : in STD_LOGIC_VECTOR (3 downto 0); 24 -- Assembled output frame: 25 frame : out STD_LOGIC_VECTOR (95 downto 0) 26 ); 27 end frameBuilder; 28 29 architecture Behavioral of frameBuilder is 30 31 32 COMPONENT cmdBank 33 PORT( 34 cmd : IN std_logic_vector(3 downto 0); 35 CMD_ADDR : OUT std_logic_vector(6 downto 0); 36 CMD_DATA : OUT std_logic_vector(15 downto 0) 37 ); 38 END COMPONENT; 39 40 -- address slot of the communication frame: 41 signal address: std_logic_vector (6 downto 0); 42 -- command slot of the communication frame: 43 signal command: std_logic_vector (15 downto 0); 44 45 begin 46 47 -- Instantiate the command back, which is essentially a lookup table, 48 -- creating the ADDRESS and DATA slots of the communication frame. 49 Inst_cmdBank: cmdBank PORT MAP( 50 cmd => cmd, 51 CMD_ADDR => address, 52 CMD_DATA => command 53 ); 54 55 56 -- Tag Slot ---------------------------------------------------------------- 57 -- Indicate that the frame contains valid data, if the codec is ready 58 -- to accept data. 59 frame (95) <= codecReady; 60 -- Set the control address valid flag: 61 frame (94) <= '0' when codecReady = '0' else -- 1: control address is valid 62 '1' when cmd(3) = '1' or cmd(2) = '1' or cmd(1) = '1' 63 or cmd(0) = '1' else 64 '0'; 65 -- Set the control data valid flag: 66 frame (93) <= '0' when codecReady = '0' else -- 1: control data is valid 67 -- (this is vaild on a write, 68


-- invaild on a read, invalid 69 -- if no cmd at all) 70 '1' when cmd(3) = '0' and (cmd(2) = '1' or cmd(1) = '1' 71 or cmd(0) = '1') else 72 '0'; 73 -- Set the left and right PCM data valid flags: 74 frame (92) <= '0' when codecReady = '0' else -- 1: left PCM data is valid. 75 -- Always send PCM data if 76 -- codec is ready. 77 '1'; 78 frame (91) <= '0' when codecReady = '0' else -- 1: Right PCM data is valid. 79 -- Always send PCM data if 80 -- codec is ready. 81 '1'; 82 -- This is valid slot data for channels that we don't use, so it's always 0: 83 frame (90 downto 84) <= "0000000"; 84 frame (83 downto 80) <= "0000"; -- unused bits stuffed with zeroes. 85 86 -- Control Address slot ---------------------------------------------------- 87 frame (79) <= '0' when codecReady = '0' else -- read or write 88 cmd(3); 89 -- address of register that's the target of the read/write operation 90 frame (78 downto 72) <= "0000000" when codecReady = '0' else 91 address; 92 frame (71 downto 60) <= "000000000000"; -- Unused bits 93 94 -- Control data slot ------------------------------------------------------- 95 -- Data to be written to target register (all zeroes if read operation) 96 frame (59 downto 44) <= "0000000000000000" when codecReady = '0' else 97 command; 98 frame (43 downto 40) <= "0000"; -- unused bits 99 100 -- PCM left slot ----------------------------------------------------------- 101 -- Send PCM data only when the codec is ready 102 frame (39 downto 22) <= "000000000000000000" when codecReady = '0' else 103 pcmL; 104 frame (21 downto 20) <= "00"; -- unused bits 105 106 -- PCM right slot ---------------------------------------------------------- 107 -- send PCM data only when the codec is ready 108 frame (19 downto 2) <= "000000000000000000" when codecReady = '0' else 109 pcmR; 110 frame (1 downto 0) <= "00"; -- unused bits 111 112 end Behavioral; 113


cmdBank.vhd

------------------------------------------------------------------------------- 1 -- cmdBank.vhd ----------------------------------------------------------- 2 -- Author: Anthony Giardina -- 3 -- For: Graphic Audio EQ Senior Project -- 4 -- Last Modified: 5/29/2012 -- 5 -- Purpose: the cmdBank module stores register values, which are used to -- 6 -- configure the LM4550 on startup. It is essentially a large lookup table. -- 7 ------------------------------------------------------------------------------- 8 ------------------------------------------------------------------------------- 9 library IEEE; 10 use IEEE.STD_LOGIC_1164.ALL; 11 use IEEE.NUMERIC_STD.ALL; 12 13 entity cmdBank is 14 Port ( 15 -- Command input: 16 cmd : in STD_LOGIC_VECTOR (3 downto 0); 17 -- Address and Data outputs: 18 CMD_ADDR : out STD_LOGIC_VECTOR (6 downto 0); 19 CMD_DATA : out STD_LOGIC_VECTOR (15 downto 0) 20 ); 21 end cmdBank; 22 23 architecture Behavioral of cmdBank is 24 25 -- All of these signals are used to store register configureation values. 26 -- They are only read, never written. 27 signal micGain: std_logic_vector (6 downto 0); 28 signal sourceSelect: std_logic; 29 signal recGainMute: std_logic_vector(4 downto 0); 30 signal pcmOutGAM: std_logic_vector (5 downto 0); 31 signal headphoneVol: std_logic_vector (5 downto 0); 32 signal masterVol: std_logic_vector (5 downto 0); 33 34 begin 35 36 -- First bit sets mute (1) or unmute (0). 37 -- second bit Sets mic gain to 0dB (0) or +20dB (1). 38 -- Last 5 bits set gain or attn. 00000 -> +12dB. 39 -- 01000 -> 0dB gain. 40 -- 11111 -> 34.5dB gain. 41 micGain <= "0001000"; 42 43 -- Select recording source: mic (0) or line in (1) 44 sourceSelect <= '1'; 45 46 -- Select recording source gain. 47 -- First bit is unmute (0) or mute(1). 48 -- Last 4 bits are gain. 0000 -> 0dB. 49 -- 1111 -> +22.5dB 50 recGainMute <= "00100"; 51 52 -- PCM output from D->A converter gain. 53 -- first bit is unmute (0) or mute(1). 54 -- last 4 bits are 00000 -> +12dB gain. 55 -- 01000 -> 0dB gain. 56 -- 11111 -> -34.5dB gain. 57 pcmOutGAM <= "000111"; 58 59 -- Headphone vol. First bit is unmute (0) or mute (1). 60 -- Last 5 bits are attenuation. 00000 -> 0dB. 61 -- 11111 -> -46.5dB atten. 62 headphoneVol <= "000000"; 63 64 -- Master volume. same as headphone volmue as far as the bits are concerned. 65


masterVol <= "000000"; 66 67 -- CMD: 68 -- 1001: Read Mic Gain (either 0dB or +20dB) 69 -- 1010: Read Record Select (source = 0: mic. Source = 1: line in.) 70 -- 1011: Read Record Gain 71 -- 1100: Read PCM output gain/attn/mute 72 -- 1101: Read Headphone volume 73 -- 1110: Read Master volume 74 -- 0001: Write Mic Gain (either 0dB or +20dB) 75 -- 0010: Write Record Select (source = 0: mic. Source = 1: line in.) 76 -- 0011: Write Record Gain 77 -- 0100: Write PCM output gain/attn/mute 78 -- 0101: Write Headphone volume 79 -- 0110: Write Master volume 80 -- cmd(3) is the leading bit, and determines a write (0) 81 -- or a read (1) operation. If it's a read operation, data field is blank. 82 83 -- Set the register address, based on this lookup table: 84 CMD_ADDR(6 downto 0) <= -- Mic Gain: 85 "0001110" when cmd(2 downto 0) = "001" else 86 -- Rec source: 87 "0011010" when cmd(2 downto 0) = "010" else 88 -- Rec Gain: 89 "0011100" when cmd(2 downto 0) = "011" else 90 -- PCM out Gain/attn/mute: 91 "0011000" when cmd(2 downto 0) = "100" else 92 -- Headphone Volume: 93 "0000100" when cmd(2 downto 0) = "101" else 94 -- Master volume: 95 "0000010" when cmd(2 downto 0) = "110" else 96 "0000000"; 97 98 -- Set the register data, based on a lookup table: 99 CMD_DATA(15 downto 0) <= "0000000000000000" 100 when cmd(3) = '1' else 101 102 -- Mic Gain: 103 micGain(6) & 104 "00000000" & 105 micGain(5) & 106 '0' & 107 micGain(4 downto 0) 108 when cmd(2 downto 0) = "001" else 109 110 -- Rec source: 111 "00000" & 112 sourceSelect & 113 "0000000" & 114 sourceSelect & 115 "00" 116 when cmd(2 downto 0) = "010" else 117 118 -- Rec Gain: 119 recGainMute(4) & 120 "000" & 121 recGainMute(3 downto 0) & 122 "0000" & 123 recGainMute(3 downto 0) 124 when cmd(2 downto 0) = "011" else 125 126 -- PCM out Gain/attn/mute: 127 pcmOutGAM(5) & 128 "00" & 129 pcmOutGAM(4 downto 0) & 130 "000" & 131 pcmOutGAM(4 downto 0) 132 when cmd(2 downto 0) = "100" else 133 134


-- Headphone Volume: 135 headphoneVol(5) & 136 "00" & 137 headphoneVol (4 downto 0) & 138 "000" & 139 headphoneVol(4 downto 0) 140 when cmd(2 downto 0) = "101" else 141 142 -- Master volume: 143 masterVol(5) & 144 "00" & 145 masterVol(4 downto 0) & 146 "000" & 147 masterVol(4 downto 0) 148 when cmd(2 downto 0) = "110" else 149 150 "0000000000000000"; 151 152 end Behavioral; 153


interfaceDriver2.vhd

------------------------------------------------------------------------------- 1 -- interfaceDriver2.vhd ------------------------------------------------------- 2 -- Author: Anthony Giardina -- 3 -- For: Graphic Audio EQ Senior Project -- 4 -- Last Modified: 5/29/2012 -- 5 -- Purpose: This is a top level driver for the peripheral board. It controls -- 6 -- the LED driver and the ADC driver. -- 7 ------------------------------------------------------------------------------- 8 ------------------------------------------------------------------------------- 9 library IEEE; 10 use IEEE.STD_LOGIC_1164.ALL; 11 use Ieee.std_logic_unsigned.all; 12 13 entity interfaceDriver2 is 14 Port ( 15 -- ADC interface signals 16 ADC_DATA_OUT : IN std_logic; 17 ADC_SYSCLK : OUT std_logic; 18 ADC_IOCLK : OUT std_logic; 19 ADC_ADDR_INPUT : OUT std_logic; 20 ADC_CS_C : OUT std_logic; 21 -- LED driver signals. 22 LED_SIN : out STD_LOGIC; 23 LED_BLANK : out STD_LOGIC; 24 LED_SCLK : out STD_LOGIC; 25 LED_LAT : out STD_LOGIC_VECTOR (4 downto 0); 26 -- Driver reset signal: 27 reset : in STD_LOGIC; 28 -- 2.048MHZ clock: 29 clk2ish : in STD_LOGIC; 30 -- port used for debugging: 31 debug: out std_logic_vector (7 downto 0); 32 -- Data from the ADC 33 adc1_out : out std_logic_vector (7 downto 0); 34 adc2_out : out std_logic_vector (7 downto 0); 35 adc3_out : out std_logic_vector (7 downto 0); 36 adc4_out : out std_logic_vector (7 downto 0); 37 adc5_out : out std_logic_vector (7 downto 0); 38 adc6_out : out std_logic_vector (7 downto 0); 39 adc7_out : out std_logic_vector (7 downto 0); 40 adc8_out : out std_logic_vector (7 downto 0); 41 adc9_out : out std_logic_vector (7 downto 0); 42 -- Data sent to the LEDs 43 led1_in : in std_logic_vector (7 downto 0); 44 led2_in : in std_logic_vector (7 downto 0); 45 led3_in : in std_logic_vector (7 downto 0); 46 led4_in : in std_logic_vector (7 downto 0); 47 led5_in : in std_logic_vector (7 downto 0); 48 led6_in : in std_logic_vector (7 downto 0); 49 led7_in : in std_logic_vector (7 downto 0); 50 led8_in : in std_logic_vector (7 downto 0); 51 led9_in : in std_logic_vector (7 downto 0) 52 ); 53 end interfaceDriver2; 54 55 architecture Behavioral of interfaceDriver2 is 56 57 COMPONENT ledDriver 58 PORT( 59 60 reset : IN std_logic; 61 clk1mhz : IN std_logic; 62 send : IN std_logic; 63 din : IN std_logic_vector(15 downto 0); 64 driverNum : IN std_logic_vector(2 downto 0); 65


LED_SIN : OUT std_logic; 66 LED_BLANK : OUT std_logic; 67 LED_SCLK : OUT std_logic; 68 LED_LAT : OUT std_logic_vector(4 downto 0) 69 ); 70 END COMPONENT; 71 72 COMPONENT clockDivider 73 PORT( 74 reset : IN std_logic; 75 clk2ish : IN std_logic; 76 clk2mhz : OUT std_logic; 77 clk1mhz : OUT std_logic; 78 updateClk : OUT std_logic 79 ); 80 END COMPONENT; 81 82 COMPONENT adcDriver 83 PORT( 84 addressIn : IN std_logic_vector(3 downto 0); 85 send : IN std_logic; 86 clk1mhz : IN std_logic; 87 clk2mhz : IN std_logic; 88 reset : IN std_logic; 89 ADC_DATA_OUT : IN std_logic; 90 dataOut : OUT std_logic_vector(7 downto 0); 91 dataOk : OUT std_logic; 92 ADC_SYSCLK : OUT std_logic; 93 ADC_IOCLK : OUT std_logic; 94 ADC_ADDR_INPUT : OUT std_logic; 95 ADC_CS_C : OUT std_logic 96 ); 97 END COMPONENT; 98 99 -- 1.024MHz clock: 100 signal clk1mhz : std_logic; 101 -- 2.048MHz clock: 102 signal clk2mhz: std_logic; 103 -- Clock which defines the period on which all of the ADC/LED Driver 104 -- devices are updated on: 105 signal updateClk: std_logic; 106 -- Control signal used for LED driver: 107 signal led_send : std_logic; 108 -- Data being sent to an individual LED driver: 109 signal led_din : std_logic_vector (15 downto 0); 110 -- Selects which driver the data is being sent to" 111 signal led_driverNum : std_logic_vector (2 downto 0); 112 -- State variables: 113 signal state : std_logic_vector (3 downto 0); 114 signal count : std_logic_vector (1 downto 0); 115 -- Signals used for rising edge detection: 116 signal lastUclk : std_logic; 117 signal lastUclk2 : std_logic; 118 -- Signals send to the LEDs: 119 signal led1 : std_logic_vector (7 downto 0); 120 signal led2 : std_logic_vector (7 downto 0); 121 signal led3 : std_logic_vector (7 downto 0); 122 signal led4 : std_logic_vector (7 downto 0); 123 signal led5 : std_logic_vector (7 downto 0); 124 signal led6 : std_logic_vector (7 downto 0); 125 signal led7 : std_logic_vector (7 downto 0); 126 signal led8 : std_logic_vector (7 downto 0); 127 signal led9 : std_logic_vector (7 downto 0); 128 -- Signals read back from the ADCs: 129 signal adc1 : std_logic_vector (7 downto 0); 130 signal adc2 : std_logic_vector (7 downto 0); 131 signal adc3 : std_logic_vector (7 downto 0); 132 signal adc4 : std_logic_vector (7 downto 0); 133 signal adc5 : std_logic_vector (7 downto 0); 134


signal adc6 : std_logic_vector (7 downto 0); 135 signal adc7 : std_logic_vector (7 downto 0); 136 signal adc8 : std_logic_vector (7 downto 0); 137 signal adc9 : std_logic_vector (7 downto 0); 138 -- Control signals for the ADC driver: 139 signal adc_addressIn : std_logic_vector(3 downto 0); 140 signal adc_dataOut : std_logic_vector (7 downto 0); 141 signal adc_dataOk : std_logic; 142 signal adc_send : std_logic; 143 -- Used for rising edge detection: 144 signal lastOk : std_logic; 145 146 begin 147 148 -- Optional signals for debugging: 149 debug(0) <= '0'; 150 debug(1) <= '0'; 151 debug(2) <= '0'; 152 debug(3) <= '0'; 153 debug(4) <= '0'; 154 debug(5) <= '0'; 155 debug(6) <= '0'; 156 debug(7) <= '0'; 157 158 -- LED Driver Controller --------------------------------------------------- 159 ---------------------------------------------------------------------------- 160 -- Set the led data in port to the proper LED values, based on which driver 161 -- is being written to, determined by the state variable: 162 led_din <= not(led1(0) & led1(1) & led1(2) & led1(3) & led1(4) & 163 led1(5) & led1(6) & led1(7) & led2) 164 when state = "0000" else 165 not(led3(0) & led3(1) & led3(2) & led3(3) & led3(4) & 166 led3(5) & led3(6) & led3(7) & led4) 167 when state = "0001" else 168 not(led5(0) & led5(1) & led5(2) & led5(3) & led5(4) & 169 led5(5) & led5(6) & led5(7) & led6) 170 when state = "0010" else 171 not(led7(0) & led7(1) & led7(2) & led7(3) & led7(4) & 172 led7(5) & led7(6) & led7(7) & led8) 173 when state = "0011" else 174 not(("11111111" & led9)) when state = "0100" else 175 "0000000000000000"; 176 177 -- Select the driver to write data to, based on the state variable: 178 led_driverNum <= "000" when state = "0000" else 179 "001" when state = "0001" else 180 "010" when state = "0010" else 181 "011" when state = "0011" else 182 "100" when state = "0100" else 183 "111"; -- Invalid driver num, so we don't accidentally 184 -- do something we don't want to do. 185 186 -- Toggle the send pulse, once data has been placed on the output lines: 187 led_send <= '1' when count = "10" else 188 '0'; 189 ---------------------------------------------------------------------------- 190 ---------------------------------------------------------------------------- 191 192 -- ADC Driver Controller --------------------------------------------------- 193 ---------------------------------------------------------------------------- 194 -- Select which ADC address to query for data: 195 adc_addressIn <= "0000" when state = "0000" else 196 "0001" when state = "0001" else 197 "0010" when state = "0010" else 198 "0011" when state = "0011" else 199 "0100" when state = "0100" else 200 "0101" when state = "0101" else 201 "0110" when state = "0110" else 202 "0111" when state = "0111" else 203


"1000" when state = "1000" else 204 "0000"; 205 206 -- Toggle the send signal when data has been placed on the output lines: 207 adc_send <= '1' when count = "10" else 208 '0'; 209 210 -- This process reads the data from the ADC, which belongs to the address 211 -- which was last written to the ADC: 212 process (clk1mhz, adc_dataOk, lastOk, adc_dataOut) begin 213 if rising_edge(clk1mhz) then 214 if ((adc_dataOk = '1') and (lastOk = '0')) then 215 -- Rising edge of dataOk 216 if (state = "0000") then 217 adc9 <= adc_dataOut; 218 elsif (state = "0001") then 219 adc1 <= adc_dataOut; 220 elsif (state = "0010") then 221 adc2 <= adc_dataOut; 222 elsif (state = "0011") then 223 adc3 <= adc_dataOut; 224 elsif (state = "0100") then 225 adc4 <= adc_dataOut; 226 elsif (state = "0101") then 227 adc5 <= adc_dataOut; 228 elsif (state = "0110") then 229 adc6 <= adc_dataOut; 230 elsif (state = "0111") then 231 adc7 <= adc_dataOut; 232 elsif (state = "1000") then 233 adc8 <= adc_dataOut; 234 end if; 235 236 lastOk <= adc_dataOk; 237 else 238 lastOk <= adc_dataOk; 239 end if; 240 end if; 241 end process; 242 ---------------------------------------------------------------------------- 243 ---------------------------------------------------------------------------- 244 245 -- This process detects a rising edge of update clock syncronously to the 246 -- clk1mhz clock, and sets the "count" state machine into motion, which 247 -- controls toggling of the "send" signals to the ADC and LED drivers. 248 process (updateClk, count, clk1mhz, reset, lastUclk) begin 249 if (rising_edge(clk1mhz)) then 250 if (reset = '0') then 251 count <= "11"; 252 lastUclk <= '0'; 253 else 254 if updateClk = '1' and lastUclk = '0' then 255 count <= "00"; 256 lastUclk <= updateClk; 257 258 else 259 lastUclk <= updateClk; 260 if count = "00" then 261 count <= "01"; 262 elsif count = "01" then 263 count <= "10"; 264 elsif count = "11" then 265 count <= "11"; 266 end if; 267 end if; 268 end if; 269 end if; 270 end process; 271 272


-- Process to control the state variable: 273 process (updateClk, state, reset) begin 274 if (reset = '0') then 275 state <= "0000"; 276 elsif (rising_edge(updateClk)) then 277 if (state = "1000") then 278 state <= "0000"; 279 else 280 state <= state + "0001"; 281 end if; 282 end if; 283 end process; 284 285 -- Instantiate ADC driver: 286 Inst_adcDriver: adcDriver PORT MAP( 287 addressIn => adc_addressIn, 288 dataOut => adc_dataOut, 289 dataOk => adc_dataOk, 290 send => adc_send, 291 clk1mhz => clk1mhz, 292 clk2mhz => clk2mhz, 293 reset => reset, 294 ADC_SYSCLK => ADC_SYSCLK, 295 ADC_IOCLK => ADC_IOCLK, 296 ADC_ADDR_INPUT => ADC_ADDR_INPUT, 297 ADC_DATA_OUT => ADC_DATA_OUT, 298 ADC_CS_C => ADC_CS_C 299 ); 300 301 -- Instantiate LED driver: 302 Inst_ledDriver: ledDriver PORT MAP( 303 reset => reset, 304 LED_SIN => LED_SIN, 305 LED_BLANK => LED_BLANK, 306 LED_SCLK => LED_SCLK, 307 LED_LAT => LED_LAT, 308 clk1mhz => clk1mhz, 309 send => led_send, 310 din => led_din, 311 driverNum => led_driverNum 312 ); 313 314 -- Instantiate clock divider, to divide down clocks: 315 Inst_clockDivider: clockDivider PORT MAP( 316 reset => reset, 317 clk2ish => clk2ish, --2.048MHz input clock 318 clk2mhz => clk2mhz, --2.048MHz output clock 319 clk1mhz => clk1mhz, --1.024MHz output clock 320 updateClk => updateClk -- update syncronizing output clock 321 ); 322 323 -- Connect signals together: 324 led1 <= led1_in; 325 led2 <= led2_in; 326 led3 <= led3_in; 327 led4 <= led4_in; 328 led5 <= led5_in; 329 led6 <= led6_in; 330 led7 <= led7_in; 331 led8 <= led8_in; 332 led9 <= led9_in; 333 334 -- Connect signals together: 335 adc1_out <= adc1; 336 adc2_out <= adc2; 337 adc3_out <= adc3; 338 adc4_out <= adc4; 339 adc5_out <= adc5; 340 adc6_out <= adc6; 341


adc7_out <= adc7; 342 adc8_out <= adc8; 343 adc9_out <= adc9; 344 345 end Behavioral; 346


adcDriver.vhd

------------------------------------------------------------------------------- 1 -- adcDriver.vhd -------------------------------------------------------------- 2 -- Author: Anthony Giardina -- 3 -- For: Graphic Audio EQ Senior Project -- 4 -- Last Modified: 5/29/2012 -- 5 -- Purpose: This module controls the TLC541L ADC at the lowest "bit bang" -- 6 -- level. Itsends ADC addressses to the ADC, and reads back data from the -- 7 -- previous address sent. -- 8 ------------------------------------------------------------------------------- 9 ------------------------------------------------------------------------------- 10 11 library IEEE; 12 use IEEE.STD_LOGIC_1164.ALL; 13 use Ieee.std_logic_unsigned.all; 14 use IEEE.NUMERIC_STD.ALL; 15 16 entity adcDriver is 17 Port ( 18 -- addressIn is the ADC analog channel that will be read on the next cycle 19 addressIn : in STD_LOGIC_VECTOR (3 downto 0); 20 -- dataOut is the ADC converison data that belongs to the previously 21 -- send ADC analog channel. 22 dataOut : out STD_LOGIC_VECTOR (7 downto 0); 23 -- dataOk goes high when the conversion data on the output 24 -- bus is valid. 25 dataOk : out STD_LOGIC; 26 -- on the rising edge of send, the driver begins serial 27 -- communication with the device: 28 send : in STD_LOGIC; 29 -- System input clocks: 30 clk1mhz : in STD_LOGIC; 31 clk2mhz : in STD_LOGIC; 32 -- System Reset: 33 reset : in STD_LOGIC; 34 -- Hardware input/output signals for the serial bus: 35 ADC_SYSCLK : out STD_LOGIC; 36 ADC_IOCLK : out STD_LOGIC; 37 ADC_ADDR_INPUT : out STD_LOGIC; 38 ADC_DATA_OUT : in STD_LOGIC; 39 ADC_CS_C : out STD_LOGIC 40 ); 41 end adcDriver; 42 43 architecture Behavioral of adcDriver is 44 45 -- state machine variable: 46 signal state: std_logic_vector (4 downto 0); 47 -- latch the input address, so it doesn't get changed durring 48 -- device communication: 49 signal latchAddressIn: std_logic_vector (3 downto 0); 50 -- ADC output data is assembled on this signal before it 51 -- is latched onto the output register, so that incomplete data 52 -- is not placed on the output: 53 signal dataOutInt: std_logic_vector (7 downto 0); 54 -- dummy signal: 55 signal a: std_logic; 56 -- signal used for syncronouse detection of the send signal: 57 signal lastSend: std_logic; 58 59 begin 60 61 -- 2mhz clock always goes to the ADC, unless in a reset state. 62 ADC_SYSCLK <= clk2mhz when reset = '1' else 63 '0'; 64 -- 1mhz clock goes to the ADC for 8 cycles of data communication: 65


ADC_IOCLK <= not clk1mhz when state >= "00011" and state <= "01010" else 66 '0'; 67 -- drive the chip select signal: 68 ADC_CS_C <= '0' when state >= "00001" and state <= "01010" else 69 '1'; 70 -- place the address bits serially on the serial bus: 71 ADC_ADDR_INPUT <= latchAddressIn(3) when state = "00011" else 72 latchAddressIn(2) when state = "00100" else 73 latchAddressIn(1) when state = "00101" else 74 latchAddressIn(0) when state = "00110" else 75 '0'; 76 77 -- This process detects the a rising edge of the state signal, 78 -- syncronously to the clk1mhz signal, and controls operation 79 -- of the state machine: 80 process (clk1mhz,reset,send, state, ADC_DATA_OUT) begin 81 if rising_edge(clk1mhz) then 82 if (send = '1' and lastSend = '0') then 83 latchAddressIn <= addressIn; 84 state <= "00001"; 85 end if; 86 lastSend <= send; 87 if state = "01100" then 88 dataOut <= dataOutInt; 89 dataOK <= '1'; 90 end if; 91 if state = "00001" then 92 dataOK <= '0'; 93 end if; 94 if state = "00000" then 95 elsif state = "11111" then 96 state <= "00000"; 97 else 98 state <= state + "00001"; 99 end if; 100 end if; 101 end process; 102 103 -- This process reads the data coming from the device over the 104 -- serial bus on the falling edge of the 1MHz clock: 105 process(clk1mhz, state, ADC_DATA_OUT) begin 106 if falling_edge(clk1mhz) then 107 if (state = "00011" ) then 108 dataOutInt(7) <= ADC_DATA_OUT; 109 elsif (state = "00100") then 110 dataOutInt(6) <= ADC_DATA_OUT; 111 elsif (state = "00101") then 112 dataOutInt(5) <= ADC_DATA_OUT; 113 elsif (state = "00110") then 114 dataOutInt(4) <= ADC_DATA_OUT; 115 elsif (state = "00111") then 116 dataOutInt(3) <= ADC_DATA_OUT; 117 elsif (state = "01000") then 118 dataOutInt(2) <= ADC_DATA_OUT; 119 elsif (state = "01001") then 120 dataOutInt(1) <= ADC_DATA_OUT; 121 elsif (state = "01010") then 122 dataOutInt(0) <= ADC_DATA_OUT; 123 end if; 124 end if; 125 end process; 126 127 end Behavioral; 128


ledDriver.vhd

------------------------------------------------------------------------------- 1 -- ledDriver.vhd -------------------------------------------------------------- 2 -- Author: Anthony Giardina -- 3 -- For: Graphic Audio EQ Senior Project -- 4 -- Last Modified: 5/29/2012 -- 5 -- Purpose: This is the low level bit banging driver module for the TLC59281 -- 6 -- LED driving IC. It is designed to be used on a serial bus with 5 devices -- 7 -- and uses a TDM technique to control all of the drivers on the same bus. -- 8 ------------------------------------------------------------------------------- 9 ------------------------------------------------------------------------------- 10 11 library IEEE; 12 use IEEE.STD_LOGIC_1164.ALL; 13 use Ieee.std_logic_unsigned.all; 14 use IEEE.NUMERIC_STD.ALL; 15 16 17 entity ledDriver is 18 Port ( 19 -- System reset: 20 reset: in std_logic; 21 -- Hardware serial bus signals: 22 LED_SIN : out STD_LOGIC; 23 LED_BLANK : out STD_LOGIC; 24 LED_SCLK : out STD_LOGIC; 25 LED_LAT : out STD_LOGIC_VECTOR (4 downto 0); 26 -- Input clock: 27 clk1mhz : in STD_LOGIC; 28 -- Control signals: 29 -- A rising edge of send signals to the ledDriver module to 30 -- begin sending data on the serial bus. 31 send : in STD_LOGIC; 32 -- din is the data that will be sent to the device. 33 din : in STD_LOGIC_VECTOR (15 downto 0); 34 -- driverNum dictates which driver the data contained on the 35 -- din signal will go to. Can have values of 000 to 100. 36 driverNum : in STD_LOGIC_VECTOR (2 downto 0) 37 ); 38 end ledDriver; 39 40 architecture Behavioral of ledDriver is 41 42 -- State variable to control operation of the driver: 43 signal state : std_logic_vector (4 downto 0); 44 -- Internal register, to latch the incoming data on the rising edge of 45 -- send, so that it does not get corrupted durring sending: 46 signal latchDin : std_logic_vector (15 downto 0); 47 -- Decoded "one hot" version of driverNum input signal: 48 signal bankSelect : std_logic_vector (4 downto 0); 49 -- signal used for send signal edge detection: 50 signal lastSend : std_logic; 51 52 begin 53 54 -- Active low reset coming in, device has active high reset. 55 LED_BLANK <= not reset; 56 57 -- Device serial clock is active for 16 cycles: 58 LED_SCLK <= clk1mhz when (state >= "00010" and state <= "10001") else 59 '0'; 60 61 -- Decode the driverNum signal into a one-hot version, used to control 62 -- the LATCH signal on every device: 63 bankSelect <= "00001" when driverNum = "000" else 64 "00010" when driverNum = "001" else 65


"00100" when driverNum = "010" else 66 "01000" when driverNum = "011" else 67 "10000" when driverNum = "100" else 68 "00000"; 69 -- Drive the LATCH signal with the bankSelect signal, unless it's a reset: 70 LED_LAT <= "00000" when reset = '0' else 71 bankSelect when state = "10011" else 72 "00000"; 73 -- This process controls the state machine, and also puts the data bits on 74 -- on the serial bus at the correct time. The state machine is set in 75 -- motion by a rising edge of send, which is syncronously detected on the 76 -- clk1mhz clock. 77 process (reset, clk1mhz,send, state, din, lastSend) begin 78 if (falling_edge(clk1mhz)) then 79 if (send = '1' and lastSend = '0') then 80 latchDin <= din; 81 state <= "00001"; 82 end if; 83 84 lastSend <= send; 85 86 case state is 87 when "00001" => LED_SIN <= latchDin(15); 88 when "00010" => LED_SIN <= latchDin(14); 89 when "00011" => LED_SIN <= latchDin(13); 90 when "00100" => LED_SIN <= latchDin(12); 91 when "00101" => LED_SIN <= latchDin(11); 92 when "00110" => LED_SIN <= latchDin(10); 93 when "00111" => LED_SIN <= latchDin(9); 94 when "01000" => LED_SIN <= latchDin(8); 95 when "01001" => LED_SIN <= latchDin(7); 96 when "01010" => LED_SIN <= latchDin(6); 97 when "01011" => LED_SIN <= latchDin(5); 98 when "01100" => LED_SIN <= latchDin(4); 99 when "01101" => LED_SIN <= latchDin(3); 100 when "01110" => LED_SIN <= latchDin(2); 101 when "01111" => LED_SIN <= latchDin(1); 102 when "10000" => LED_SIN <= latchDin(0); 103 when others => LED_SIN <= '0'; 104 end case; 105 106 if state >= "00001" and state <= "10011" then 107 state <= state + "00001"; 108 elsif state >= "10100" then 109 state <= "00000"; 110 end if; 111 112 end if; 113 end process; 114 115 end Behavioral; 116


clockDivider.vhd

------------------------------------------------------------------------------- 1 -- clockDivider.vhd ----------------------------------------------------------- 2 -- Author: Anthony Giardina -- 3 -- For: Graphic Audio EQ Senior Project -- 4 -- Last Modified: 5/29/2012 -- 5 -- Purpose: This module takes in a 2.048 50% duty cycle clock, and produces -- 6 -- the following 3 output clocks: -- 7 -- > 2.048MHz, 50% duty cycle -- 8 -- > 1.024MHz, 50% duty cycle -- 9 -- > 4.000KHz, 50% duty cycle -- 10 ------------------------------------------------------------------------------- 11 ------------------------------------------------------------------------------- 12 13 library IEEE; 14 use IEEE.STD_LOGIC_1164.ALL; 15 use Ieee.std_logic_unsigned.all; 16 use IEEE.NUMERIC_STD.ALL; 17 18 entity clockDivider is 19 Port ( 20 -- System reset: 21 reset : in STD_LOGIC; 22 -- Input clock: 23 clk2ish : in STD_LOGIC; 24 -- Output clocks: 25 clk2mhz : out STD_LOGIC; 26 clk1mhz : out STD_LOGIC; 27 updateClk : out STD_LOGIC 28 ); 29 end clockDivider; 30 31 architecture Behavioral of clockDivider is 32 33 -- State is a large counter that is used as a clock divider. 34 signal state : std_logic_vector (9 downto 0); 35 36 begin 37 38 -- Counter to increment the state signal by one on every rising edge 39 -- of the 2MHz clock. Only reset once all of the bits are 1, so that 40 -- the duty cycle of every bit is 50%. 41 process (clk2ish, reset) begin 42 if (reset = '0') then 43 state <= "0000000000"; 44 elsif (rising_edge(clk2ish)) then 45 if state = "1111111111" then 46 state <= "0000000000"; 47 else 48 state <= state + "0000000001"; 49 end if; 50 end if; 51 end process; 52 53 -- Assign clocks to bits of the counter. 54 updateClk <= state(8); 55 clk1mhz <= state(0); 56 clk2mhz <= clk2ish; 57 58 end Behavioral; 59


gainAtten.vhd

------------------------------------------------------------------------------- 1 -- gainAtten.vhd -------------------------------------------------------------- 2 -- Author: Anthony Giardina -- 3 -- For: Graphic Audio EQ Senior Project -- 4 -- Last Modified: 5/29/2012 -- 5 -- Purpose: This module provides gain or attenuation to the twos-compliment -- 6 -- PCM codes that come out of each of the band filters, based on the input -- 7 -- PCM value on the pcmInput signal. The values are scaled based on the -- 8 -- lut.vhd lookup table. -- 9 ------------------------------------------------------------------------------- 10 ------------------------------------------------------------------------------- 11 library IEEE; 12 use IEEE.STD_LOGIC_1164.ALL; 13 14 entity gainAtten is 15 Port ( 16 -- Input PCM value, which will be attenuated or amplified: 17 input : in STD_LOGIC_VECTOR (17 downto 0); 18 -- Factor by which the input signal will be scaled: 19 pcmInput : in STD_LOGIC_VECTOR (7 downto 0); 20 -- scaled output: 21 output : out STD_LOGIC_VECTOR (17 downto 0) 22 ); 23 end gainAtten; 24 25 architecture Behavioral of gainAtten is 26 27 -- output of the lookup table: 28 signal lutValue : std_logic_vector (9 downto 0); 29 -- output of the multiplier: 30 signal multOutput : std_logic_vector (27 downto 0); 31 32 33 COMPONENT multiplier 34 PORT ( 35 a : IN STD_LOGIC_VECTOR(17 DOWNTO 0); 36 b : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 37 p : OUT STD_LOGIC_VECTOR(27 DOWNTO 0) 38 ); 39 END COMPONENT; 40 41 42 COMPONENT lut 43 PORT( 44 din : IN std_logic_vector(7 downto 0); 45 dout : OUT std_logic_vector(9 downto 0) 46 ); 47 END COMPONENT; 48 49 begin 50 51 -- Instantiate multiplier, used for multiplying the input 52 -- value and the scaling value together: 53 your_instance_name : multiplier 54 PORT MAP ( 55 a => input, 56 b => lutValue, 57 p => multOutput 58 ); 59 60 -- Instantiate lookup table. The lookup table takes in an 8 61 -- bit value , and outputs scaled integer values on a logarithmic 62 -- scale, which will be used for multiplication. 63 Inst_lut: lut PORT MAP( 64 din => pcmInput, 65


dout => lutValue 66 ); 67 68 -- Shift over by 8 to undo scale factor 69 output(17 downto 0) <= multOutput (27 downto 10); 70 71 end Behavioral; 72


lut.vhd

-- Generated by matlab script divisionError.m 1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 4 entity lut is 5 Port ( din : in STD_LOGIC_VECTOR (7 downto 0); 6 dout : out STD_LOGIC_VECTOR (9 downto 0)); 7 end lut; 8 9 architecture Behavioral of lut is 10 11 begin 12 13 dout <= 14 "0001000100" when din = "11111111" else 15 "0001000101" when din = "11111110" else 16 "0001000110" when din = "11111101" else 17 "0001000110" when din = "11111100" else 18 "0001000111" when din = "11111011" else 19 "0001001000" when din = "11111010" else 20 "0001001001" when din = "11111001" else 21 "0001001001" when din = "11111000" else 22 "0001001010" when din = "11110111" else 23 "0001001011" when din = "11110110" else 24 "0001001100" when din = "11110101" else 25 "0001001100" when din = "11110100" else 26 "0001001101" when din = "11110011" else 27 "0001001110" when din = "11110010" else 28 "0001001111" when din = "11110001" else 29 "0001010000" when din = "11110000" else 30 "0001010001" when din = "11101111" else 31 "0001010001" when din = "11101110" else 32 "0001010010" when din = "11101101" else 33 "0001010011" when din = "11101100" else 34 "0001010100" when din = "11101011" else 35 "0001010101" when din = "11101010" else 36 "0001010110" when din = "11101001" else 37 "0001010111" when din = "11101000" else 38 "0001011000" when din = "11100111" else 39 "0001011000" when din = "11100110" else 40 "0001011001" when din = "11100101" else 41 "0001011010" when din = "11100100" else 42 "0001011011" when din = "11100011" else 43 "0001011100" when din = "11100010" else 44 "0001011101" when din = "11100001" else 45 "0001011110" when din = "11100000" else 46 "0001011111" when din = "11011111" else 47 "0001100000" when din = "11011110" else 48 "0001100001" when din = "11011101" else 49 "0001100010" when din = "11011100" else 50 "0001100011" when din = "11011011" else 51 "0001100100" when din = "11011010" else 52 "0001100101" when din = "11011001" else 53 "0001100110" when din = "11011000" else 54 "0001100111" when din = "11010111" else 55 "0001101001" when din = "11010110" else 56 "0001101010" when din = "11010101" else 57 "0001101011" when din = "11010100" else 58 "0001101100" when din = "11010011" else 59 "0001101101" when din = "11010010" else 60 "0001101110" when din = "11010001" else 61 "0001101111" when din = "11010000" else 62 "0001110000" when din = "11001111" else 63 "0001110010" when din = "11001110" else 64 "0001110011" when din = "11001101" else 65


"0001110100" when din = "11001100" else 66 "0001110101" when din = "11001011" else 67 "0001110110" when din = "11001010" else 68 "0001111000" when din = "11001001" else 69 "0001111001" when din = "11001000" else 70 "0001111010" when din = "11000111" else 71 "0001111011" when din = "11000110" else 72 "0001111101" when din = "11000101" else 73 "0001111110" when din = "11000100" else 74 "0001111111" when din = "11000011" else 75 "0010000001" when din = "11000010" else 76 "0010000010" when din = "11000001" else 77 "0010000011" when din = "11000000" else 78 "0010000101" when din = "10111111" else 79 "0010000110" when din = "10111110" else 80 "0010001000" when din = "10111101" else 81 "0010001001" when din = "10111100" else 82 "0010001010" when din = "10111011" else 83 "0010001100" when din = "10111010" else 84 "0010001101" when din = "10111001" else 85 "0010001111" when din = "10111000" else 86 "0010010000" when din = "10110111" else 87 "0010010010" when din = "10110110" else 88 "0010010011" when din = "10110101" else 89 "0010010101" when din = "10110100" else 90 "0010010110" when din = "10110011" else 91 "0010011000" when din = "10110010" else 92 "0010011010" when din = "10110001" else 93 "0010011011" when din = "10110000" else 94 "0010011101" when din = "10101111" else 95 "0010011110" when din = "10101110" else 96 "0010100000" when din = "10101101" else 97 "0010100010" when din = "10101100" else 98 "0010100011" when din = "10101011" else 99 "0010100101" when din = "10101010" else 100 "0010100111" when din = "10101001" else 101 "0010101001" when din = "10101000" else 102 "0010101010" when din = "10100111" else 103 "0010101100" when din = "10100110" else 104 "0010101110" when din = "10100101" else 105 "0010110000" when din = "10100100" else 106 "0010110010" when din = "10100011" else 107 "0010110011" when din = "10100010" else 108 "0010110101" when din = "10100001" else 109 "0010110111" when din = "10100000" else 110 "0010111001" when din = "10011111" else 111 "0010111011" when din = "10011110" else 112 "0010111101" when din = "10011101" else 113 "0010111111" when din = "10011100" else 114 "0011000001" when din = "10011011" else 115 "0011000011" when din = "10011010" else 116 "0011000101" when din = "10011001" else 117 "0011000111" when din = "10011000" else 118 "0011001001" when din = "10010111" else 119 "0011001011" when din = "10010110" else 120 "0011001101" when din = "10010101" else 121 "0011010000" when din = "10010100" else 122 "0011010010" when din = "10010011" else 123 "0011010100" when din = "10010010" else 124 "0011010110" when din = "10010001" else 125 "0011011000" when din = "10010000" else 126 "0011011011" when din = "10001111" else 127 "0011011101" when din = "10001110" else 128 "0011011111" when din = "10001101" else 129 "0011100010" when din = "10001100" else 130 "0011100100" when din = "10001011" else 131 "0011100110" when din = "10001010" else 132 "0011101001" when din = "10001001" else 133 "0011101011" when din = "10001000" else 134


"0011101110" when din = "10000111" else 135 "0011110000" when din = "10000110" else 136 "0011110011" when din = "10000101" else 137 "0011110101" when din = "10000100" else 138 "0011111000" when din = "10000011" else 139 "0011111010" when din = "10000010" else 140 "0011111101" when din = "10000001" else 141 "0100000000" when din = "10000000" else 142 143 "0100000000" when din = "01111111" else 144 "0100000010" when din = "01111110" else 145 "0100000101" when din = "01111101" else 146 "0100001000" when din = "01111100" else 147 "0100001010" when din = "01111011" else 148 "0100001101" when din = "01111010" else 149 "0100010000" when din = "01111001" else 150 "0100010011" when din = "01111000" else 151 "0100010110" when din = "01110111" else 152 "0100011001" when din = "01110110" else 153 "0100011011" when din = "01110101" else 154 "0100011110" when din = "01110100" else 155 "0100100001" when din = "01110011" else 156 "0100100100" when din = "01110010" else 157 "0100100111" when din = "01110001" else 158 "0100101011" when din = "01110000" else 159 "0100101110" when din = "01101111" else 160 "0100110001" when din = "01101110" else 161 "0100110100" when din = "01101101" else 162 "0100110111" when din = "01101100" else 163 "0100111010" when din = "01101011" else 164 "0100111110" when din = "01101010" else 165 "0101000001" when din = "01101001" else 166 "0101000100" when din = "01101000" else 167 "0101001000" when din = "01100111" else 168 "0101001011" when din = "01100110" else 169 "0101001111" when din = "01100101" else 170 "0101010010" when din = "01100100" else 171 "0101010110" when din = "01100011" else 172 "0101011001" when din = "01100010" else 173 "0101011101" when din = "01100001" else 174 "0101100000" when din = "01100000" else 175 "0101100100" when din = "01011111" else 176 "0101101000" when din = "01011110" else 177 "0101101100" when din = "01011101" else 178 "0101101111" when din = "01011100" else 179 "0101110011" when din = "01011011" else 180 "0101110111" when din = "01011010" else 181 "0101111011" when din = "01011001" else 182 "0101111111" when din = "01011000" else 183 "0110000011" when din = "01010111" else 184 "0110000111" when din = "01010110" else 185 "0110001011" when din = "01010101" else 186 "0110001111" when din = "01010100" else 187 "0110010011" when din = "01010011" else 188 "0110011000" when din = "01010010" else 189 "0110011100" when din = "01010001" else 190 "0110100000" when din = "01010000" else 191 "0110100100" when din = "01001111" else 192 "0110101001" when din = "01001110" else 193 "0110101101" when din = "01001101" else 194 "0110110010" when din = "01001100" else 195 "0110110110" when din = "01001011" else 196 "0110111011" when din = "01001010" else 197 "0110111111" when din = "01001001" else 198 "0111000100" when din = "01001000" else 199 "0111001001" when din = "01000111" else 200 "0111001110" when din = "01000110" else 201 "0111010010" when din = "01000101" else 202 "0111010111" when din = "01000100" else 203


"0111011100" when din = "01000011" else 204 "0111100001" when din = "01000010" else 205 "0111100110" when din = "01000001" else 206 "0111101011" when din = "01000000" else 207 "0111110000" when din = "00111111" else 208 "0111110110" when din = "00111110" else 209 "0111111011" when din = "00111101" else 210 "1000000000" when din = "00111100" else 211 "1000000101" when din = "00111011" else 212 "1000001011" when din = "00111010" else 213 "1000010000" when din = "00111001" else 214 "1000010110" when din = "00111000" else 215 "1000011011" when din = "00110111" else 216 "1000100001" when din = "00110110" else 217 "1000100111" when din = "00110101" else 218 "1000101100" when din = "00110100" else 219 "1000110010" when din = "00110011" else 220 "1000111000" when din = "00110010" else 221 "1000111110" when din = "00110001" else 222 "1001000100" when din = "00110000" else 223 "1001001010" when din = "00101111" else 224 "1001010000" when din = "00101110" else 225 "1001010110" when din = "00101101" else 226 "1001011100" when din = "00101100" else 227 "1001100011" when din = "00101011" else 228 "1001101001" when din = "00101010" else 229 "1001110000" when din = "00101001" else 230 "1001110110" when din = "00101000" else 231 "1001111101" when din = "00100111" else 232 "1010000011" when din = "00100110" else 233 "1010001010" when din = "00100101" else 234 "1010010001" when din = "00100100" else 235 "1010011000" when din = "00100011" else 236 "1010011111" when din = "00100010" else 237 "1010100110" when din = "00100001" else 238 "1010101101" when din = "00100000" else 239 "1010110100" when din = "00011111" else 240 "1010111011" when din = "00011110" else 241 "1011000010" when din = "00011101" else 242 "1011001010" when din = "00011100" else 243 "1011010001" when din = "00011011" else 244 "1011011001" when din = "00011010" else 245 "1011100000" when din = "00011001" else 246 "1011101000" when din = "00011000" else 247 "1011110000" when din = "00010111" else 248 "1011110111" when din = "00010110" else 249 "1011111111" when din = "00010101" else 250 "1100000111" when din = "00010100" else 251 "1100001111" when din = "00010011" else 252 "1100011000" when din = "00010010" else 253 "1100100000" when din = "00010001" else 254 "1100101000" when din = "00010000" else 255 "1100110001" when din = "00001111" else 256 "1100111001" when din = "00001110" else 257 "1101000010" when din = "00001101" else 258 "1101001010" when din = "00001100" else 259 "1101010011" when din = "00001011" else 260 "1101011100" when din = "00001010" else 261 "1101100101" when din = "00001001" else 262 "1101101110" when din = "00001000" else 263 "1101110111" when din = "00000111" else 264 "1110000000" when din = "00000110" else 265 "1110001010" when din = "00000101" else 266 "1110010011" when din = "00000100" else 267 "1110011101" when din = "00000011" else 268 "1110100110" when din = "00000010" else 269 "1110110000" when din = "00000001" else 270 "1110111010" when din = "00000000" else 271 "0100000000"; 272


273 end Behavioral; 274


summer9x2ch.vhd

------------------------------------------------------------------------------- 1 -- summer9x2ch.vhd ------------------------------------------------------------ 2 -- Author: Anthony Giardina -- 3 -- For: Graphic Audio EQ Senior Project -- 4 -- Last Modified: 5/29/2012 -- 5 -- Purpose: This module takes in 18 twos compliment signals (9 per channel) -- 6 -- and generates two sums (one per channel). -- 7 ------------------------------------------------------------------------------- 8 ------------------------------------------------------------------------------- 9 library IEEE; 10 use IEEE.STD_LOGIC_1164.ALL; 11 12 entity summer9x2ch is 13 Port ( clock : in STD_LOGIC; 14 in1_r : in STD_LOGIC_VECTOR (17 downto 0); 15 in1_l : in STD_LOGIC_VECTOR (17 downto 0); 16 in2_r : in STD_LOGIC_VECTOR (17 downto 0); 17 in2_l : in STD_LOGIC_VECTOR (17 downto 0); 18 in3_r : in STD_LOGIC_VECTOR (17 downto 0); 19 in3_l : in STD_LOGIC_VECTOR (17 downto 0); 20 in4_r : in STD_LOGIC_VECTOR (17 downto 0); 21 in4_l : in STD_LOGIC_VECTOR (17 downto 0); 22 in5_r : in STD_LOGIC_VECTOR (17 downto 0); 23 in5_l : in STD_LOGIC_VECTOR (17 downto 0); 24 in6_r : in STD_LOGIC_VECTOR (17 downto 0); 25 in6_l : in STD_LOGIC_VECTOR (17 downto 0); 26 in7_r : in STD_LOGIC_VECTOR (17 downto 0); 27 in7_l : in STD_LOGIC_VECTOR (17 downto 0); 28 in8_r : in STD_LOGIC_VECTOR (17 downto 0); 29 in8_l : in STD_LOGIC_VECTOR (17 downto 0); 30 in9_r : in STD_LOGIC_VECTOR (17 downto 0); 31 in9_l : in STD_LOGIC_VECTOR (17 downto 0); 32 out_r : out STD_LOGIC_VECTOR (17 downto 0); 33 out_l : out STD_LOGIC_VECTOR (17 downto 0)); 34 end summer9x2ch; 35 36 architecture Behavioral of summer9x2ch is 37 38 -- Intermediate signals used to connect everything: 39 signal s10_r : std_logic_vector(17 downto 0); 40 signal s11_r : std_logic_vector(17 downto 0); 41 signal s12_r : std_logic_vector(17 downto 0); 42 signal s13_r : std_logic_vector(17 downto 0); 43 signal s14_r : std_logic_vector(17 downto 0); 44 signal s15_r : std_logic_vector(17 downto 0); 45 signal s16_r : std_logic_vector(17 downto 0); 46 47 signal s10_l : std_logic_vector(17 downto 0); 48 signal s11_l : std_logic_vector(17 downto 0); 49 signal s12_l : std_logic_vector(17 downto 0); 50 signal s13_l : std_logic_vector(17 downto 0); 51 signal s14_l : std_logic_vector(17 downto 0); 52 signal s15_l : std_logic_vector(17 downto 0); 53 signal s16_l : std_logic_vector(17 downto 0); 54 55 COMPONENT adder 56 PORT ( 57 a : IN STD_LOGIC_VECTOR(17 DOWNTO 0); 58 b : IN STD_LOGIC_VECTOR(17 DOWNTO 0); 59 clk : IN STD_LOGIC; 60 s : OUT STD_LOGIC_VECTOR(17 DOWNTO 0) 61 ); 62 END COMPONENT; 63 64


signal r : std_logic_vector (17 downto 0); 65 signal l : std_logic_vector (17 downto 0); 66 67 68 begin 69 70 -- Outputs are right shifted by 3: 71 out_r <= r(17) & r(13) & r(12) & r(11) & r(10) & r(9) & r(8) & r(7) & 72 r(6) & r(5) & r(4) & r(3) & r(2) & r(1) & r(0) & r(0) & r(0) & 73 r(0); 74 out_l <= l(17) & l(13) & l(12) & l(11) & l(10) & l(9) & l(8) & l(7) & 75 l(6) & l(5) & l(4) & l(3) & l(2) & l(1) & l(0) & l(0) & l(0) & 76 l(0); 77 78 -- This giant pile of 2-input adders sum all of the input signals together: 79 s1_l : adder 80 PORT MAP ( 81 a => in1_l, 82 b => in2_l, 83 clk => clock, 84 s => s10_l 85 ); 86 87 s1_r : adder 88 PORT MAP ( 89 a => in1_r, 90 b => in2_r, 91 clk => clock, 92 s => s10_r 93 ); 94 -- 95 s2_l : adder 96 PORT MAP ( 97 a => in3_l, 98 b => in4_l, 99 clk => clock, 100 s => s11_l 101 ); 102 103 s2_r : adder 104 PORT MAP ( 105 a => in3_r, 106 b => in4_r, 107 clk => clock, 108 s => s11_r 109 ); 110 -- 111 s3_l : adder 112 PORT MAP ( 113 a => in5_l, 114 b => in6_l, 115 clk => clock, 116 s => s12_l 117 ); 118 119 s3_r : adder 120 PORT MAP ( 121 a => in5_r, 122 b => in6_r, 123 clk => clock, 124 s => s12_r 125 ); 126 -- 127 s4_l : adder 128 PORT MAP ( 129 a => in7_l, 130 b => in8_l, 131 clk => clock, 132 s => s13_l 133


); 134 135 s4_r : adder 136 PORT MAP ( 137 a => in7_r, 138 b => in8_r, 139 clk => clock, 140 s => s13_r 141 ); 142 -- 143 s5_l : adder 144 PORT MAP ( 145 a => s10_l, 146 b => s11_l, 147 clk => clock, 148 s => s14_l 149 ); 150 151 s5_r : adder 152 PORT MAP ( 153 a => s10_r, 154 b => s11_r, 155 clk => clock, 156 s => s14_r 157 ); 158 -- 159 s6_l : adder 160 PORT MAP ( 161 a => s12_l, 162 b => s13_l, 163 clk => clock, 164 s => s15_l 165 ); 166 167 s6_r : adder 168 PORT MAP ( 169 a => s12_r, 170 b => s13_r, 171 clk => clock, 172 s => s15_r 173 ); 174 -- 175 s7_l : adder 176 PORT MAP ( 177 a => s14_l, 178 b => s15_l, 179 clk => clock, 180 s => s16_l 181 ); 182 183 s7_r : adder 184 PORT MAP ( 185 a => s14_r, 186 b => s15_r, 187 clk => clock, 188 s => s16_r 189 ); 190 -- 191 s8_l : adder 192 PORT MAP ( 193 a => s16_l, 194 b => in9_l, 195 clk => clock, 196 s => l 197 ); 198 199 s8_r : adder 200 PORT MAP ( 201 a => s16_r, 202


b => in9_r, 203 clk => clock, 204 s => r 205 ); 206 207 end Behavioral; 208


ledLut.vhd

------------------------------------------------------------------------------- 1 -- ledLut.vhd ----------------------------------------------------------------- 2 -- Author: Anthony Giardina -- 3 -- For: Graphic Audio EQ Senior Project -- 4 -- Last Modified: 5/29/2012 -- 5 -- Purpose: This module converts 18-bit twos-compliment values and converts -- 6 -- them to values which can be displayed on the LED banks, representing -- 7 -- the amplitude of the input value. -- 8 ------------------------------------------------------------------------------- 9 ------------------------------------------------------------------------------- 10 library IEEE; 11 use IEEE.STD_LOGIC_1164.ALL; 12 use Ieee.std_logic_unsigned.all; 13 use IEEE.NUMERIC_STD.ALL; 14 15 entity ledLut is 16 Port ( bandPcm : in STD_LOGIC_VECTOR (17 downto 0); 17 ledOut : out STD_LOGIC_VECTOR (7 downto 0)); 18 end ledLut; 19 20 architecture Behavioral of ledLut is 21 22 -- Sign bit of input twos-compliment number: 23 signal s : std_logic; 24 -- the rest of the bits, without the sign bit: 25 signal d : std_logic_vector (16 downto 0); 26 27 begin 28 -- Sign bit of twos compliment PCM value 29 s <= bandPcm (17); 30 -- left shift by 2 to get some additional range on the LEDs 31 d <= bandPcm(14) & bandPcm(13) & bandPcm(12) & bandPcm(11) & bandPcm(10) & 32 bandPcm(9) & bandPcm(8) & bandPcm(7) & bandPcm(6) & bandPcm(5) & 33 bandPcm(4) & bandPcm(3) & bandPcm(2) & bandPcm(1) & bandPcm(0) & 34 bandPcm(0) & bandPcm(0); 35 36 -- This is a lookup table. The values were more or less experimentally 37 -- determined for best appearance on the display: 38 ledOut <= "00000000" when ((s = '1') and ( d <= "00000000000000011")) 39 or ((s = '0') and ( d >= "10000000000000000")) 40 else 41 "00000001" when ((s = '1') and ( d <= "00000000000000011")) 42 or ((s = '0') and ((d < "10000000000000000") 43 and (d >= "00100000000000000"))) 44 else 45 "00000011" when ((s = '1') and ((d > "00000000000000011") 46 and (d <= "00000000000011111"))) or ((s = '0') 47 and ((d < "00100000000000000") 48 and (d >= "00001000000000000"))) 49 else 50 "00000111" when ((s = '1') and ((d > "00000000000011111") 51 and (d <= "00000000001111111"))) or ((s = '0') 52 and ((d < "00001000000000000") 53 and (d >= "00000010000000000"))) 54 else 55 "00001111" when ((s = '1') and ((d > "00000000001111111") 56 and (d <= "00000001111111111"))) or ((s = '0') 57 and ((d < "00000010000000000") 58 and (d >= "00000000100000000"))) 59 else 60 "00011111" when ((s = '1') and ((d > "00000001111111111") 61 and (d <= "00000111111111111"))) or ((s = '0') 62 and ((d < "00000000100000000") 63 and (d >= "00000000001000000"))) 64 else 65 "00111111" when ((s = '1') and ((d > "00000111111111111") 66 and (d <= "00011111111111111"))) or ((s = '0') 67 and ((d < "00000000001000000") 68


and (d >= "00000000000010000"))) 69 else 70 "01111111" when ((s = '1') and ((d > "00011111111111111") 71 and (d <= "01111111111111111"))) or ((s = '0') 72 and ((d < "00000000000010000") 73 and (d >= "00000000000000100"))) else 74 "11111111" when ((s = '1') and ( d > "01111111111111111")) 75 or ((s = '0') and ( d < "00000000000000100")) 76 else 77 "01010101"; -- obviously invalid display output, for debugging 78 79 end Behavioral; 80


AtlysGeneral.ucf

# AtlysGeneral.ucf 1 # Adapted from the AtlysGeneral.ucf file, available 2 # from the Digilent website 3 PIN "masterClock/clkout3_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; 4 PIN "masterClock/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; 5 # clock pin for Atlys rev C board 6 NET "sysClk" LOC = "L15"; 7 8 # onBoard Leds 9 NET "led<0>" LOC = "U18"; 10 NET "led<1>" LOC = "M14"; 11 NET "led<2>" LOC = "N14"; 12 NET "led<3>" LOC = "L14"; 13 NET "led<4>" LOC = "M13"; 14 NET "led<5>" LOC = "D4"; 15 NET "led<6>" LOC = "P16"; 16 NET "led<7>" LOC = "N12"; 17 18 # onBoard SWITCHES 19 NET "sysReset" LOC = "A10"; 20 NET "mode" LOC = "D14"; 21 NET "interfaceLoopback" LOC = "C14"; 22 23 24 # Audio 25 NET "BITCLK" LOC = "L13"; 26 NET "AUDSDI" LOC = "T18"; 27 NET "AUDSDO" LOC = "N16"; 28 NET "AUDSYNC" LOC = "U17"; 29 NET "AUDRST" LOC = "T17"; 30 31 # PMOD Connector 32 NET "JB<0>" LOC = "T3"; 33 NET "JB<1>" LOC = "R3"; 34 NET "JB<2>" LOC = "P6"; 35 NET "JB<3>" LOC = "N5"; 36 NET "JB<4>" LOC = "V9"; 37 NET "JB<5>" LOC = "T9"; 38 NET "JB<6>" LOC = "V4"; 39 NET "JB<7>" LOC = "T4"; 40 41 # onboard VHDCI 42 NET "LED_SIN" LOC = "U15"; 43 NET "LED_BLANK" LOC = "M11"; 44 NET "LED_LAT<1>" LOC = "T12"; 45 NET "LED_LAT<3>" LOC = "R8"; 46 NET "ADC_CS_C" LOC = "U8"; 47 NET "ADC_IOCLK" LOC = "N7"; 48 NET "ADC_DATA_OUT" LOC = "R7"; 49 NET "LED_SCLK" LOC = "V15"; 50 NET "LED_LAT<0>" LOC = "N11"; 51 NET "LED_LAT<2>" LOC = "T10"; 52 NET "LED_LAT<4>" LOC = "T8"; 53 NET "ADC_ADDR_INPUT" LOC = "V8"; 54 NET "ADC_SYSCLK" LOC = "P8"; 55


Appendix B: Matlab Source Code divisionError.m

% divisionError.m 1 % This Matlab script creates the lookup table lut.vhd. The purpose of 2 % the lookup table is described in the report. The script also outputs 3 % figures which show the transfer function of the lookup table, and 4 % the error associated with the scaled integer arithmitic that it 5 % preforms. 6 7 clear 8 9 mindbStep = 0.09; 10 11 adjDB = zeros(1,128); 12 13 shiftFactor = 256; 14 15 for p=1:length(adjDB) 16 adjDB(p) = (p-1) * mindbStep; 17 end 18 19 adjLIN = zeros(size(adjDB)); 20 21 for p=1: length(adjDB) 22 adjLIN(p) = 10^(adjDB(p)/20); 23 end 24 25 adjLinScaled = fix (adjLIN.* shiftFactor); 26 27 pcmCodes = linspace(0,2^17-1,2^17); 28 29 resultScaledUp = zeros(length(adjDB),length(pcmCodes)); 30 31 for p=1:length(adjLIN) 32 for q=1:length(pcmCodes) 33 resultScaledUp(p,q) = adjLinScaled(p) * pcmCodes(q); 34 end 35 end 36 37 resultIdeal = zeros(length(adjDB),length(pcmCodes)); 38 39 for p=1:length(adjLIN) 40 for q=1:length(pcmCodes) 41 resultIdeal(p,q) = adjLIN(p) * pcmCodes(q); 42 end 43 end 44 45 resultScaledDown = fix(resultScaledUp / shiftFactor); 46 47 error = zeros(length(adjDB),length(pcmCodes)); 48 49 for p=1:length(adjLIN) 50 for q=1:length(pcmCodes) 51 error(p,q) = ((resultIdeal(p,q) - resultScaledDown(p,q))/ ... 52 resultIdeal(p,q))*100; 53 end 54 end 55 56 %Warning: This will bring your computer to it's knees, but looks good. 57 % figure(3) 58 % mesh(pcmCodes,adjLIN,error); 59 % title ('Error for scaled integer multiplication/division'); 60 % xlabel('Input PCM code') 61 % ylabel('lut output value') 62 % zlabel('Percent Error') 63 64


maxError = max(error,[],1); 65 66 adjLINDiv = 1./adjLIN; 67 adjLinDivScaled = fix ( adjLINDiv .* shiftFactor); 68 resultScaledUpDiv = zeros(length(adjDB),length(pcmCodes)); 69 70 for p=1:length(adjLINDiv) 71 for q=1:length(pcmCodes) 72 resultScaledUpDiv(p,q) = adjLinDivScaled(p) * pcmCodes(q); 73 end 74 end 75 76 resultIdealDiv = zeros(length(adjDB),length(pcmCodes)); 77 for p=1:length(adjLIN) 78 for q=1:length(pcmCodes) 79 resultIdealDiv(p,q) = adjLINDiv(p) * pcmCodes(q); 80 end 81 end 82 83 resultScaledDownDiv = fix(resultScaledUpDiv / shiftFactor); 84 85 errorDiv = zeros(length(adjDB),length(pcmCodes)); 86 87 for p=1:length(adjLIN) 88 for q=1:length(pcmCodes) 89 errorDiv(p,q) = ((resultIdealDiv(p,q) - ... 90 resultScaledDownDiv(p,q))/resultIdealDiv(p,q))*100; 91 end 92 end 93 94 maxErrorDiv = max(errorDiv,[],1); 95 96 figure (2) 97 grid on 98 plot(linspace(128,255,128),adjLinScaled,'-r','LineWidth',2); 99 hold on 100 plot(linspace(0,127,128),fliplr(adjLinDivScaled),'-g','LineWidth',2); 101 grid on 102 legend('Multiplication','Division'); 103 title('Transfer Function of lookup table'); 104 xlabel('Input') 105 ylabel('Output') 106 107 figure(11) 108 109 semilogx (linspace(0,length(maxErrorDiv)-1,length(maxErrorDiv)), ... 110 maxErrorDiv,'-g','LineWidth',2); 111 hold on 112 semilogx (linspace(0,length(maxError)-1,length(maxError)),maxError, ... 113 '-r','LineWidth',2); 114 legend('Division Error','Multiplication Error'); 115 grid on 116 title('Maximum error for scaled integer multiplication/division'); 117 xlabel('Input PCM code') 118 ylabel('Percent Error') 119 120 FILE = fopen('lut.vhd','w') 121 fprintf(FILE, '-- Generated by matlab script divisionError.m \n'); 122 fprintf(FILE, 'library IEEE;\n'); 123 fprintf(FILE, 'use IEEE.STD_LOGIC_1164.ALL;\n'); 124 fprintf(FILE, ' \n'); 125 fprintf(FILE, 'entity lut is\n'); 126 fprintf(FILE, ' Port ( din : in STD_LOGIC_VECTOR (7 downto 0);\n'); 127 fprintf(FILE, ' dout : out STD_LOGIC_VECTOR (9 downto 0));\n'); 128 fprintf(FILE, 'end lut;\n'); 129 fprintf(FILE, ' \n'); 130 fprintf(FILE, 'architecture Behavioral of lut is\n'); 131 fprintf(FILE, ' \n'); 132 fprintf(FILE, 'begin\n'); 133


fprintf(FILE, ' \n'); 134 fprintf(FILE, 'dout <= \n'); 135 for p = 1:128 136 fprintf(FILE,'\t\t"'); 137 fprintf(FILE,dec2bin(adjLinDivScaled(129-p),10)); 138 fprintf(FILE,'" when din = "'); 139 fprintf(FILE,dec2bin(256-p,8)); 140 fprintf(FILE,'" else \n'); 141 end 142 143 fprintf(FILE, ' \n'); 144 145 for p = 1:128 146 fprintf(FILE,'\t\t"'); 147 fprintf(FILE,dec2bin(adjLinScaled(p),10)); 148 fprintf(FILE,'" when din = "'); 149 fprintf(FILE,dec2bin(128-p,8)); 150 fprintf(FILE,'" else \n'); 151 end 152 153 fprintf(FILE,'\t\t"'); 154 fprintf(FILE,dec2bin(adjLinScaled(1),10)); 155 fprintf(FILE,'";\n'); 156 157 fprintf(FILE, ' \n'); 158 fprintf(FILE, 'end Behavioral;\n'); 159 fclose(FILE); 160


filterPlotter.m

% filterPlotter.m 1 % This script plots the magnitude response of 9 paralell FIR filters, 2 % which are stored in the file filterCoe.mat. Plots 1-9 are the 3 % individual filter responses, and plot 10 is the combined 4 % system response. 5 6 clear 7 % Load filters from file where they are stored: 8 load filterCoe.mat 9 10 p = 2^15; 11 12 % Preform a padded FFT on all of the time-domain filters. 13 f1_spect = fft(f1,p); 14 f2_spect = fft(f2,p); 15 f3_spect = fft(f3,p); 16 f4_spect = fft(f4,p); 17 f5_spect = fft(f5,p); 18 f6_spect = fft(f6,p); 19 f7_spect = fft(f7,p); 20 f8_spect = fft(f8,p); 21 f9_spect = fft(f9,p); 22 23 % x axis, frequency in Hz 24 x = linspace(0,48000,p); 25 26 figure(1) 27 28 % plot all of the filter responses 29 semilogx(x,20*log10(abs(f1_spect)),'g--','LineWidth',2); 30 hold on 31 semilogx(x,20*log10(abs(f2_spect)),'b--','LineWidth',2); 32 semilogx(x,20*log10(abs(f3_spect)),'k-','LineWidth',2); 33 semilogx(x,20*log10(abs(f4_spect)),'y-','LineWidth',2); 34 semilogx(x,20*log10(abs(f5_spect)),'m-','LineWidth',2); 35 semilogx(x,20*log10(abs(f6_spect)),'c-','LineWidth',2); 36 semilogx(x,20*log10(abs(f7_spect)),'r--','LineWidth',2); 37 semilogx(x,20*log10(abs(f8_spect)),'g-','LineWidth',2); 38 semilogx(x,20*log10(abs(f9_spect)),'b-','LineWidth',2); 39 40 % sum up all of the responses 41 sum = zeros(1,p); 42 for q = 1:p 43 sum(q) = abs(f1_spect(q)) + ... 44 abs(f2_spect(q)) + ... 45 abs(f3_spect(q)) + ... 46 abs(f4_spect(q)) + ... 47 abs(f5_spect(q)) + ... 48 abs(f6_spect(q)) + ... 49 abs(f7_spect(q)) + ... 50 abs(f8_spect(q)) + ... 51 abs(f9_spect(q)); 52 end 53 semilogx(x,20*log10(sum),'r-','LineWidth',2); 54 55 % trim the axis so that nothing above nyquist frequency is displayed: 56 axis([0 24000 -50 10]) 57 58 % labels and such: 59 grid on 60 title('FIR Filter responses') 61 xlabel('Analog Frequency, Hz') 62 ylabel('Magnitude (dB)') 63 legend ('f1','f2','f3','f4','f5','f6','f7','f8','f9', ... 64 'Total System Response'); 65


Appendix C: FIR Filter Coefficients f1_450pt.coe

; 1 ; XILINX CORE 2 Generator(tm)Distributed 3 Arithmetic FIR filter 4 coefficient (.COE) File 5 ; Generated by MATLAB(R) 6 7.10 and the Filter 7 Design Toolbox 4.7. 8 ; 9 ; Generated on: 04-Apr-10 2012 10:55:57 11 ; 12 Radix = 16; 13 Coefficient_Width = 16; 14 CoefData = ace1, 15 03e6, 16 03d0, 17 03ba, 18 03a6, 19 0391, 20 037f, 21 036b, 22 035b, 23 0349, 24 033a, 25 032a, 26 031c, 27 030d, 28 0300, 29 02f3, 30 02e7, 31 02db, 32 02d1, 33 02c5, 34 02bc, 35 02b1, 36 02a9, 37 029f, 38 0298, 39 028f, 40 0289, 41 0281, 42 027c, 43 0274, 44 0270, 45 0269, 46 0265, 47 025f, 48 025c, 49 0256, 50 0255, 51 024e, 52 024f, 53 0245, 54 0245, 55 0257, 56 0239, 57 023a, 58 0238, 59 023c, 60 023c, 61 023e, 62 023d, 63

023c, 64 023a, 65 0239, 66 0237, 67 0237, 68 0236, 69 0236, 70 0236, 71 0237, 72 0238, 73 0239, 74 023b, 75 023d, 76 023f, 77 0240, 78 0243, 79 0244, 80 0247, 81 0248, 82 024a, 83 024c, 84 024e, 85 024f, 86 0252, 87 0253, 88 0256, 89 0258, 90 025b, 91 025d, 92 0261, 93 0261, 94 0267, 95 0268, 96 0267, 97 0271, 98 0273, 99 0276, 100 0278, 101 027b, 102 027e, 103 0282, 104 0286, 105 028b, 106 028e, 107 0292, 108 0295, 109 0298, 110 029c, 111 029f, 112 02a2, 113 02a6, 114 02a9, 115 02ad, 116 02b1, 117 02b4, 118 02b8, 119 02bb, 120 02bf, 121 02c3, 122 02c6, 123 02ca, 124 02cd, 125 02d0, 126

02d4, 127 02d7, 128 02dc, 129 02df, 130 02e3, 131 02e6, 132 02eb, 133 02ee, 134 02f3, 135 02f5, 136 02fa, 137 02ff, 138 0301, 139 0304, 140 0309, 141 030d, 142 0311, 143 0314, 144 0317, 145 031b, 146 031e, 147 0322, 148 0325, 149 0329, 150 032d, 151 0330, 152 0333, 153 0336, 154 033a, 155 033d, 156 0340, 157 0344, 158 0347, 159 034a, 160 034e, 161 0351, 162 0354, 163 0357, 164 035a, 165 035d, 166 0360, 167 0363, 168 0366, 169 0369, 170 036c, 171 036e, 172 0372, 173 0374, 174 0377, 175 0379, 176 037d, 177 037f, 178 0382, 179 0385, 180 0388, 181 038a, 182 038c, 183 038f, 184 0391, 185 0394, 186 0397, 187 0399, 188 039b, 189


039d, 190 03a0, 191 03a2, 192 03a5, 193 03a7, 194 03aa, 195 03ac, 196 03ae, 197 03b0, 198 03b2, 199 03b3, 200 03b5, 201 03b7, 202 03b9, 203 03ba, 204 03bc, 205 03bd, 206 03bf, 207 03c0, 208 03c2, 209 03c3, 210 03c5, 211 03c6, 212 03c7, 213 03c8, 214 03c9, 215 03ca, 216 03cc, 217 03cc, 218 03ce, 219 03ce, 220 03d0, 221 03d0, 222 03d1, 223 03d2, 224 03d3, 225 03d3, 226 03d4, 227 03d4, 228 03d4, 229 03d5, 230 03d5, 231 03d6, 232 03d6, 233 03d6, 234 03d6, 235 03d6, 236 03d7, 237 03d7, 238 03d7, 239 03d7, 240 03d7, 241 03d7, 242 03d7, 243 03d6, 244 03d6, 245 03d6, 246 03d6, 247 03d6, 248 03d5, 249 03d5, 250 03d4, 251 03d4, 252 03d4, 253 03d3, 254 03d3, 255 03d2, 256 03d1, 257 03d0, 258

03d0, 259 03ce, 260 03ce, 261 03cc, 262 03cc, 263 03ca, 264 03c9, 265 03c8, 266 03c7, 267 03c6, 268 03c5, 269 03c3, 270 03c2, 271 03c0, 272 03bf, 273 03bd, 274 03bc, 275 03ba, 276 03b9, 277 03b7, 278 03b5, 279 03b3, 280 03b2, 281 03b0, 282 03ae, 283 03ac, 284 03aa, 285 03a7, 286 03a5, 287 03a2, 288 03a0, 289 039d, 290 039b, 291 0399, 292 0397, 293 0394, 294 0391, 295 038f, 296 038c, 297 038a, 298 0388, 299 0385, 300 0382, 301 037f, 302 037d, 303 0379, 304 0377, 305 0374, 306 0372, 307 036e, 308 036c, 309 0369, 310 0366, 311 0363, 312 0360, 313 035d, 314 035a, 315 0357, 316 0354, 317 0351, 318 034e, 319 034a, 320 0347, 321 0344, 322 0340, 323 033d, 324 033a, 325 0336, 326 0333, 327

0330, 328 032d, 329 0329, 330 0325, 331 0322, 332 031e, 333 031b, 334 0317, 335 0314, 336 0311, 337 030d, 338 0309, 339 0304, 340 0301, 341 02ff, 342 02fa, 343 02f5, 344 02f3, 345 02ee, 346 02eb, 347 02e6, 348 02e3, 349 02df, 350 02dc, 351 02d7, 352 02d4, 353 02d0, 354 02cd, 355 02ca, 356 02c6, 357 02c3, 358 02bf, 359 02bb, 360 02b8, 361 02b4, 362 02b1, 363 02ad, 364 02a9, 365 02a6, 366 02a2, 367 029f, 368 029c, 369 0298, 370 0295, 371 0292, 372 028e, 373 028b, 374 0286, 375 0282, 376 027e, 377 027b, 378 0278, 379 0276, 380 0273, 381 0271, 382 0267, 383 0268, 384 0267, 385 0261, 386 0261, 387 025d, 388 025b, 389 0258, 390 0256, 391 0253, 392 0252, 393 024f, 394 024e, 395 024c, 396


024a, 397 0248, 398 0247, 399 0244, 400 0243, 401 0240, 402 023f, 403 023d, 404 023b, 405 0239, 406 0238, 407 0237, 408 0236, 409 0236, 410 0236, 411 0237, 412 0237, 413 0239, 414 023a, 415 023c, 416 023d, 417 023e, 418 023c, 419

023c, 420 0238, 421 023a, 422 0239, 423 0257, 424 0245, 425 0245, 426 024f, 427 024e, 428 0255, 429 0256, 430 025c, 431 025f, 432 0265, 433 0269, 434 0270, 435 0274, 436 027c, 437 0281, 438 0289, 439 028f, 440 0298, 441 029f, 442

02a9, 443 02b1, 444 02bc, 445 02c5, 446 02d1, 447 02db, 448 02e7, 449 02f3, 450 0300, 451 030d, 452 031c, 453 032a, 454 033a, 455 0349, 456 035b, 457 036b, 458 037f, 459 0391, 460 03a6, 461 03ba, 462 03d0, 463 03e6, 464 ace1; 465


f2_460pt.coe

; 1 ; XILINX CORE 2 Generator(tm)Distribut3 ed Arithmetic FIR 4 filter coefficient 5 (.COE) File 6 ; Generated by 7 MATLAB(R) 7.10 and the 8 Filter Design Toolbox 9 4.7. 10 ; 11 ; Generated on: 04-12 Apr-2012 11:14:06 13 ; 14 Radix = 16; 15 Coefficient_Width = 16 16; 17 CoefData = 42af, 18 dcf6, 19 e4d2, 20 ead0, 21 ef61, 22 f2dc, 23 f582, 24 f787, 25 f90f, 26 fa3a, 27 fb1c, 28 fbc9, 29 fc4a, 30 fcad, 31 fcf6, 32 fd2e, 33 fd56, 34 fd75, 35 fd8b, 36 fd9c, 37 fda6, 38 fdaf, 39 fdb4, 40 fdb7, 41 fdb8, 42 fdba, 43 fdb9, 44 fdb9, 45 fdb7, 46 fdb6, 47 fdb3, 48 fdb2, 49 fdb0, 50 fdaf, 51 fdac, 52 fdab, 53 fda8, 54 fda8, 55 fda5, 56 fda5, 57 fda3, 58 fda3, 59 fda1, 60 fda1, 61 fda2, 62 fd9b, 63 fdab, 64 fd95, 65 fda3, 66 fda8, 67 fd9e, 68

fd9d, 69 fda6, 70 fdaa, 71 fda6, 72 fda3, 73 fda6, 74 fdad, 75 fdb1, 76 fdb1, 77 fdaf, 78 fdb1, 79 fdb5, 80 fdbc, 81 fdc0, 82 fdc3, 83 fdc3, 84 fdc5, 85 fdc9, 86 fdcf, 87 fdd5, 88 fddb, 89 fddf, 90 fde3, 91 fde6, 92 fdea, 93 fdf0, 94 fdf7, 95 fdfe, 96 fe05, 97 fe0b, 98 fe12, 99 fe16, 100 fe1c, 101 fe22, 102 fe2a, 103 fe31, 104 fe3a, 105 fe42, 106 fe4b, 107 fe53, 108 fe58, 109 fe63, 110 fe66, 111 fe71, 112 fe7a, 113 fe81, 114 fe8b, 115 fe97, 116 fea0, 117 fea8, 118 feb4, 119 febe, 120 fec7, 121 fece, 122 fed9, 123 fee4, 124 feef, 125 fef8, 126 ff03, 127 ff0f, 128 ff1c, 129 ff27, 130 ff32, 131 ff3c, 132 ff47, 133 ff53, 134 ff5e, 135 ff69, 136

ff74, 137 ff7f, 138 ff8c, 139 ff99, 140 ffa6, 141 ffb2, 142 ffbf, 143 ffcb, 144 ffd8, 145 ffe5, 146 fff2, 147 fffd, 148 000a, 149 0015, 150 0022, 151 002e, 152 003b, 153 0049, 154 0055, 155 0064, 156 006f, 157 007d, 158 008b, 159 0097, 160 00a6, 161 00b3, 162 00c0, 163 00cb, 164 00d9, 165 00e5, 166 00f1, 167 00fe, 168 010c, 169 0118, 170 0125, 171 0131, 172 013e, 173 014b, 174 0157, 175 0164, 176 0172, 177 017f, 178 018c, 179 0197, 180 01a4, 181 01af, 182 01bc, 183 01c7, 184 01d2, 185 01de, 186 01ea, 187 01f5, 188 0201, 189 020b, 190 0217, 191 0221, 192 022d, 193 0238, 194 0243, 195 024e, 196 0259, 197 0263, 198 026e, 199 0279, 200 0282, 201 028d, 202 0295, 203 029f, 204


02a9, 205 02b1, 206 02ba, 207 02c2, 208 02cb, 209 02d2, 210 02dc, 211 02e3, 212 02eb, 213 02f2, 214 02fa, 215 0301, 216 0309, 217 0310, 218 0318, 219 031e, 220 0325, 221 032b, 222 0331, 223 0337, 224 033c, 225 0341, 226 0347, 227 034b, 228 0350, 229 0354, 230 0359, 231 035c, 232 0360, 233 0363, 234 0367, 235 0369, 236 036c, 237 036d, 238 036f, 239 036f, 240 0372, 241 0373, 242 0375, 243 0375, 244 0376, 245 0377, 246 0377, 247 0378, 248 0377, 249 0377, 250 0376, 251 0375, 252 0375, 253 0373, 254 0372, 255 036f, 256 036f, 257 036d, 258 036c, 259 0369, 260 0367, 261 0363, 262 0360, 263 035c, 264 0359, 265 0354, 266 0350, 267 034b, 268 0347, 269 0341, 270 033c, 271 0337, 272 0331, 273

032b, 274 0325, 275 031e, 276 0318, 277 0310, 278 0309, 279 0301, 280 02fa, 281 02f2, 282 02eb, 283 02e3, 284 02dc, 285 02d2, 286 02cb, 287 02c2, 288 02ba, 289 02b1, 290 02a9, 291 029f, 292 0295, 293 028d, 294 0282, 295 0279, 296 026e, 297 0263, 298 0259, 299 024e, 300 0243, 301 0238, 302 022d, 303 0221, 304 0217, 305 020b, 306 0201, 307 01f5, 308 01ea, 309 01de, 310 01d2, 311 01c7, 312 01bc, 313 01af, 314 01a4, 315 0197, 316 018c, 317 017f, 318 0172, 319 0164, 320 0157, 321 014b, 322 013e, 323 0131, 324 0125, 325 0118, 326 010c, 327 00fe, 328 00f1, 329 00e5, 330 00d9, 331 00cb, 332 00c0, 333 00b3, 334 00a6, 335 0097, 336 008b, 337 007d, 338 006f, 339 0064, 340 0055, 341 0049, 342

003b, 343 002e, 344 0022, 345 0015, 346 000a, 347 fffd, 348 fff2, 349 ffe5, 350 ffd8, 351 ffcb, 352 ffbf, 353 ffb2, 354 ffa6, 355 ff99, 356 ff8c, 357 ff7f, 358 ff74, 359 ff69, 360 ff5e, 361 ff53, 362 ff47, 363 ff3c, 364 ff32, 365 ff27, 366 ff1c, 367 ff0f, 368 ff03, 369 fef8, 370 feef, 371 fee4, 372 fed9, 373 fece, 374 fec7, 375 febe, 376 feb4, 377 fea8, 378 fea0, 379 fe97, 380 fe8b, 381 fe81, 382 fe7a, 383 fe71, 384 fe66, 385 fe63, 386 fe58, 387 fe53, 388 fe4b, 389 fe42, 390 fe3a, 391 fe31, 392 fe2a, 393 fe22, 394 fe1c, 395 fe16, 396 fe12, 397 fe0b, 398 fe05, 399 fdfe, 400 fdf7, 401 fdf0, 402 fdea, 403 fde6, 404 fde3, 405 fddf, 406 fddb, 407 fdd5, 408 fdcf, 409 fdc9, 410 fdc5, 411


fdc3, 412 fdc3, 413 fdc0, 414 fdbc, 415 fdb5, 416 fdb1, 417 fdaf, 418 fdb1, 419 fdb1, 420 fdad, 421 fda6, 422 fda3, 423 fda6, 424 fdaa, 425 fda6, 426 fd9d, 427 fd9e, 428 fda8, 429 fda3, 430 fd95, 431 fdab, 432 fd9b, 433 fda2, 434 fda1, 435 fda1, 436 fda3, 437 fda3, 438 fda5, 439 fda5, 440 fda8, 441 fda8, 442 fdab, 443 fdac, 444 fdaf, 445 fdb0, 446 fdb2, 447 fdb3, 448 fdb6, 449 fdb7, 450 fdb9, 451 fdb9, 452 fdba, 453 fdb8, 454 fdb7, 455 fdb4, 456 fdaf, 457 fda6, 458 fd9c, 459 fd8b, 460 fd75, 461 fd56, 462 fd2e, 463 fcf6, 464 fcad, 465 fc4a, 466 fbc9, 467 fb1c, 468 fa3a, 469 f90f, 470 f787, 471 f582, 472 f2dc, 473 ef61, 474 ead0, 475 e4d2, 476 dcf6, 477 42af; 478


f3_400pt.coe

; 1 ; XILINX CORE 2 Generator(tm)Distributed 3 Arithmetic FIR filter 4 coefficient (.COE) File 5 ; Generated by MATLAB(R) 6 7.10 and the Filter 7 Design Toolbox 4.7. 8 ; 9 ; Generated on: 04-Apr-10 2012 10:35:18 11 ; 12 Radix = 16; 13 Coefficient_Width = 16; 14 CoefData = 6119, 15 ffdd, 16 ffdf, 17 ffe2, 18 ffe7, 19 ffed, 20 fff5, 21 fffd, 22 0008, 23 0012, 24 001f, 25 002c, 26 003b, 27 0049, 28 0059, 29 006a, 30 007b, 31 008c, 32 009f, 33 00b1, 34 00c4, 35 00d6, 36 00e9, 37 00fb, 38 010e, 39 0120, 40 0132, 41 0142, 42 0153, 43 0161, 44 0171, 45 017c, 46 018a, 47 0193, 48 019e, 49 01a3, 50 01ac, 51 01ac, 52 01b4, 53 01a7, 54 01c9, 55 01bd, 56 01a9, 57 01a6, 58 0197, 59 018e, 60 017c, 61 016d, 62 0157, 63 0143, 64 0128, 65 010f, 66 00ef, 67 00d0, 68

00ac, 69 0087, 70 005e, 71 0034, 72 0006, 73 ffd6, 74 ffa3, 75 ff6f, 76 ff37, 77 fefe, 78 fec2, 79 fe84, 80 fe43, 81 fe01, 82 fdbd, 83 fd77, 84 fd2f, 85 fce6, 86 fc9b, 87 fc4f, 88 fc01, 89 fbb3, 90 fb63, 91 fb12, 92 fac2, 93 fa6d, 94 fa20, 95 f9d3, 96 f97b, 97 f92b, 98 f8d7, 99 f887, 100 f834, 101 f7e6, 102 f796, 103 f749, 104 f6fb, 105 f6b1, 106 f667, 107 f620, 108 f5da, 109 f597, 110 f555, 111 f517, 112 f4da, 113 f4a1, 114 f469, 115 f437, 116 f405, 117 f3d9, 118 f3ae, 119 f389, 120 f365, 121 f347, 122 f32b, 123 f315, 124 f301, 125 f2f3, 126 f2e8, 127 f2e2, 128 f2e0, 129 f2e3, 130 f2e9, 131 f2f5, 132 f305, 133 f319, 134 f331, 135 f354, 136

f374, 137 f39d, 138 f3c7, 139 f3f9, 140 f42d, 141 f467, 142 f4a5, 143 f4e8, 144 f52f, 145 f57b, 146 f5ca, 147 f61f, 148 f677, 149 f6d4, 150 f733, 151 f798, 152 f7ff, 153 f86b, 154 f8d9, 155 f94c, 156 f9c1, 157 fa3a, 158 fab4, 159 fb33, 160 fbb3, 161 fc37, 162 fcbb, 163 fd43, 164 fdcc, 165 fe57, 166 fee3, 167 ff71, 168 ffff, 169 008f, 170 011f, 171 01b1, 172 0241, 173 02d3, 174 0362, 175 03f6, 176 0486, 177 0517, 178 05a5, 179 0633, 180 06bf, 181 074b, 182 07d3, 183 085b, 184 08e0, 185 0963, 186 09e3, 187 0a62, 188 0adc, 189 0b55, 190 0bc9, 191 0c3b, 192 0ca9, 193 0d14, 194 0d79, 195 0ddc, 196 0e3a, 197 0e95, 198 0eea, 199 0f3b, 200 0f87, 201 0fcf, 202 1011, 203 1050, 204


1088, 205 10bc, 206 10ea, 207 1114, 208 1137, 209 1156, 210 116e, 211 1182, 212 118f, 213 1198, 214 1198, 215 1198, 216 118f, 217 1182, 218 116e, 219 1156, 220 1137, 221 1114, 222 10ea, 223 10bc, 224 1088, 225 1050, 226 1011, 227 0fcf, 228 0f87, 229 0f3b, 230 0eea, 231 0e95, 232 0e3a, 233 0ddc, 234 0d79, 235 0d14, 236 0ca9, 237 0c3b, 238 0bc9, 239 0b55, 240 0adc, 241 0a62, 242 09e3, 243 0963, 244 08e0, 245 085b, 246 07d3, 247 074b, 248 06bf, 249 0633, 250 05a5, 251 0517, 252 0486, 253 03f6, 254 0362, 255 02d3, 256 0241, 257 01b1, 258 011f, 259 008f, 260 ffff, 261 ff71, 262 fee3, 263 fe57, 264 fdcc, 265 fd43, 266 fcbb, 267 fc37, 268 fbb3, 269 fb33, 270 fab4, 271 fa3a, 272 f9c1, 273

f94c, 274 f8d9, 275 f86b, 276 f7ff, 277 f798, 278 f733, 279 f6d4, 280 f677, 281 f61f, 282 f5ca, 283 f57b, 284 f52f, 285 f4e8, 286 f4a5, 287 f467, 288 f42d, 289 f3f9, 290 f3c7, 291 f39d, 292 f374, 293 f354, 294 f331, 295 f319, 296 f305, 297 f2f5, 298 f2e9, 299 f2e3, 300 f2e0, 301 f2e2, 302 f2e8, 303 f2f3, 304 f301, 305 f315, 306 f32b, 307 f347, 308 f365, 309 f389, 310 f3ae, 311 f3d9, 312 f405, 313 f437, 314 f469, 315 f4a1, 316 f4da, 317 f517, 318 f555, 319 f597, 320 f5da, 321 f620, 322 f667, 323 f6b1, 324 f6fb, 325 f749, 326 f796, 327 f7e6, 328 f834, 329 f887, 330 f8d7, 331 f92b, 332 f97b, 333 f9d3, 334 fa20, 335 fa6d, 336 fac2, 337 fb12, 338 fb63, 339 fbb3, 340 fc01, 341 fc4f, 342

fc9b, 343 fce6, 344 fd2f, 345 fd77, 346 fdbd, 347 fe01, 348 fe43, 349 fe84, 350 fec2, 351 fefe, 352 ff37, 353 ff6f, 354 ffa3, 355 ffd6, 356 0006, 357 0034, 358 005e, 359 0087, 360 00ac, 361 00d0, 362 00ef, 363 010f, 364 0128, 365 0143, 366 0157, 367 016d, 368 017c, 369 018e, 370 0197, 371 01a6, 372 01a9, 373 01bd, 374 01c9, 375 01a7, 376 01b4, 377 01ac, 378 01ac, 379 01a3, 380 019e, 381 0193, 382 018a, 383 017c, 384 0171, 385 0161, 386 0153, 387 0142, 388 0132, 389 0120, 390 010e, 391 00fb, 392 00e9, 393 00d6, 394 00c4, 395 00b1, 396 009f, 397 008c, 398 007b, 399 006a, 400 0059, 401 0049, 402 003b, 403 002c, 404 001f, 405 0012, 406 0008, 407 fffd, 408 fff5, 409 ffed, 410 ffe7, 411


ffe2, 412 ffdf, 413 ffdd, 414 6119; 415


f4_200pts.coe

; 1 ; XILINX CORE 2 Generator(tm)Distributed 3 Arithmetic FIR filter 4 coefficient (.COE) File 5 ; Generated by MATLAB(R) 6 7.10 and the Filter 7 Design Toolbox 4.7. 8 ; 9 ; Generated on: 02-Apr-10 2012 20:07:53 11 ; 12 Radix = 16; 13 Coefficient_Width = 16; 14 CoefData = ad37, 15 2e3a, 16 2435, 17 1d15, 18 1812, 19 1491, 20 1226, 21 107e, 22 0f64, 23 0ea9, 24 0e31, 25 0de2, 26 0db0, 27 0d88, 28 0d68, 29 0d43, 30 0d17, 31 0ce0, 32 0c9c, 33 0c47, 34 0be2, 35 0b68, 36 0add, 37 0a3c, 38 098c, 39 08c5, 40 07f0, 41 0704, 42 060c, 43 04ff, 44 03e7, 45 02bd, 46 018a, 47 0048, 48 ff00, 49 fdad, 50 fc5a, 51 fafe, 52 f9a5, 53 f845, 54 f6ef, 55 f594, 56 f44b, 57 f2fa, 58 f1c8, 59 f08b, 60 ef75, 61 ee68, 62 ed53, 63 ec81, 64 ebaa, 65 eae3, 66 ea3c, 67 e9c1, 68

e957, 69 e901, 70 e8ca, 71 e8bc, 72 e8cc, 73 e8fa, 74 e943, 75 e9a9, 76 ea34, 77 eae2, 78 ebaf, 79 ec9a, 80 ed9c, 81 eebc, 82 eff3, 83 f148, 84 f2b6, 85 f43d, 86 f5d5, 87 f77e, 88 f934, 89 faf8, 90 fcc8, 91 fea1, 92 0081, 93 0265, 94 0449, 95 062b, 96 0806, 97 09da, 98 0ba2, 99 0d5d, 100 0f07, 101 10a3, 102 122d, 103 13a1, 104 14fd, 105 1639, 106 1761, 107 1862, 108 194c, 109 1a0f, 110 1aaa, 111 1b2c, 112 1b8b, 113 1bbe, 114 1bcd, 115 1bbe, 116 1b8b, 117 1b2c, 118 1aaa, 119 1a0f, 120 194c, 121 1862, 122 1761, 123 1639, 124 14fd, 125 13a1, 126 122d, 127 10a3, 128 0f07, 129 0d5d, 130 0ba2, 131 09da, 132 0806, 133 062b, 134 0449, 135 0265, 136

0081, 137 fea1, 138 fcc8, 139 faf8, 140 f934, 141 f77e, 142 f5d5, 143 f43d, 144 f2b6, 145 f148, 146 eff3, 147 eebc, 148 ed9c, 149 ec9a, 150 ebaf, 151 eae2, 152 ea34, 153 e9a9, 154 e943, 155 e8fa, 156 e8cc, 157 e8bc, 158 e8ca, 159 e901, 160 e957, 161 e9c1, 162 ea3c, 163 eae3, 164 ebaa, 165 ec81, 166 ed53, 167 ee68, 168 ef75, 169 f08b, 170 f1c8, 171 f2fa, 172 f44b, 173 f594, 174 f6ef, 175 f845, 176 f9a5, 177 fafe, 178 fc5a, 179 fdad, 180 ff00, 181 0048, 182 018a, 183 02bd, 184 03e7, 185 04ff, 186 060c, 187 0704, 188 07f0, 189 08c5, 190 098c, 191 0a3c, 192 0add, 193 0b68, 194 0be2, 195 0c47, 196 0c9c, 197 0ce0, 198 0d17, 199 0d43, 200 0d68, 201 0d88, 202 0db0, 203 0de2, 204


0e31, 205 0ea9, 206 0f64, 207 107e, 208

1226, 209 1491, 210 1812, 211 1d15, 212

2435, 213 2e3a, 214 ad37; 215


f5_101pt.coe

; 1 ; XILINX CORE 2 Generator(tm)Distributed 3 Arithmetic FIR filter 4 coefficient (.COE) File 5 ; Generated by MATLAB(R) 6 7.10 and the Filter 7 Design Toolbox 4.7. 8 ; 9 ; Generated on: 02-Apr-10 2012 17:46:19 11 ; 12 Radix = 16; 13 Coefficient_Width = 16; 14 CoefData = c1c8, 15 4bcc, 16 3183, 17 24cd, 18 1eef, 19 1c6a, 20 1b5c, 21 1ac7, 22 1a2b, 23 1931, 24 17be, 25 15b5, 26 1316, 27 0fdb, 28 0c1b, 29 07d0, 30 0319, 31 fe05, 32 f8bb, 33 f347, 34 edd9, 35 e88b, 36 e38b, 37 dee8, 38 dacd, 39

d74c, 40 d48e, 41 d29f, 42 d19d, 43 d18e, 44 d284, 45 d46e, 46 d753, 47 db26, 48 dfe6, 49 e56f, 50 eba9, 51 f263, 52 f98f, 53 0104, 54 0898, 55 1007, 56 1741, 57 1e20, 58 2470, 59 29f7, 60 2ebe, 61 329e, 62 3555, 63 371e, 64 379e, 65 371e, 66 3555, 67 329e, 68 2ebe, 69 29f7, 70 2470, 71 1e20, 72 1741, 73 1007, 74 0898, 75 0104, 76 f98f, 77 f263, 78

eba9, 79 e56f, 80 dfe6, 81 db26, 82 d753, 83 d46e, 84 d284, 85 d18e, 86 d19d, 87 d29f, 88 d48e, 89 d74c, 90 dacd, 91 dee8, 92 e38b, 93 e88b, 94 edd9, 95 f347, 96 f8bb, 97 fe05, 98 0319, 99 07d0, 100 0c1b, 101 0fdb, 102 1316, 103 15b5, 104 17be, 105 1931, 106 1a2b, 107 1ac7, 108 1b5c, 109 1c6a, 110 1eef, 111 24cd, 112 3183, 113 4bcc, 114 c1c8; 115


f6_101pt.coe

; 1 ; XILINX CORE 2 Generator(tm)Distributed 3 Arithmetic FIR filter 4 coefficient (.COE) File 5 ; Generated by MATLAB(R) 6 7.10 and the Filter 7 Design Toolbox 4.7. 8 ; 9 ; Generated on: 02-Apr-10 2012 17:49:20 11 ; 12 Radix = 16; 13 Coefficient_Width = 16; 14 CoefData = 14b0, 15 0176, 16 006c, 17 fec0, 18 fca0, 19 fa57, 20 f837, 21 f694, 22 f5b1, 23 f5bb, 24 f6b9, 25 f88f, 26 fafd, 27 fdab, 28 0032, 29 0235, 30 036b, 31 03af, 32 030b, 33 01ba, 34 001d, 35 feb1, 36 fdf8, 37 fe60, 38 0032, 39

0374, 40 07e7, 41 0d09, 42 1219, 43 1636, 44 1879, 45 1820, 46 14a5, 47 0de8, 48 0430, 49 f841, 50 eb3f, 51 de98, 52 d3d4, 53 cc60, 54 c97b, 55 cbd6, 56 d39f, 57 e063, 58 f10d, 59 040d, 60 177a, 61 2950, 62 37a4, 63 40ec, 64 4422, 65 40ec, 66 37a4, 67 2950, 68 177a, 69 040d, 70 f10d, 71 e063, 72 d39f, 73 cbd6, 74 c97b, 75 cc60, 76 d3d4, 77 de98, 78

eb3f, 79 f841, 80 0430, 81 0de8, 82 14a5, 83 1820, 84 1879, 85 1636, 86 1219, 87 0d09, 88 07e7, 89 0374, 90 0032, 91 fe60, 92 fdf8, 93 feb1, 94 001d, 95 01ba, 96 030b, 97 03af, 98 036b, 99 0235, 100 0032, 101 fdab, 102 fafd, 103 f88f, 104 f6b9, 105 f5bb, 106 f5b1, 107 f694, 108 f837, 109 fa57, 110 fca0, 111 fec0, 112 006c, 113 0176, 114 14b0; 115


f7_101pt.coe

; 1 ; XILINX CORE 2 Generator(tm)Distributed 3 Arithmetic FIR filter 4 coefficient (.COE) File 5 ; Generated by MATLAB(R) 6 7.10 and the Filter 7 Design Toolbox 4.7. 8 ; 9 ; Generated on: 02-Apr-10 2012 17:43:52 11 ; 12 Radix = 16; 13 Coefficient_Width = 16; 14 CoefData = f5a9, 15 fd41, 16 fef2, 17 0131, 18 02cb, 19 02f9, 20 01e9, 21 00a1, 22 0046, 23 013a, 24 02bf, 25 0363, 26 020b, 27 fed4, 28 fb3e, 29 f952, 30 fa51, 31 fdd1, 32 01e4, 33 044b, 34 03fe, 35 01df, 36 002b, 37 00d0, 38 03e5, 39 074f, 40 0802, 41 0427, 42 fcb1, 43 f52c, 44 f1bd, 45 f477, 46 fbce, 47 035f, 48 06cb, 49 04c0, 50 0024, 51 fe63, 52 037e, 53 0e8f, 54 1924, 55 1a70, 56 0cd4, 57 f282, 58 d608, 59 c5d1, 60 cc9b, 61 eafb, 62 15c8, 63 3ac1, 64 494c, 65 3ac1, 66 15c8, 67 eafb, 68

cc9b, 69 c5d1, 70 d608, 71 f282, 72 0cd4, 73 1a70, 74 1924, 75 0e8f, 76 037e, 77 fe63, 78 0024, 79 04c0, 80 06cb, 81 035f, 82 fbce, 83 f477, 84 f1bd, 85 f52c, 86 fcb1, 87 0427, 88 0802, 89 074f, 90 03e5, 91 00d0, 92 002b, 93 01df, 94 03fe, 95 044b, 96 01e4, 97 fdd1, 98 fa51, 99 f952, 100 fb3e, 101 fed4, 102 020b, 103 0363, 104 02bf, 105 013a, 106 0046, 107 00a1, 108 01e9, 109 02f9, 110 02cb, 111 0131, 112 fef2, 113 fd41, 114 f5a9115


f8_101pt.coe

; 1 ; XILINX CORE 2 Generator(tm)Distributed 3 Arithmetic FIR filter 4 coefficient (.COE) File 5 ; Generated by MATLAB(R) 6 7.10 and the Filter 7 Design Toolbox 4.7. 8 ; 9 ; Generated on: 02-Apr-10 2012 17:03:57 11 ; 12 Radix = 16; 13 Coefficient_Width = 16; 14 CoefData = 0222, 15 ffe7, 16 0035, 17 00ab, 18 ff72, 19 fdb0, 20 fef9, 21 021d, 22 021f, 23 ff7a, 24 ff11, 25 0021, 26 fe84, 27 fd10, 28 009b, 29 0466, 30 01e3, 31 fde5, 32 fee6, 33 ffd0, 34 fc63, 35 fcd9, 36 04a0, 37 0758, 38 ffb4, 39

faff, 40 fec8, 41 fecb, 42 fa09, 43 ff9e, 44 0bbf, 45 088c, 46 f967, 47 f73d, 48 ff9c, 49 fcb1, 50 f84b, 51 0894, 52 174c, 53 0431, 54 ea59, 55 f297, 56 02f6, 57 f7d1, 58 f9c4, 59 2924, 60 3650, 61 dff6, 62 93e3, 63 dcec, 64 6760, 65 6760, 66 dcec, 67 93e3, 68 dff6, 69 3650, 70 2924, 71 f9c4, 72 f7d1, 73 02f6, 74 f297, 75 ea59, 76 0431, 77 174c, 78

0894, 79 f84b, 80 fcb1, 81 ff9c, 82 f73d, 83 f967, 84 088c, 85 0bbf, 86 ff9e, 87 fa09, 88 fecb, 89 fec8, 90 faff, 91 ffb4, 92 0758, 93 04a0, 94 fcd9, 95 fc63, 96 ffd0, 97 fee6, 98 fde5, 99 01e3, 100 0466, 101 009b, 102 fd10, 103 fe84, 104 0021, 105 ff11, 106 ff7a, 107 021f, 108 021d, 109 fef9, 110 fdb0, 111 ff72, 112 00ab, 113 0035, 114 ffe7, 115 0222; 116


f9_101pt.coe

; 1 ; XILINX CORE 2 Generator(tm)Distributed 3 Arithmetic FIR filter 4 coefficient (.COE) File 5 ; Generated by MATLAB(R) 6 7.10 and the Filter Design 7 Toolbox 4.7. 8 ; 9 ; Generated on: 02-Apr-10 2012 16:53:42 11 ; 12 Radix = 16; 13 Coefficient_Width = 16; 14 CoefData = fff4, 15 0143, 16 0008, 17 ff86, 18 0012, 19 008f, 20 ffd7, 21 ff5d, 22 0047, 23 00b4, 24 ff94, 25 ff3e, 26 0099, 27 00cb, 28 ff33, 29 ff33, 30 0108, 31 00c6, 32 feb5, 33 ff4b, 34 0193, 35 0096, 36 fe1f, 37 ff98, 38 0234, 39

0028, 40 fd76, 41 002d, 42 02e1, 43 ff65, 44 fcc7, 45 0127, 46 038f, 47 fe2a, 48 fc1d, 49 02b3, 50 0431, 51 fc32, 52 fb87, 53 0540, 54 04b9, 55 f8c4, 56 fb10, 57 0a32, 58 051b, 59 f0c1, 60 fac5, 61 1a86, 62 054f, 63 aeba, 64 7aab, 65 aeba, 66 054f, 67 1a86, 68 fac5, 69 f0c1, 70 051b, 71 0a32, 72 fb10, 73 f8c4, 74 04b9, 75 0540, 76 fb87, 77 fc32, 78

0431, 79 02b3, 80 fc1d, 81 fe2a, 82 038f, 83 0127, 84 fcc7, 85 ff65, 86 02e1, 87 002d, 88 fd76, 89 0028, 90 0234, 91 ff98, 92 fe1f, 93 0096, 94 0193, 95 ff4b, 96 feb5, 97 00c6, 98 0108, 99 ff33, 100 ff33, 101 00cb, 102 0099, 103 ff3e, 104 ff94, 105 00b4, 106 0047, 107 ff5d, 108 ffd7, 109 008f, 110 0012, 111 ff86, 112 0008, 113 0143, 114 fff4; 115


Appendix D: Cost and Scheduling

Table 12: Bill of Materials and Total Cost

Component Manufacturer Distrib Ref Name Qty Req'd Ordered

Extended Price

1N914A FSC none D74 D73 2 2 $ -

3MM_LED_RED Kingbright Mouser D1-D72 72 100 $ 9.00

AWHW40G-0202-T-R Assmann WSW Components Digi-Key J1 1 1 $ 0.95

CB2518T4R7M TaiyoYuden Digi-Key L1 1 3 $ 0.42

GRM21BF51A106ZE15L Murata Digi-Key C23 C10 C12 C24 C26 C27 C28 C29 8 10 $ 4.78

GRM219R71C104KA01D Murata Digi-Key C22 C4 C3 C1 C2 C5 C6 C7 C8 C9 10 20 $ 6.12

PS30-10PB10BR10K TT Electronics/BI Digi-Key

R6 R9 R12 R15 R18 R21 R24 R27 R30 9 10 $ 10.54

71600-040LF FCI Digi-Key

1 2 $ 4.22

RC0805FR-071KL_1 Yageo Digi-Key

R8 R11 R14 R17 R20 R23 R26 R29 R32 R33 R36 11 20 $ 0.40

RC0805FR-071M62L_1 Yageo Digi-Key R38 1 10 $ 0.20

RC0805FR-072KL_1 Yageo Digi-Key R1 R2 R3 R4 R5 5 10 $ 0.20

RC0805FR-078K2L_1 Yageo Digi-Key

R7 R10 R13 R16 R19 R22 R25 R28 R31 R34 R37 11 20 $ 0.40

RC0805FR-0710KL_1 Yageo Digi-Key R35 1 10 $ 0.20

RC0805FR-07180KL_1 Yageo Digi-Key R39 1 10 $ 0.20

SN74LVCH16244ADGGRG4 Texas Instruments TI U1 1 3 $ -

TLC541IDW Texas Instruments TI U13 1 3 $ -

TLC59281DBQR Texas Instruments TI U2 U3 U4 U5 U6 5 9 $ -

TLV1117-33CDCYR Texas Instruments TI U7 U8 2 3 $ -

TPS61072DDCRG4 Texas Instruments TI U14 1 3 $ -

TPSB107K006R0250 Texas Instruments Digi-Key C11 C13 C25 3 6 $ 4.56

Digikey Shipping & Tax USPS Digi-Key

1 1 $ 5.61

Mouser Shipping & Tax USPS Mouser

1 1 $ 8.76

Custom PCB (incl ship and tax) Advance Circuits

Advanced Circuits

1 1 $ 61.70

68-pin SCSI cable Maddison Cable Corp Halted Specialties

1 1 $ 5.00

Digilent Atlys (incl ship and tax) Digilent

Halted Specialties

1 1 $ 210.45

Misc cables Various Halted Specialties

1 1 $ 15.00

Total $ 348.71


Table 13: Gantt chart showing actual project progress

Month April May June

Week (starting Monday) 22 9 16 23 30 7 14 21 28 4 11 18 25

Component selection

Firmware development

Schematic design

PCB Layout

Hardware assembly and test

Firmware test

Design filters

Final system integration

Test and tweak

Documentation

Appendix E: References

[1] Ashok Ambardar, Analog and Digital Signal Processing, 2nd ed. Pacific Grove, California: Brooks/Cole

Publishing Company, 1999.

[2] et al Kitazato, Digital Graphic Equalizer, Patent # 4,661,982, 1987.

[3] Digilent Incorporated. (2011, February) Atlys C2 Reference Manual. [Online]. www.digilentinc.com

[4] Kingbright. (2011, March) T-1 (3mm) Solid State Lamp WP710A10SRC/E, Datasheet. [Online].

www.kingbrightusa.com

[5] Texas Instruments, Incorporated. (2011, January) TLC59281 16-Channel, Constant-Current LED Driver,

Datasheet. [Online]. www.ti.com

[6] Michael Leddige. (2006, December) Transmission Line Basics II - Class 6. [Online]. www.intel.com

[7] Texas Instruments, Incorporated. (2001, June) TLC541L 8-BIT Analog-to-Digital Converters with Serial

Control and 11 Inputs, Datasheet. [Online]. www.ti.com

[8] TT Electronics. (2009, December) Model PSxx Slide Potentiometer, Datasheet. [Online].

www.bitechnologies.com

[9] Digilent, Incorporated. (2010, June) Digilent Incorporated Web Site. [Online]. www.digilentinc.com

[10] Xilinx, Incorporated. (2011, October) Spartan-6 FPGA Data Sheet: DC and Switching Characteristics,

Datasheet. [Online]. www.xilinx.com

[11] Texas Instruments, Incorporated. (2010, August) TLV1117, Adjustable and Fixed Low-Dropout Voltage

Regulator, Datasheet. [Online]. www.ti.com

[12] Xilinx, Incorporated. (2011, October) LogiCORE IP FIR Compiler v5.0, Datasheet. [Online]. www.xilinx.com

www.digilentinc.com

www.kingbrightusa.com

www.ti.com

www.intel.com

www.ti.com

www.bitechnologies.com

www.digilentinc.com

www.xilinx.com

www.ti.com

www.xilinx.com


[13] Xilinx, Incorporated. (2011, May) Spartan-6 FPGA Clocking Resources. [Online]. www.xilinx.com

[14] Intel Corporation. (2000, september) Audio Codec '97, White Paper. [Online]. www.intel.com

[15] Texas Instruments, Incorporated. (2005, November) SN74LVCH16244A 16-bit Buffer/Driver with 3-state

Outputs, Datasheet. [Online]. www.ti.com

[16] National Semiconductor Corporation. (2002, December) LM4550 AC '97 Rev 2.1 Multi-Channel Audio

Codec with Stereo Headphone Amplifier, Sample Rate Conversion and National 3D Sound, Datasheet.

[Online]. www.national.com

www.xilinx.com

www.intel.com

www.ti.com

www.national.com

Digital Graphic Equalizer Implemented Using an FPGA · 2017-07-25 · G raph ic Equ l ze Nine LED...

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