Digital Fundamentals -...
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Digital Fundamentals Logic gates
Transcript of Digital Fundamentals -...
Digital Fundamentals
Logic gates
Objectives
•Describe the operation of the inverter, the AND gate, and the OR gate
•Describe the operation of the NAND gate and the NOR gate
•Express the operation of the NOT, AND, OR, NAND, and NOR gates with Boolean algebra
•Describe the operation of the exclusive-OR and exclusive-NOR gates
•Recognize and use both the distinctive shape logic gate symbols and the rectangular outline logic gate symbols of ANSI/IEEE Standard 91-1984
•Construct timing diagrams showing the proper time relationships of inputs and outputs for the various logic gates
•Make basic comparisons between the major IC technologies - CMOS and TTL
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•Explain how the different series within the CMOS and TTL families differ from each other
•Define propagation, delay time, power dissipation, speed-power product, and fan-out in relation to logic gates
•List specific fixed-function integrated circuit devices that contain the various logic gates
•Use each logic gate in simple applications
•Troubleshoot logic gates for opens and shorts by using the logic pulser and probe or the oscilloscope
•Describe the basic concepts of programmable logic
Inverter
Check out the file F03-02!
Thruth table
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AND Gate
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Pulsed operation
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Logic expressions for an AND gate
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Enable/inhibit function with an AND gateAND works as a gate for the clock signal
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Seat belt alarm system
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OR Gate
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0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 1
Logic expressions for an OR gate
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Simplified intrusion detection
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NAND Gate
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Equivalent operations!
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Example
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Example
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NOR Gate
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Equivalent operations!
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Example
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Exclusive-OR Gate
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Exclusive-NOR Gate
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Pulsed operation
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Example
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Fixed-function logic: IC gates
5V
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3V3
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Fixed-function logic gates - Examples
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IC packages
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Pin configuration diagrams for some common fixed-function ICs
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Logic symbols for hex inverter
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Performance characteristics and parameters
propagation delay time
PLHPHL tandt
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DC Supply voltage (marked VCC)
With CMOS gates you can use wider supply voltage range:5V CMOS tolerates supply variations from 2V to 6V,3V3 CMOS tolerates supply variations from 2V to 3.6V
TTL requires stable supply voltage: maximum variationis +/- 10% (i.e. 4.5V to 5.5V)
Power dissipation (marked PD)
supply current with HIGH ouput
supply current with LOW ouput
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+=2
CCLCCHCCD
IIVP
CMOS power dissipation is usually smaller compared to TTL, but the dissipationdepends on frequency (power dissipation for TTL has no frequency dependence).
Input and output logic levels
5V CMOS
1.5V
3.5V
5V CMOS
0.33V
4.4V
TTL
0.8V
2V
TTL
0.4V
2.4V
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Speed-power product (SPP)
DPPtSPP =
can be used to compared devices when considering both the speed and the dissipation power
Fan-out and loading
Fan-out is the number of inputs (of the same IC family) that can be connected to its output and stillmantain the output voltage levels within specified limits.
In CMOS circuits the fan-out is high but depends on frequency thru capacitive effects
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Comparison of propagation delay time and power in CMOS and TTL
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How to read datasheets and find the information you need
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Troubleshooting
Internal failures – An open TTL input acts as a HIGH level
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Troubleshooting a NAND gate for an open input
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Troubleshooting a NOR gate for an open input
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Example
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Example
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Example
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Programmable arrays – OR array
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Programmable arrays – AND array
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Classification of SPLDs – PROM
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Classification of SPLDs – PLA (programmable logic array)
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Classification of SPLDs – PAL (programmable array logic)
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Classification of SPLDs – GAL
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Summary
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Summary
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