Digital Fundamentalselectronics.physics.helsinki.fi/wp-content/uploads/2012/01/luento10.pdf ·...
Transcript of Digital Fundamentalselectronics.physics.helsinki.fi/wp-content/uploads/2012/01/luento10.pdf ·...
Objectives
•Identify the basic forms of data movement in shift registers
•Explain how serial in/serial out, serial in/parallel out, parallel in/serial out, and parallel in/parallel out shift registers operate
•Describe how a bidirectional shift register operates
•Determine the sequence of a Johnson counter
•Set up a ring counter to produce a specified sequence
•Construct a ring counter from a shift register
•Use a shift register as a time-delay device
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•Use a shift register as a time-delay device
•Use a shift register to implement a serial-to-parallel data converter
•Implement a basic shift-register-controlled keyboard encoder
•Troubleshoot a digital system by "exercising" the system with a known test pattern
•Interpret ASNI/IEEE Standard 91-1984 shift register symbols with dependency notation
•Describe a basic CPLD
•Use shift registers in a system application
Figure 10--1 The flip-flop as a storage element.
Basic shift register functions
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in the SET state in the RESET state
Figure 10--2 Basic data movement in shift registers. (Four bits are used for illustration. The bits move in the direction of the arrows.)
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Figure 10-6Example 10-1: Show the states for the specified data input and clock waveforms. Open file F10-06 to verify operation.
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Figure 10--7 Logic symbolfor an 8-bit serial in/serial out shift register (SISO).
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Figure 10--8 A serial in/parallel out shift register (SIPO).
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Figure 10-9 Example 10-2: Show the states of the 4-bit register (SRG 4). The register initially contains all 1s.
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Figure 10--10 The 74HC1648-bit serial in/parallel out shift register (SIPO).
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Figure 10--12 A 4-bit parallel in/serial out shift register (PISO). Open file F10-12 to verify operation.
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Figure 10-13 Example 10-3: Show the data-output waveform for a 4-bit register.
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i.e. the LSB
Figure 10--16 A parallel in/parallel out register (PIPO).
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Figure 10--18 Sample timing diagram for a 74HC195 shift register.
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Figure 10--19 Four-bit bidirectional shift register. Open file F10-19 to verify the operation.
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Figure 10-20 Example 10-4: Determine the state of the shift register after each clock pulse for the given inputs
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Figure 10--22 Sample timing diagram for a 74HC194 shift register.
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Figure 10--23 Four-bit and 5-bit Johnson counters.
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Figure 10--24Timing sequence for a 4-bit Johnson counter
Figure 10—25 Timing sequence for a 5-bit Johnson counter
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Figure 10—25 Timing sequence for a 5-bit Johnson counter
Figure 10--26 A 10-bit ring counter. Open file F10-26 to verify operation.
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Figure 10-27 Example 10-5: If a 10-bit ring counter has the initial state 1010000000, determine the waveform for each of the Q outputs
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Figure 10-28The shift register as a time-delay device.
Shift register applications
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Figure 10-29 Example 10-6: Determine the amount of time delay between the serial input and each output in the next figure.
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Figure 10--30 Timing diagram showing time delays for the register in Figure 10-29.
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Figure 10-31 74HC195 connected as a ring counter.
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Figure 10--33 Simplified logic diagram of a serial-to-parallel converter.
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Figure 10--34 Serial data format.
Figure 10-35 An example of a timing diagramfor the serial-to-parallel data converterin fig. 10-33.
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Figure 10-36UART interface (Universal Asynchronous receiver transmitter)
Figure 10-37 Basic UART blockdiagram
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diagram
Figure 10--39 Sample test pattern.
Troubleshooting
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Figure 10-41 Properoutputs for the circuit under test in Figure 10-40. The input test pattern is shown.
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Figure 10-42 Logic symbol for the 74HC164
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Figure 10--43 Logic symbol for the 74HC194.
Do nothing: S0 = 0, S1 = 0 (mode 0)
Shift right: S0 = 1, S1 = 0 (mode 1, as in 1, 4D)
Shift left: S0 = 0, S1 = 1 (mode 2, as in 2, 4D)
Parallel load: S0 = 1, S1 = 1 (mode 3, as in 3, 4D)
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Figure 10--44 Basic diagram of a CPLD.
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Figure 10-45 Basic logic array block in a CPLD
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Figure 10--46 Basic CPLD macrocell.
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Figure 10--47 Basic E2CMOS interconnection technology.
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Figure 10--48 Block diagram of MAX 7000 CPLDs. Data sheets can be found at www.altera.com.
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Figure 10--49 Basic logic diagramof the security entry system.
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Figure 10--51
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