# Digital Electronics

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### Transcript of Digital Electronics

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LOGIC GATESADDERS

FLIP-FLOPSREGISTERS

Digital Electronics

Mark Neil - Microprocessor Course

Numbers in a computer:

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In the Microprocessor and memory Bits are stored electronically

Each bit is represented by an electrical signal which is either a high or low voltage level. High 1 and low 0 High 0 and low 1

Normal Logic

Inverse Logic

High and Low

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1:‘High’

0:‘Low’

CMOS

NO MAN’S LAND74HCxx

0.1 – 1.0 Volts

3.5 – 4.9 Volts

Transistor Transistor Logic (TTL)

NO MAN’S LAND74LSxx

0.8 – 0.4

Volts

2.0 – 2.4

Volts

It is actually a bit more complicated than this since there are different thresholds for inputs and outputs and their noise margins (indicated here in RED)..

Making a Zero or a One

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How do you actually make a 0 or 1 ?

It is clear that depending upon the position of the J1

switch the line will be either ‘0’ or ‘1’

Pull-up resistor

Making a Zero or a One

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How do you actually make a 0 or 1 in CMOS?

0

+V

1

+V

?

+V

?

+V

“Tri-state” outputHigh

impedance

BANG!

J1

J2

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Binary Logic

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Once the bits are generated, we want to be able to perform various operations on those bits

The operations which the microprocessor carries out can all be constructed with a few simple circuits

The basic building blocks are logic “gates”

Binary Logic truth tables

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A B AND

0 0 0

0 1 0

1 0 0

1 1 1

A B OR

0 0 0

0 1 1

1 0 1

1 1 1

A NOT

0 1

1 0

• You may remember from the first year lab the gates AND, OR, NOT

• Any digital device can be made out of either ORs and NOTs or ANDs and NOTs.

DeMorgan’s Theorem

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You can swap ANDs with ORs if at the same time you invert all inputs and outputs :

Exercise: Write truth table for both and prove that this is correct

An AND out of NOTs and ORs

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Exercise: Test the claim that you can make any logic device exclusively out of NOTs and ORs by making an AND out of NOTs and ORs:

Answer:

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Show that this device has an identical truth table as the AND gate.

Exercise: Exclusive OR

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Construct an exclusive OR (XOR) gate using OR, ANDs, and NOT:

A B XOR

0 0 0

0 1 1

1 0 1

1 1 0

The Exclusive OR

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Solution:

Addition with Binary Logic Gates

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Example: Adding two 4 bit numbers results in a 4 bit number plus one carry bit or effectively a 5 bit numberLets construct this adder from gates

Computers carry out addition with binary addition of bits stored in registers

We can build additions of large numbers of bits out of units which add two bits

$3+$4 $3+$C $D+$4 $D+$C

0011 0011 1101 1101

+ 0100 + 1100 + 0100 + 1100

= 0111 = 1111 =10001 =11001

$7 $F $11 $19

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Additions of two bits: The half adder

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A B C S

0 0 0 0

1 0 0 1

0 1 0 1

1 1 1 0

Adding two bits generates two bits of output 1 “Sum Bit” S 1 “Carry Bit” C

The truth table for this operation is shown along with an implementation using two gates

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Full Adder

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In order to add larger numbers, we need to be able to bring the carry from the lower order bits, and add this to the sum

The inputs are: the two bits to be added (A,B) The Carry Bit (C)

The outputs are: The Sum Bit (S) The Carry Out Bit (C+)

We can build this from two half adders and an XOR gate

A B C C+ S

0 0 0 0 0

0 1 0 0 1

1 0 0 0 1

1 1 0 1 0

0 0 1 0 1

0 1 1 1 0

1 0 1 1 0

1 1 1 1 1

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Two bit adder

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We can construct logic that adds more than 1 bit together by using multiple full adder circuits

Exercise:Draw a circuit that adds two two bit words (Ao,A1) and (B0,B1) and produces three Sum Bits (S0,S1,S2)

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Solution

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With the Full adder building block we can generalize to produce a circuit which adds larger numbers

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Four plus Four bit addition

This can clearly be generalized to any number of bits

There is a problem in building circuits this way as the carry bits need to propogate through the circuit before the answer is correct

There are other ways to construct adder circuits which avoid this problem

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Storing Zeros and Ones: Registers

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Registers are electronic devices capable of storing 0’s or 1’s

D-FLIP-FLOPs are the most elementary registers can store one bit

8 DFFs clocked together make a one byte register Capable of storing 8 bits

SR Latch: Set and Reset

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Gate level design of an SR latch

S* R* Q Q*

0 1 1 0

1 0 0 1

• When S* is low and R* High, Q is high (Set)

• When S* is high and R* is low Q is cleared (Reset)

• Q and Q* are complements

SR Latch: Hold

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Gate level design of an SR latch

S* R* Q Q*

1 1 1 0

1 1 0 1

• When S* and R* are high both states for Q are possible (and stable)

• The latch remembers the last state it was in, and holds Q in that state

SR Latch: Don’t do this…

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Gate level design of an SR latch

S* R* Q Q*

0 0 1 1

• When S* and R* are low Q and Q* are no longer complementary

• The latch can also enter a race condition if you try to take S* and R* high again “at the same time”

SR Latch: 1 bit memory

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Gate level design of an SR latch

S R Q Q*

H H H L

H H L H

H L L H

L H H L

L L H H

• S/R high is ambiguous, but stable

• This circuit “remembers” that S went low

Ambiguous but stable

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Gated D Latch

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Ensures that S and R are always complementary. When the Clock is high – D is set on the outputs of the latch and it is held there when the clock is lowExercise: Fill out the truth table for this circuit.

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D latch timing

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The input Data to the gated D latch appears on the output (Q)while the clock is high.

Sometimes we want to transfer the data into the register only at a specified moment (for example when the clock changes)

The Master-Slave D Flip-Flop uses two d-latches to latch the data on the edge (depending on the design either positive or negative) of the input clock

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Master Slave – D Flip Flop

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Data is stored in the “Master” latch (Qm) when the clock is high

When the clock goes from high to low The data is held in

the Master The Data is stored in

the slave latch output

The Qs output can only change when the clock goes from high to low

A real D-Flip-Flop (DFF)

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CLK D S R Q Q-bar

X X L H H L

X X H L L H

X X L L H H

H H H H L

L H H L H

When S and R are High, on the rising edge of the clock the data are transferred and stored in Q.

One can Set or Reset (Clear) the DFF using S or R

4-bit Register

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A register that stores

4 bits

Data coming inD0,D1,D2,D3

Data Stored on rising edge of clock inQ0,Q1,Q2,Q3

Byte Register

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8 bit register in a single package

74F574Also contains tri-state outputs

CLK

Byte coming in

Byte Stored

Arithmetic Logic Unit (ALU)

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Centre of every computer

Composed of building blocks we have been learning about Adders Flip Flops Registers

We also need to have a data bus to move data in and out - we will learn about this soon

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Exercise: build an external 1 Byte memory

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CP (Write Data)

Byte coming in(PORTA)

Byte Stored(PORTE)

Output Enable* (Read Data)

* = INVERTED

Control lines(PORTD)

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The data sheets of the 74F574

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The 74F574 outputs

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The outputs of the 574 are tri-state : They Can be high ‘1’, low ‘0’, and DISCONNECTED

(HIGH IMPEDANCE STATE).

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The 74F574 Function Table

When Output Enable (OE*) is low, the data can be read from the register

Data can be written to the register at any time by driving the Clock Pulse (CP) from low to high

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Timing diagram: Load Register – Enable Output

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CP

OE

O0-O7

D0-D7

ts = setup time

ts

tPZH = Output Enable time

tPZH

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Timing diagram: write with OE Low

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CP

OE

O0-O7 (out)

D0-D7 (in)

Tp = propagation delay

tp