DIGITAL ELECTRONICS - polito.it · 2009-04-28 · Digital Electronics - A2 28/04/2009 2009 DDC -...

Digital Electronics - A2 28/04/2009

2009 DDC - 2006 Storey 1

28/04/2009 - 1 DigElnA2 - 2009 DDC

DIGITAL ELECTRONICS

A – INTRODUCTIONA.2 – Logic circuits parameters

» Static parameters» Interfacing and compatibility» Output stages» Dynamic parameters

Politecnico di Torino - ICT school

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A2: logic circuits parameters

• Review of digital circuits parameters• Static electrical characteristics; V/I parameters• Interfacing and compatibility• Transcharacteristic of inverter• Output stage: OC, TP, 3S• Models for the output stage• Dynamic parameters: Tr, Tf, Tp; • RC models for delay evaluation

– Reference 1: Storey, ch 14– Reference 2:

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Digital modules

• A digital module uses – A Power Supply (VPW– GND) – Input and out signals, represented as binary words

» Groups of 1/0, in serial or parallel format

1 0 0 1 ...

DIGITALMODULE

0110

VPW

GND

1100

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Power supply and signal

• Power supply voltage VPW is (mostly) a positive voltage

– Some modules use several supply voltages– Most usual values: 5 V; 3,3 V; 2,5 V; 1,8 V; ..... 0,8 V

• Here we analyze signals on single inputs and outputs– Results usable for modules with any number of inputs and

outputs

DIGITALMODULE

1 0 0 1 ... 1 0 0 1 ...

VPW

GND


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Logic states and voltage levels

• Logic states (0/1, L/H) are represented by electric quantities (usually voltages: V)

• The logic state ↔ voltage assignment is arbitrary– “positive logic”: 1↔VH ; 0↔VL

– “negative logic”: 0↔VH ; 1↔VL

• In this course

– state 1, H :electric level High, most positive voltage, labeled as VH

– state 0, L :electric level Low, most negative voltage, labeled as VL

VH (1)

VL (0)

V

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Output of logic circuits

• SPDT switch at the output

• First approximation model: – VH = VPW and VL= 0V (GND)

state 1, H :VO = VH

state 0, L :VO = VL

VH ≈ VPW

VL ≈ 0V, GND

VO

VO

VPW

0V

VO

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VT

VI

Input of logic circuits

• Sense the logic state by comparing the input voltage VI with a threshold VT.

VI > VT: state H

VI < VT: state L

VI

Sensed asHigh state

Sensed asLow state

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VH

VL

VO

High level

Low level

VT

VISensed asHigh state

SensedasLow state

Input – output connection

• VI comes from a logic output; VO and VI must match.

VO VI


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Output levels and Input threshold

• Manufacturer cannot guarantee the value of VO;

– Two limit values are specified: VOH and VOL

• Manufacturer cannot guarantee the value of VT

– Two limit values are specified: VIH and VIL

VOH

VOL

VO VI

VIH

VIL

VI > VIH: state H

VI < VIL: state L

VO > VOH: state H

VO < VOL: state L

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High level

Low level

Allowedrangefor input voltage

VIMIN

VIH

VIL

V

VOH

VOL

VIMAXVOmax

inputoutput

IN/OUT specifications

• Ranges, not levels

VOmin

Correctvalues foroutput voltages

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Connection among logic gates

• With these ranges the input reads the correct logic states from the output voltage

High level

Low level

VT

VOVI

VOH

VOL

VIH

VIL

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Compatibility of logic circuits

• Compatible logic circuits can exchange logic states – Inputs read in the correct way the output voltage levels.

• Conditions for logic compatibility:

– VOL < VIL

» Guarantees that the voltage issued by a LOW logic output is read as LOW state by logic inputs connected to that output.

– VOH > VIH

» Guarantees that the voltage issued by a HIGH logic output is read as HIGH state by logic inputs connected to that output.

– To guarantee compatibility in any condition :» use VILmax,VIHmin,VOHmin, VOLmax


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VOH

VOL

VO

Output A Input 1 Input 2

VI

VIH1

VIL1

VIH2

VIL2

VI

An example of (in)compatibility

• Output A drives 1 and 2 inputs with the voltage V’– Input 1 senses V’ as High state (V’ > VIH2)– Input 2 may read V’ as High or Low state

» If VT between V’ and VIH2, it is sensed as Low

2

1A

V’V’

Storey, Electronics: A Systems Approach, 3rd Edition © Pearson Education Limited 2006A2.14

Logic families

We have seen that different devices use different voltages ranges for their logic levels.

They also differ in other characteristics.

In order to assure correct operation when gates are interconnected they are produced in families .

Digital circuits which belong to the same family have compatible IN/OUT V and I levels.

14.3

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Actual signals

• Noise and interferences modify the output voltage.

The output rangesbecome wider VT

VOVI

VOH

VOL

VIH

VIL

Interconnection(group D)

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Noise margins

• The gaps VOH - VIH , and VOL- VIL guaranteecorrect sensing of the logic state, even with noise

• The gap is called noise margin:

NMH = VOH - VIH

• NML = VIL - VOL

VIMIN

High level

Low level

VIH

VIL

V

VIMAX

inputoutput

Noisemargin

VOH

VOL

Undefinedlogic state


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Digital signal recovery

• All digital inputs compare VI with a threshold

• The input circuit verifies if VI >< VT

• The output issues VOvoltages external to VOH-VOL

Vin

Vout

VT

VOH

VOL

DIGITAL MODULE

INPUT CIRCUIT

Vin VH/VLLOGIC

OPERATOR

VoutOUTPUT CIRCUIT

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Logic inverter with MOS transistor

• Structure:– VGS = VI

– nMOS (used as Switch)towards GND

– RPU towards power supply

• Behavior:– VI ≈ 0V < VTH (state I = L)

» MOS OFF, SW open» VU ≈ VAL (state U = H)

– VI = VAL > VTH (state I = H)» MOS ON, SW closed» VU ≈ 0V (state U = L) GND

VPW

UI SWn

RPU

VPW

VO

VI

MOSn

RPU

G

S

D

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Inverter transcharacteristic

• Basic inverter VO(VI) transcharacteristic.

VI

VO

VI VO

Input voltageVi ≈ 0V; output Vo ≈ Val

VAL

VO

VIMOSn

RPU Intermediate levels; undefined logic state

Input voltage Vi ≈ Val; output Vo ≈ 0V


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Simplified equivalent output circuit

• Low state: output to ground

• High state: VAL through RPU

GND

VAL

VO

GND

VAL

RPUVO

RPU

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Refined equivalent output circuit

• Low state: partition of VAL(RON << RPU)

• High state: VAL through RPU

GND

VAL

IOFF

VO

GND

VAL

RPU

RON

VO

RPU

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Inverter with load

• Output parameters:– Val = 5 V– Rpu = 10 kΩ– Ron = 100 Ω– Ioff = 100 nA

• Evaluate Vo (for L and H states)– No-load– Load 10 kΩ towards GND– Load 3 kΩ towards Val, and towards 3V– Load 1 kΩ towards Val, 3V, GND– Load 300Ω towards Val, 3V, GND

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Inverter with load: discussion

• The leakage current Ioff in most cases has negligible effect

• Loads towards GND:– no effect on the Low output voltage (in some cases improve

it: more close to ground)– Move towards GND the High output voltage: actual effect

must be verified

• Loads towards VAL:– no effect on the High output voltage (in some cases improve

it: more close to VAL)– Move towards VAL the Low output voltage: actual effect must

be verified.


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Complementary MOS inverter

• CMOS structure– Combination of nMOS (towards GND) and pMOS (towards

Val)» Output = 1 when I = 0 (SWp closed, SWn open)» Output = 0 when I = 1 (SWp open, SWn closed)

GND

VAL

U

GND

VAL

U

I

VAL

GND

UIMOSp

I MOSn

D

D

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CMOS inverter: characteristic

VGSn = VI > VTHn MOSn fully ONVGSp = VI - VAL > VTHp

MOSp fully OFFMixed case; both MOSn and MOSp partially ON

VGSn = VI < VTHn

MOSn fully OFFVGSp = VI - VAL < VTHp

MOSp fully ON

VAL

VGSp = VI - VAL

VGSn = VI

ID

VI

0

VAL

GNDVI

VGSp

VGSn

G

Sn

Dn

Sp

DpVTHn VTHp

0

0

-VAL

VAL

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Features of CMOS inverter

• Fully symmetric structure– The MOS/SW pair operate as a unique SPDT switch which

brings the output to GND or to the power supply.– No pull-up or pull-down resistor– Symmetric behavior in H and L states

VAL

GND

UI

SWp

SWn

U

GND

I

VAL

VAL

GND

UI

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CMOS inverter transcharacteristic

• Compared with R-SW– Symmetric– More steep

VI

VO

VI VO

Input VI ≈ 0V; Output VO ≈ VAL

Intermediate voltage, undefinedlogic behavior

Input VI ≈ VAL; Output VO ≈ 0V

GND

VI

G

S

D

S

D

VAL

VO


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Current CMOS devices

• Actual circuits have very steep transcharacteristic

• Input voltages are interpreted as H/L comparing the level with a threshold VT

– VI > VT H

– VI < VT L

Threshold voltage

VT VI

VO

VI < VT LVO ≈ VAL H VI > VT H

VO ≈ 0V L

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VIH and V IL parameters

• VT changes with power supply, temperature, ….

– VT does not have a precise value

– Manufactures can guarantee a range for VT: VIL….VIH

• VI >VIH logic state H• VI < VIL logic state L• VIL< VI < VIH

– Undefined logic state

VI

VO

VOH

VOL

VTVIH

VIL

45°tangents

State L State H???

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Example: logic inverters

Transcharacteristic of a BJT logic gate (74LS04)A: Val = 5VB: Val = 3V

Transcharacteristic of a CMOS device(74HC04)C: Val = 5VD: Val = 3V

VH output andThreshold VT

change with Val

No change of VT !

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CMOS equivalent circuit

• The output MOS have an equivalent resistance RO

– Different towards GND or Val (nMOS and pMOS)

GND

VO

VAL

GND

VAL

ROH

ROL

VOVI


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Logic circuits output types

• Totem Pole (TP)– Standard type, 2 switches/transistors

• Open Collector/Open Drain (OC/OD)– Only the SW towards GND, high state from a pull-up resistor– Allow to get logic operators by wiring (WIRED LOGIC)– Used to collect multiple signaling on a single wire (interrupts)

• Three State (3-S)– L, H + high Z (open)– Require Enable command– Allow to put on the same line several outputs– Used for microcomputer buses

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Open Collector (Open Drain) output

• Output stage with a single switch (MOS or BJT) towards GND

• SW closed:Out to GND out state: L

• SW open:Out hig Z out state:depends from external circuit

• No collision

In Out

GND

Out

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Open Collector/Drain model

• The output MOS forces the low level by connecting the output to GND

L VO = 0V

• Whe the MOS is OFF, VO goes to the high level thanks to an externalpullup resistor RPU

H VO = VAL

VAL

RPU

GND

VO ≈ GNDSWL

VAL

RPU

GND

SWL VO ≈ VAL

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GND

VO

VAL

RPU

RON

SWL

OC model with Ron

• MOS switches have ON resistance

• For correct (static) operation

RON << RPU

• Strong asymmetry of the equivalent resistance Roin the H and L states


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Logic operators with O.C.

• OC outputs can be used to build logic operators

– L node is LOW if at least one among SW (A, B) is closed

• 1 any SW closed– Logic operator: NOR

out = 0 when at leastone of the inputs = 1

WIRED OR

• Application:– Interrupt request line

L

A

GND

VAL

B

RPU

In1

In2L

VAL

Storey, Electronics: A Systems Approach, 3rd Edition © Pearson Education Limited 2006A2.38

Wired-AND operation

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Totem Pole and 3-state outputs

MOSp

VAL

GND

MOSn

VO

MOSp

VAL

GND

MOSn

VO

The 3S output has twocommands, and usestwo control variables

The TP output has a single command

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3 State output model

If both switches are open,(ENABLE = 0), the output SPDT has a new state Z .With output = Z, the logicstate depends fromexternal circuits.

GND

Two SPST switches useindependent commands

VO

VAL

SWH

SWL

VO

VAL

GND

HZL


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Model for 3-S outputs with Enable

• SPDP switch (SWL , as for TP) + SPST switch (SWE) to Enable/disable the output

• The model points out the operation of the OUT ENABLE (OE) command

– The output “logic state” (H/L) depends from SWL

– The “electric state” (Active/HighZ) depends from SWE

– The Enable command can be shared by several outputs

VO

VAL

GND

SWL

SWE

OE

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Application of three-state outputs

• A control unit issues mutually exclusive enable signals (only one at a time)

– The control unit “knows” which output should be enabled

• Application examples:– Memory or register reading – Multiplexer

• Cannot be used if the pre-selection is not available

– Example: interrupt

Enablecontrol

OEi

0

1

1

OE1

In1

OE2

In2

OE3

In3

L

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Output current: state H

• A High output drives a load to GND

• Current IO < 0

• Voltage VOdepends from current IO :

VO = VAL + ROH · IO

• For correct operation VO > VOH, • To get VO > VOH, IO > IOH

IOROH

RLVAL VO

IO

VO

VOH

IOH

VALActualVO ,IO

RL

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Output current: state L

• A Low output drives a load to VPW

• Current IO < 0

• Voltage VOdepends from current IO :

VO = ROL · IO

• For correct operation VO < VOL, • To get VO < VOL, IO < IOL

IOROLRC VP

W

VO

IOVOL

IOL

VAL

ActualVO ,IO

RC


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Operating areas

For correct operation(VO external toVOL/VOH), the currentIO must be within the IOL - IOH limits

VO

IO

VOH

VOLIOH IOL

VPW

Low state

High state

Too high IO current IO < IOH IO > IOLCorrect operation

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Input and output static parameters

• VIH: maximum value of the threshold VT

– Input voltages VI > VIH are interpreted as H state

• VIL: minimum value of the threshold VT

– Input voltages VI < VIL are interpreted as L state

• VOH: high state minimum output voltage

– State H: VO > VOH, as long as |IO| < |IOH|

• VOL: low state maximum output voltage

– State L: VO < VOL, as long as |IO| < |IOL|

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Logic compatibility check

• Separate analysis for Low and High states

• Verify voltage levels compatibility– VOL < VIL; VOH > VIH

• Evaluate output currents for Low and High states adding

– Input currents of connected logic circuits IIL, IIH– Load currents

» Low state: loads connected to VPW

» High state: loads connected to GND

• Verify current compatibility– Low state: IO < IOL; high state: IO > IOH

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Dynamic parameters of signals

• Rise time and Fall time– Defined from 10% to 90% of swing

VO

100

90

10

ttf tr0

VH

VL

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Dynamic parameters of modules

• Delays from input to output (propagation time tP)– Reference level: 50% of VOH - VOL swing

VI

VO

t

t

tPHL tPLH

VOH

VOL

VOH

VOL

(VOH + VOL)/2

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From CMOS data sheet

• tr , tf tTLH , (transition time LH, HL)• The label defines the direction of change

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Origin of delays and linear model

• Delays and edge slope depends on reactive parameters (L and C)

• Actual circuit have nonlinear, II-order behavior

• Linear, I order models can be used for a first approximation analysis

• Delays among modules: tD

• Delays inside modules: tP


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Delay RC model: L H transition

VA

VB

tVOL

VOH

VAL

VT

tDLH

Thevenin network (VA, ROH) forthe output

RI CI at input

The state change(L H) is sensedwhen VB crosses VT(transmissiondelay tDLH)

RICI

B

VA VB

output input

ROH

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Delay RC model: H L transition

Thevenin network (VA=0, ROL) forthe output

RI CI at input

The state change(H L) is sensedwhen VB crosses VT(transmissiondelay tDHL)

VA

VB

tVOL

VOH

VAL

VT

tDHL

RICI

B

VB

ROL

output input

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Delay evaluation

• The state change delay tDXY

– Can be evaluated from V(t) and static electric parameters– Variable delay, depending on C, VT, and other parameters– Specs define maximum delay for a maximum capacitive load

» Minimum delay is unknown; may be assumed = 0

V

t

VOH

VOL

VT2

tDLH2

VT1

tDLH1

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R/SW output circuit

• For correct (static) operation

ROL << RPU

• Strong asymmetry of the equivalent resistance Roin the H and L states

• Strong asymmetry of the time constant Ro x C in the H and L states

C

B

VA

RPU

C

BRON


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Delays in R/SW structures

• Asymmetric waveform

– Fast H L transient (τHL = C ROL//RPU)– Slow L H transient (τLH = C RPU)

Slow L H transientτLH = C RPU

τLH >> τLùHL

Fast H L transientτHL = C ROL//RPUROL<< RPU

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GND

VO

VAL

ROH

ROL

SWH

SWL

CMOS logic output

• The equivalent output resistance Ro is:

– ROH for state H– ROL for state L

• ROL and ROH have similar values C

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OC output: asymmetric time constants

Delays for CMOS structure

• Same approach as R/SW, but now ROH ≅ ROL

– Same time constants: τLH ≅ τHL

– Symmetric transitions– Small resistors, fast transitions

tτLH = C ROH

VH

VL

τHL = C ROL

TP output: symmetric time constants

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Effect of load

• The equivalent total capacitance CT depends from the number of connected inputs:CT = sum (CI)

• With many connected inputs:– Delay and transition time go up– Transitions becomee slower

(may cause multiple state change)

• The maximum number of inputs which can be driven by a single output is limited by capacitive loading

R1ICI1

Binput

R I2CI2

ROVA

CMOS: very high input resistance


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Fan out

• The maximum number of inputs which can be connected to an output is the

FAN OUT

• Fan Out depends from– Static compatibility (max output & input currents, loads)– Dynamic compatibility (delays, rise/fall times)

• In CMOS circuits the input current is very small (II≈0) – Each input adds a parasitic capacitor– Fan out is limited by capacitive loading

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Lesson A2: final test

• Describe the specific features and benefits of digital signals.

• Explain the “compatibility” among logic circuits

• Define the noise margin

• Is it possible to measure VIH e VILfrom a single device?

• Explain the asymmetry of rise/fall times in a R-SW gate

• Which parameters influence the delays in CMOS circuits ?

DIGITAL ELECTRONICS - polito.it · 2009-04-28 · Digital Electronics - A2 28/04/2009 2009 DDC -...

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