digital elecronics lab
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7/23/2019 digital elecronics lab http://slidepdf.com/reader/full/digital-elecronics-lab 1/3 Design a synchronous counter using JK FF and external gates for the following sequence 000, 101, 110, 111, 011, 010, 000. Design a sequence generator for the following sequence 7, 5, 3, , 1 and dis!lay it. "et u! a counter to count in the following sequence, #0, , $, %, &, 1, 3, 5, 7, 13, 0... Design and set u! a 3 'it 'inary to gray and gray to 'inary code con(erter using )ode control switch. *eali+e the oolean function using $ - 1 / 2 F a, ', c4 2 0,1, 3, 5, 74 Design and set u! a 3 'it co)!arator using gates. Design a circuit to generate a sequence 0101010110101010. *e!eat this sequence 6lot sourcing and sining currents of 889 :;:D gates. ; three stage counter )ust 'e designed that will count in two different )odes de!ending on logic le(el of control line. <f control line is high the counter )ust count 0, , $, %, 0. <f the control line is low the counter )ust ount u! through all eight states.
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Transcript of digital elecronics lab
7/23/2019 digital elecronics lab
http://slidepdf.com/reader/full/digital-elecronics-lab 1/3
Design a synchronous counter using JK FF and external gates for the
following sequence 000, 101, 110, 111, 011, 010, 000.
Design a sequence generator for the following sequence 7, 5, 3, , 1 and
dis!lay it.
"et u! a counter to count in the following sequence, #0, , $, %, &, 1, 3,
5, 7, 13, 0...
Design and set u! a 3 'it 'inary to gray and gray to 'inary code
con(erter using )ode control switch.
*eali+e the oolean function using $ - 1 / 2 F a, ', c4 2 0,1, 3,
5, 74
Design and set u! a 3 'it co)!arator using gates.
Design a circuit to generate a sequence 0101010110101010. *e!eat this
sequence
6lot sourcing and sining currents of 889 :;:D gates.
; three stage counter )ust 'e designed that will count in two different
)odes de!ending on logic le(el of control line. <f control line is high the
counter )ust count 0, , $, %, 0. <f the control line is low the counter
)ust ount u! through all eight states.
7/23/2019 digital elecronics lab
http://slidepdf.com/reader/full/digital-elecronics-lab 2/3
Design and set u! an asta'le )ulti(i'rator to generate a square wa(e of
frequency 1 =+ using 7$13 <>.
"et u! a 'inary adder cu) su'stractor using ?s co)!li)ent for) using
<> 7$&3.
"et u! all 'asic logic gates using - 1 /. %. Design and set u! a
decade counter using JK fli! flo!s.
Design and set u! a $ 'it serial su'tractor.
Design and set u! a $ 'it ri!!le carry adder.
Design and set u! a )ode 10 counter.
Design and set u! a $ 'it serial adder.
@enerate a delay of 100 )s
Design and setu! a 3A'it asynchronous down counter using JK Fli!flo!.
7/23/2019 digital elecronics lab
http://slidepdf.com/reader/full/digital-elecronics-lab 3/3
Design and setu! a A'it asynchronous u!Adown counter using JK
Fli!flo!.
Design and setu! a 3A 'it synchronous u! counter using JK Fli! flo!
Design and setu! a 3A 'it synchronous u! counter using JK Fli! flo!
Design and setu! a 3A'it synchronous down counter using JK Fli! flo!.
Design and setu! a )odeA% synchronous self starting counter using JK
Fli! Flo!
