Digital Design – Physical Implementation

Digital Design – Physical Implementation

Chapter 7 - Physical Implementation

2

Digital DesignPhysical Implementation

Figure 7.1 How do we get from A to B?

BeltWarnk

s

wp

A B

Digital circuit Physicalimplementationdesign

IC

3


Figure 7.2 Custom IC design.

B e lt W a r nk

s

wpTransistorschematic

Fabmonths

IC

4


Figure 7.3 Gate array technology -- note: real gate arrays have thousands of gates, not just a few.

Be l tW a r nk

s

wp

Gate array layout w/o wires

Gate array layout w/ wires

kp

s

w

FabICweeks

(just wiring)

5


Figure 7.4 Half-adder on a gate array.

Gate array

s = a’b + ab’

ab

co

s

ab a’b ab’

6


Figure 7.5 Standard cell technology.

Be l tW a r nk

s

wp

Cell library

Standard cell layout

kps

w

FabIC1-3 months

(cells and wiring)cell row

cell row

cell row

7


Figure 7.6 Half-adder using standard cells.

co = abs = a’b + ab’

ab

cos

ab a’b

ab’

8


Figure 7.7 Implementing an AND/OR circuit using NANDs only -- half-adder sum example.

aba

b

s

aba

b

s

xx’

xx x

ba

b

s

a

=x’+y’ = (xy)’x’’ = x

9


Figure 7.8 Converting a one-level AND circuit to NAND.

a

bco

a

bco

a

bco

10


Figure 7.9 FPGA chips.

11


Figure 7.10 Implementing logic functions using a memory: (a) 2-input function truth table, (b) corresponding memory contents and

connections, (c) the proper output appears for the given input values, (d) two functions having the same two inputs, (e) memory contents for

the two functions.

x y F0 0

101 0

11

1001 a1

a0 Dxy

F

1001

4x1 Mem.

0123 a1

a0 Dx=0

y=0F=1

1001

4x1 Mem.

0123

F = x’y’ + xy F = x’y’ + xyG = xy’

x y F0 0

101 0

11

1001

G0010

a1a0 D1

xy

F

10000110

4x2 Mem.

0123

(a) (b) (c) (d) (e)G

D0

1 rd 1 rd1 rd

12


Figure 7.11 Lookup table implementation.

Be l tW a r nk

s

wp

Fab

IC1-3 months

k p w0 0

101 0

11

0000

s

00001111

0 010

1 011

0010

a1a0

kp

0000

8x1 Mem.

0123

0010

4567

s

D

w

a2 Programming(seconds)

13


Figure 7.12 Partitioning a circuit onto two lookup tables.

(a) (b) (c)

B el tW a r nk

s

wp

t

B el tW a r nk

s

wp

t

3 inputs 2 inputs 1 output 1 output

x

x=kps’ w=x+t

a1a0 D

0111

4x1 Mem.

0123

a1a0

kp

0000

8x1 Mem.

0123

0010

4567

s

D

a2

t

w

14


Figure 7.13 Partitioning a circuit onto two lookup tables. Italicized bits are unused.

(a)

(b) (c)

a1a0

00000000

8x2 Mem.

0123

0000

0001

4567D1

a2

abcde

F

D0

abc

d

e

F

abc

a1a0

00100010

8x2 Mem.

0123

00101010

4567D1

a2

D0

de F

t

t

15


Figure 7.14 Implementing a 2x4 decoder onto two 3-input 2-output lookup tables. Italicized bits are unused.

a1a0

10010000

8x2 Mem.

0123

00000000

4567D1

a2

D0

a1a0

00001001

8x2 Mem.

0123

00000000

4567D1

a2

D0

i1i0

d3d2d1d0

0 0

d0

d1

d2

d3

i0i1

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Figure 7.15 A partial FPGA that includes a switch matrix (left), and the switch matrix’s internals showing two 4x1 muxes controlled by two 2-

bit registers (right).

a1a0

00000000

8x2 Mem.

0123

00000000

4567D1

a2

D0

a1a0

00000000

8x2 Mem.

0123

00000000

4567D1

a2

D0Switchmatrix

P2P1P0

P3

P6P7

FPGA (partial) Switch matrix

m0m1m2m3

o1o0

m0m1m2m3

o0s1s04x1mux

i0i1i2i3

d

2-bit memory

o1s1s04x1mux

i0i1i2i3

d

2-bit memory

P4P5

P8P9

17


Figure 7.16 Implementing a 2x4 decoder on the partial FPGA fabric having a switch matrix.

a1a0

10010000

8x2 Mem.

0123

00000000

4567D1

a2

D0

a1a0

00001001

8x2 Mem.

0123

00000000

4567D1

a2

D0Switchmatrix

i100

i0

d3d2


m0m1m2m3

o1o0

m0m1m2m3

o0s1s04x1mux

i0i1i2i3

d

o1s1s04x1mux

i0i1i2i3

di1i0

d1d0

10

11

1011

18


Figure 7.17 Implementing the extended seatbelt warning light circuit on the partial FPGA fabric having a switch matrix. Italicized bits are

unused.

a1a0

0000

0000

8x2 Mem.

0123

0000

0100

4567D1

a2

D0

a1a0

0001

0101

8x2 Mem.

0123

00000000

4567D1

a2

D0Switchmatrix

pk0

s

w


m0m1m2m3

o1o0

m0m1m2m3

o0s1s04x1mux

i0i1i2i3

d

o1s1s04x1mux

i0i1i2i3

dt0

00

10

0010

19


Figure 7.18 An FPGA with configurable logic blocks, which contain flip-flops along with a lookup table.We’ve put 0s in all the configuration

memory bit cells in the figure.

a1a0

00000000

8x2 Mem.

0123

00000000

4567D1

a2

D0

a1a0

00000000

8x2 Mem.

0123

00000000

4567D1

a2

D0

Switchmatrix

P2P1P0

P3

P6P7

FPGA

m0m1m2m3

o1o0

P4P5

P8P9

2x1 2x1 2x1 2x1

CLB CLB

1 0 1 0

1-bitCLBoutputconfigurationmemory

0000

0 0 0 0

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Figure 7.19 Implementing a sequential circuit on an FPGA.

a1a0

11100100

8x2 Mem.

0123

00000000

4567D1

a2

D0

a1a0

00011011

8x2 Mem.

0123

00000000

4567

D1

a2

D0

Switchmatrix

a00

b

zy

FPGA

m0m1m2m3

o1o0

cd

xw

2x1 2x1 2x1 2x1

CLB CLBa b c d

w x y z

a2 a1 a0a b0

D1w=a’

D0x=b’

0

1

10 00

011

000below unused

1100

1010

1 1 1 1

Left lookup table

1011

21


Figure 7.20 FPGA architecture.

CLB

SM

CLB

SM

CLB

CLB

SM

CLB

SM

CLB

CLB CLB CLB

22


Figure 7.21 Programming an FPGA: all configuration bit cells exist in a scan chain (top); a scan chain conceptually is a big shift register

(middle); a bit file’s contents would be shifted in during programming -- some relationships between the file’s bits and configuration bit cells are

shown (bottom).

a1a0

11100101

8x2 Mem.

0123

00000000

4567D1

a2

D0

a1a0

01001110

8x2 Mem.

0123

00000000

4567

D1

a2

D0

Switchmatrix

a00

b

zy

FPGA

m0m1m2m3

o1o0

cd

xw

2x1 2x1 2x1 2x1

CLB CLB

1 1 1 1

1011

Conceptual view of configuration bit scan chainis a 40-bit shift register

Pin

Pclk

Pin

Pclk

Bit file contents for desired circuit: 1101011000000000111101010011010000000011

23


Figure 7.22 Example logic IC.

I1 I2 I3 I4 I5 I6 I7GND

I8I9I10I11I12I13I14VCC

IC

24


Figure 7.23 7400-series IC.

25


Table 7.1 Commonly-used 7400-series ICs

Part Description Pins74LS00 Four 2-input NAND 1474LS02 Four 2-input NOR 1474LS04 Six inverters 1474LS08 Four 2-input AND 1474LS10 Three 3-input NAND 1474LS11 Three 3-input AND 1474LS14 Six inverters (Schmitt trigger) 1474LS20 Two 4-input NAND 1474LS27 Three 3-input NOR 1474LS30 One 8-input NAND 1474LS32 Four 2-input OR 1474LS74 Two D flip-flop, positive edge triggered, with preset and reset 1474LS83 4-bit binary full-adder 1674LS85 4-bit magnitude comparator 16

26


Figure 7.24 Implementing the seat-belt warning circuit with 74LS series ICs.

k

s

wp

I1 I2 I3 I4 I5 I6 I7

I8I9I10I11I12I13I14

74LS08 IC

k

s

wp

I1 I2 I3 I4 I5 I6 I7

I8I9I10I11I12I13I14

74LS04 ICs

p

k

n

nw

(a)

(b) (c)

27


Figure 7.25 Implementing the seat-belt warning circuit with one 74LS IC, namely the 74LS27 consisting of three 3-input NOR gates.

k

s

wp

I1 I2 I3 I4 I5 I6 I7

I8I9I10I11I12I13I14

74LS27 IC

s

p

k

w(a)

(b) (c)

k

s

wp0

28


Figure 7.26 A basic example of a programmable logic device. (AND gates are wired-AND).

I1 I2 I3

O1

PLD IC

programmable nodes

29


Figure 7.27 Two types of programmable nodes: (top) fuse based, (bottom) memory based.

Fuse“unblown” fuse “blown” fuse

programmable node

mem1

mem0

30


Figure 7.28 Simplified PLD drawing.

O1

PLD IC

I1 I2 I3

I3*I2’wired AND

31


Figure 7.29 Seat-belt warning system on a simple PLD.

w

PLD IC

k p s

kps’

0

0

32

O1

PLD IC

I1 I2 I3

O2

O1

PLD IC

I1 I2 I3(a) (b)

FF

2x1

programmable bit

O2

FF

2x1

clk


Figure 7.30 (a) PLD with two outputs, (b) PLD with programmable registered outputs.

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Table 7.2 Sample % of new implementations in various technologies. Total is more than 100% due to overlap among categories. Source:

Synopsys, DAC 2002 panel.

Technology %Standard cell 55%Gate array 5%System-on-a-Chip 30%Full-custom 10%CPLD/FPGA 10%Other 5%

Digital Design – Physical Implementation

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