DesignSimulationSynthesisDFTVerification

1. ObjectivesThis presentation main objective is to inform the audience about Digital Design Flow that is now implemented on ETTI servers how can this tools be used on a real design situation.It was considered that the best way to present the tools is by taking a design example and run it through all the flow steps available at this moment.For this purpose the microcontroller 8051 was chosen, because for this IP the architecture is relatively simple, wide known and available for free at many sites.

2. Design specs*Fully synchronous design Easily expandable by adapting/changing VHDL source code Parametrizeable design by simply changing VHDL constants User selectable number (N) of timers/counters and serial interface units Active timer/counter and serial interface units selected by additional SFRInstruction set compatible to the industry standard 8051 microcontroller Up to 10 times faster due to completely new architecture Optional implementation of the multiply command (MUL) using a parallel multiplier Optional implementation of the divide command (DIV) using a parallel divider Optional implementation of the decimal adjustment command (DA) No multiplexed I/O ports 256 bytes internal RAM Up to 64 kbyte ROM, up to 64 kbyte RAM*http://www.oreganosystems.at/download/mc8051_design.zip

2. Design specsBlock diagram IP core

2. Design specsDesign hierarchy of the IP core

3. SimulationThe easiest way to test the design is to write some assembler code, load it into the ROM, then run in on the IP and check if the result are the expected ones.For this to be accomplished Keil uVision 4 assembler program was used to generate the hexadecimal code from the mnemonics written and then using some additional software we were able to load the code into the ROM.For the simulation part, we used ModelSim SE 10.1b, 64bits version.To begin with, lets consider the following simple assembler code:

clr A setb C rrc A again: rr A jmp again endWhat the code does?Step 1. clears the accumulator registerStep 2. sets the carry bitStep 3. rotates to right the accumulator register using the previous set carry bitStep 4. rotates to right the accumulator registerStep 5. jumps to step 4.

3. Simulation clr A setb C rrc A again: rr A jmp again endWhat the code does?Step 1. clear the accumulator registerStep 2. set the carry bitStep 3. rotate to right the accumulator register using the previous set carry bitStep 4. rotate to right the accumulator registerStep 5. jump to step 4. :06000000E4D3130380FDB0:00000001FFHex format code111001001101001100010011000000111000000011111101Binary code to load to ROM

3. Simulation clr A setb C rrc A again: rr A jmp again end

3. SimulationLets consider a more complex example. This short program counts the number of ones from a given value found in accumulator register (here 71H 01110001B) storing the result in R3 register (should be 4).

mov A, #71H mov R3, #0again: clr C rrc A jnc skip inc R3skip: jnz again jmp $ endHow?Step 1. load the accumulator register with 71HStep 2. load the R3 with 0 (no one found)Step 3. clear carry bit Step 4. rotate to right the accumulator register using the carry registerStep 5. if the carry bit is not set it jumps to skip and from there back to step 3, otherwise first increment R3 register (a 1 bit was found) and from there back to step 4:0D00000074717B00C31350010B70F980FE7A:00000001FFHex format code0111010001110001...Binary code to load to ROM

3. Simulation mov A, #71H mov R3, #0again: clr C rrc A jnc skip inc R3skip: jnz again jmp $ end71H 01110001B

4. SynthesisFor the synthesis part Leonardo Spectrum Level 3 - 2011a.4 was used. Also for this example a 350nm technology was used.The initial synthesis script:

# This is the synthesis script for the 8051 microcontroller in TCL

load_library $env(PDK_DIR)/leospec/c35_CORELIB.syn

set design_name mc8051_core

set design_files {mc8051_pcontrol_fsm_control_fsm_rtlcontrol_mem_control_mem_rtlmc8051_control_mc8051_control_strucalucore_alucore_rtlalumux_alumux_rtladdsub_cy_addsub_cy_rtladdsub_ovcy_addsub_ovcy_rtladdsub_core_...}

4. SynthesisThe initial synthesis script:

foreach src_file $design_files { analyze src/$src_file.vhd }

elaborate $design_name

ungroup -all -hierarchy

set_attribute -port clk -name clock_cycle -value 100.0 set_attribute -port clk -name pulse_width -value 50.0 set_attribute -port clk -name clock_offset -value 0.0

optimize -macro -area -effort standard

write netlists/$design_name.v

# Generate reports report_area -cell_usage reports/${design_name}_area.txtreport_delay -clock_frequency -critical_paths -num_paths 3 reports/${design_name}_delay.txt

4. SynthesisThe initial synthesis area report:

Number of ports : 156 Number of nets : 5218 Number of instances : 4852 Number of references to this view : 0

Total accumulated area : Number of gates : 507780 Number of accumulated instances : 4852 Clock Frequency Report

Clock : Frequency ------------------------------------

clk : 16.6 MHz

Critical Path Report

Critical path #1, (path slack = 39.7)Critical path #2, (path slack = 39.7)Critical path #3, (path slack = 39.7)The initial synthesis delay report:

4. SynthesisIt was desired for the design to work at a higher frequency so we modified the script regarding the constrains for the clock signal (25MHz operating frequency) and the optimization of the design for timing.

set_attribute -port clk -name clock_cycle -value 40.0 set_attribute -port clk -name pulse_width -value 20.0 set_attribute -port clk -name clock_offset -value 0.0

optimize -macro -delay -effort standard optimize_timing

Clock Frequency Report

Clock : Frequency ------------------------------------

clk : 25.7 MHz

Critical Path Report

Critical path #1, (path slack = 1.2)Critical path #2, (path slack = 1.3)Critical path #3, (path slack = 1.3)The optimized synthesis delay report:

4. SynthesisFurther more:

set_attribute -port clk -name clock_cycle -value 20.0 set_attribute -port clk -name pulse_width -value 10.0 set_attribute -port clk -name clock_offset -value 0.0

optimize -macro -delay -effort standard optimize_timingSTILL RUNNING...The optimized synthesis delay report:

5. DFT