Digital Design: An Embedded Systems Approach Using...

Digital Design:An Embedded Systems Approach Using Verilog

Chapter 4

Sequential Basics

Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using Verilog, by Peter J. Ashenden, published by Morgan

Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.

Verilog

Digital Design — Chapter 4 — Sequential Basics 2

Sequential Basics

� Sequential circuits

� Outputs depend on current inputs and

previous inputs

� Store state: an abstraction of the history of inputs

� Usually governed by a periodic clock signal

Verilog


D-Flipflops

� 1-bit storage element

� We will treat it as a basic component

� Other kinds of flipflops

� SR (set/reset), JK, T (toggle)

D Q

clkD

clk

Q

Verilog


Registers

� Store a multi-bit encoded value� One D-flipflop per bit

� Stores a new value oneach clock cycle

wirewirewirewire [n:0] d;regregregreg [n:0] q;...

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk)q <= d;

event list

nonblocking asignment

D Q

clk

D Q

clk

D Q

clk

d(0)

…… …

d(1)

d(n)

n n

q(0)

q(1)

q(n)

clk

D Q

clk

Verilog


Pipelines Using Registers

Total delay = Delay1 + Delay2 + Delay3

Interval between outputs > Total delay

Clock period = max(Delay1, Delay2, Delay3)

Total delay = 3 × clock period

Interval between outputs = 1 clock period

D Q

clk

combin-

ational

circuit 1

D Q

clk

combin-

ational

circuit 2

D Q

clk

combin-

ational

circuit 3

d_in

clk

d_out

combin-

ational

circuit 1

combin-

ational

circuit 2

combin-

ational

circuit 3d_in d_out

Verilog


Pipeline Example

� Compute the average of corresponding numbers in three input streams

� New values arrive on each clock edge

modulemodulemodulemodule average_pipeline ( outputoutputoutputoutput regregregreg signedsignedsignedsigned [5:-8] avg,inputinputinputinput signedsignedsignedsigned [5:-8] a, b, c,inputinputinputinput clk );

wirewirewirewire signedsignedsignedsigned [5:-8] a_plus_b, sum, sum_div_3;regregregreg signedsignedsignedsigned [5:-8] saved_a_plus_b, saved_c, saved_sum;...

Verilog


Pipeline Example

...

assignassignassignassign a_plus_b = a + b;

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk) beginbeginbeginbegin // Pipeline register 1saved_a_plus_b <= a_plus_b;saved_c <= c;

endendendend

assignassignassignassign sum = saved_a_plus_b + saved_c;

alwaysalwaysalwaysalways @(posedge clk) // Pipeline register 2saved_sum <= sum;

assignassignassignassign sum_div_3 = saved_sum * 14'b00000001010101;

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk) // Pipeline register 3avg <= sum_div_3;

endmoduleendmoduleendmoduleendmodule

Verilog


D-Flipflop with Enable

� Storage controlled by a clock-enable

� stores only when CE = 1 on a rising edge

of the clock

� CE is a synchronous control input

D

CE

Q

clk D

CE

clk

Q

Verilog


Register with Enable

� One flipflop per bit

� clk and CE wired in common

wirewirewirewire [n:0] d;wirewirewirewire ce;regregregreg [n:0] q;...

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk)ifififif (ce) q <= d;

Verilog


Register with Synchronous Reset

� Reset input forces stored value to 0

� reset input must be stable around rising

edge of clk

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk)ifififif (reset) q <= 0;elseelseelseelse ifififif (ce) q <= d;

D

CE

Q

clk

resetD

CE

reset

clk

Q

1 2 3 4 5 6 7 8

Verilog


Register with Asynchronous Reset

� Reset input forces stored value to 0

� reset can become 1 at any time, and effect

is immediate

� reset should return to 0 synchronously

D

CE

Q

clk

reset

D

CE

reset

clk

Q

1 2 3 4 5 6 7 8

Verilog


Asynch Reset in Verilog

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk orororor posedgeposedgeposedgeposedge reset)ifififif (reset) q <= 0;elseelseelseelse ifififif (ce) q <= d;

� reset is an asynchronous control input here

� include it in the event list so that the process responds to changes immediately

Verilog


Example: Accumulator

� Sum a sequence of signed numbers

� A new number arrives when data_en = 1

� Clear sum to 0 on synch reset

modulemodulemodulemodule accumulator( outputoutputoutputoutput regregregreg signedsignedsignedsigned [7:-12] data_out,

inputinputinputinput signedsignedsignedsigned [3:-12] data_in,inputinputinputinput data_en, clk, reset );

wirewirewirewire signedsignedsignedsigned [7:-12] new_sum;

assignassignassignassign new_sum = data_out + data_in;

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk)ifififif (resetresetresetreset) data_out <= 20'b0;elseelseelseelse if (data_endata_endata_endata_en) data_out <= new_sum;


Verilog


Flipflop and Register Variations

modulemodulemodulemodule flip_flop_n ( outputoutputoutputoutput regregregreg Q,outputoutputoutputoutput Q_n,inputinputinputinput pre_n, clr_n, D,inputinputinputinput clk_n, CE );

alwaysalwaysalwaysalways @( negedgenegedgenegedgenegedge clk_n orororornegedgenegedgenegedgenegedge pre_n orororor negedge clr_n ) beginbeginbeginbegin

ifififif ( !pre_n && !clr_n)$display("Illegal inputs: pre_n and clr_n both 0");

ifififif (!pre_n) Q <= 1'b1;elseelseelseelse ifififif (!clr_n) Q <= 1'b0;elseelseelseelse ifififif (CE) Q <= D;

endendendend

assignassignassignassign Q_n = ~Q;


D

CE

Q

Qclk

pre

clr

Verilog


Shift Registers

� Performs shift operation on stored data

� Arithmetic scaling

� Serial transfer

of data

D

D_in

CE

load_en

Q

clk

D

CE

Q

clk

0

1

D

CE

Q

clk

0

1

D

CE

Q

clk

0

1

Q(n–1)

Q(n–2)

Q(0)

D(n–1)

D(n–2)

D(0)

clkCE

load_en

D_in

Verilog


Example: Sequential Multiplier

� 16×16 multiply over 16 clock cycles, using one adder� Shift register for multiplier bits

� Shift register for lsb’s of accumulated product

17-bit reg

reset

CE

D Q

clk

D

16-bit reg

CE

Q

clk

D_in

15-bitshift reg

CE

Q

clk

16-bitshift reg

D_in

D

CE

load_en

Q

clk x

16-bitadder

c0

y

c16

s15...0

1615

031...16

P(14...0)

P(31...15)

y(15...0)

x(15...0)

y_load_eny_ce

x_ce

P_resetP_ceclk

Verilog


Latches

� Level-sensitive storage

� Data transmitted while enable is '1'

� transparent latch

� Data stored while enable is '0'

D Q

LE

D

LE

Q

Verilog


Feedback Latches

� Feedback in gate circuits produces latching behavior

� Example: reset/set (RS) latch

S

R

Q

� Current RTL synthesis tools don’t accept Verilog models with unclocked feedback

+V

Q

Q

R

S

Verilog


Latches in Verilog

� Latching behavior is usually an error!

alwaysalwaysalwaysalways @*ifififif (~sel) beginbeginbeginbegin

z1 <= a1; z2 <= b1;endendendendelseelseelseelse beginbeginbeginbegin

z1 <= a2; z3 <= b2;endendendend

Oops!Should bez2 <= ...

� Values must be stored

� for z2 while sel = 1

� for z3 while sel = 0

Verilog


Counters

� Stores an unsigned integer value

� increments or decrements the value

� Used to count occurrences of

� events

� repetitions of a processing step

� Used as timers

� count elapsed time intervals by

incrementing periodically

Verilog


Free-Running Counter

� Increments every rising edge of clk

� up to 2n–1, then wraps back to 0

� i.e., counts modulo 2n

� This counter is synchronous� all outputs governed by clock edge

D Q

clk

+1 Q

clk

Verilog


Example: Periodic Control Signal

� Count modulo 16 clock cycles

� Control output = 1 every 8th and 12th cycle

� decode count values 0111 and 1011

+1

clk

ctrl

0

1

2

3

0

1

2

3

D Q

clk

D Q

clk

D Q

clk

D Q

clk

Verilog


Example: Periodic Control Signal

modulemodulemodulemodule decoded_counter ( outputoutputoutputoutput ctrl,inputinputinputinput clk );

regregregreg [3:0] count_value;

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk)count_value <= count_value + 1;

assignassignassignassign ctrl = count_value == 4'b0111 ||count_value == 4'b1011;


Verilog


Count Enable and Reset

� Use a register with control inputs

� Increments when CE = 1 on rising clock edge

� Reset: synch or asynch

+1Q

clk

CE

reset

clk

D

CE

Q

reset

Verilog


Terminal Count

� Status signal indicating final count value

� TC is 1 for one cycle in every 2n cycles

� frequency = clock frequency / 2n

� Called a clock divider

counter

… …

Q0

Q1

Qnclk

… TC

Verilog


Divider Example

� Alarm clock beep: 500Hz from 1MHz clock

count

tone2tone

clk

10-bitcounter

Q

TCclk

D

CE

Q

clk

tone

tone2

count

clk

1 100 2 2 10 2 10

1023 1023 1023

Verilog


Divide by k

� Decode k–1 as terminal count and reset

counter register

� Counter increments modulo k

� Example: decade counter

� Terminal count = 9

clk Q0Q1Q2Q3

Q0

Q1

Q2

Q3

clk

reset

counter

Verilog


Decade Counter in Verilog

modulemodulemodulemodule decade_counter ( outputoutputoutputoutput regregregreg [3:0] q,inputinputinputinput clk );

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk)q <= q == 9 ? 0 : q + 1;


Verilog


Down Counter with Load

� Load a starting value, then decrement

� Terminal count = 0

� Useful for interval timer

D Q

clk

–1

=0?

Q

TC

clkload

D

0

1

Verilog


Loadable Counter in Verilog

modulemodulemodulemodule interval_timer_rtl ( outputoutputoutputoutput tc,inputinputinputinput [9:0] data,inputinputinputinput load, clk );

regregregreg [9:0] count_value;

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk)ifififif (load) count_value <= data;elseelseelseelse count_value <= count_value - 1;

assignassignassignassign tc = count_value == 0;


Verilog


Reloading Counter in Verilog

modulemodulemodulemodule interval_timer_repetitive ( outputoutputoutputoutput tc,inputinputinputinput [9:0] data,inputinputinputinput load, clk );

regregregreg [9:0] load_value, count_value;

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk)ifififif (load) beginbeginbeginbeginload_value <= data;count_value <= data;

endendendendelseelseelseelse ifififif (count_value == 0)count_value <= load_value;

elseelseelseelsecount_value <= count_value - 1;

assignassignassignassign tc = count_value == 0;


Verilog


Ripple Counter

� Each bit toggles between 0 and 1

� when previous bit changes from 1 to 0D

Q

Q

clk

D

Q

Q

clk

D

Q

Q

clk

D

Q

Q

clk

Q0

Q1

Q2

Qn

clk

Q1

Q0

Q0

clk

Q1

Q2

Q2

Verilog


Ripple or Synch Counter?

� Ripple counter is ok if

� length is short

� clock period long relative to flipflop delay

� transient wrong values can be tolerated

� area must be minimal

� E.g., alarm clock

� Otherwise use a synchronous counter

Verilog


Datapaths and Control

� Digital systems perform sequences of operations on encoded data

� Datapath� Combinational circuits for operations

� Registers for storing intermediate results

� Control section: control sequencing� Generates control signals

� Selecting operations to perform

� Enabling registers at the right times

� Uses status signals from datapath

Verilog


Example: Complex Multiplier

� Cartesian form, fixed-point

� operands: 4 pre-, 12 post-binary-point bits

� result: 8 pre-, 24 post-binary-point bits

� Subject to tight area constraints

ir jaaa += ir jbbb +=

)()( riiriirrir babajbabajppabp ++−=+==

� 4 multiplies, 1 add, 1 subtract

� Perform sequentially using 1 multiplier, 1

adder/subtracter

Verilog


Complex Multiplier Datapath

0

1

0

1

D

CE

Q

clk

D

CE

Q

clk

× ±

D

CE

Q

clk

D

CE

Q

clk

p_r

p_i

a_r

a_i

b_r

b_i

a_sel

b_selpp1_cepp2_ce

subp_r_cep_i_ce

clk

Verilog


Complex Multiplier in Verilog

modulemodulemodulemodule multiplier( outputoutputoutputoutput regregregreg signedsignedsignedsigned [7:-24] p_r, p_i,

inputinputinputinput signedsignedsignedsigned [3:-12] a_r, a_i, b_r, b_i,inputinputinputinput clk, reset, input_rdy );

regregregreg a_sel, b_sel, pp1_ce, pp2_ce, sub, p_r_ce, p_i_ce;

wirewirewirewire signedsignedsignedsigned [3:-12] a_operand, b_operand;wirewirewirewire signedsignedsignedsigned [7:-24] pp, sumregregregreg signedsignedsignedsigned [7:-24] pp1, pp2;

...

Verilog


Complex Multiplier in Verilog

assignassignassignassign a_operand = ~a_sel ? a_r : a_i;assignassignassignassign b_operand = ~b_sel ? b_r : b_i;

assignassignassignassign pp = {{4{a_operand[3]}}, a_operand, 12'b0} *

{{4{b_operand[3]}}, b_operand, 12'b0};

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk) // Partial product 1 register

ifififif (pp1_ce) pp1 <= pp;

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk) // Partial product 2 registerifififif (pp2_ce) pp2 <= pp;

assignassignassignassign sum = ~sub ? pp1 + pp2 : pp1 - pp2;

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk) // Product real-part registerifififif (p_r_ce) p_r <= sum;

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk) // Product imaginary-part registerifififif (p_i_ce) p_i <= sum;

...

endmodule

Verilog


Multiplier Control Sequence

� Avoid resource conflict

� First attempt1. a_r * b_r → pp1_reg

2. a_i * b_i → pp2_reg

3. pp1 – pp2 → p_r_reg

4. a_r * b_i → pp1_reg

5. a_i * b_r → pp2_reg

6. pp1 + pp2 → p_i_reg

� Takes 6 clock cycles

Verilog


Multiplier Control Sequence

� Merge steps where no resource conflict

� Revised attempt

1. a_r * b_r → pp1_reg

2. a_i * b_i → pp2_reg

3. pp1 – pp2 → p_r_reg

a_r * b_i → pp1_reg

4. a_i * b_r → pp2_reg

5. pp1 + pp2 → p_i_reg

� Takes 5 clock cycles

Verilog


Multiplier Control Signals

Step a_sel b_sel pp1_ce pp2_ce sub p_r_ce p_i_ce

1 0 0 1 0 – 0 0

2 1 1 0 1 – 0 0

3 0 1 1 0 1 1 0

4 1 0 0 1 – 0 0

5 – – 0 0 0 0 1

Verilog


Finite-State Machines

� Used the implement control sequencing

� Based on mathematical automaton theory

� A FSM is defined by

� set of inputs: Σ

� set of outputs: Γ

� set of states: S

� initial state: s0 ∈ S

� transition function: δ: S × Σ → S

� output function: ω: S × Σ → Γ or ω: S → Γ

Verilog


FSM in Hardware

� Mealy FSM: ω: S × Σ → Γ

� Moore FSM: ω: S → Γ

Mealy FSM only

D

reset

Q

clk

current_state

outputsinputs

clk

reset

nextstatelogic

outputlogic

Verilog


FSM Example: Multiplier Control

� One state per step

� Separate idle state?

� Wait for input_rdy = 1

� Then proceed to steps 1, 2, ...

� But this wastes a cycle!

� Use step 1 as idle state

� Repeat step 1 if input_rdy ≠ 1

� Proceed to step 2 otherwise

� Output function� Defined by table on slide 43

� Moore or Mealy?

current_state

input_rdy

next_state

step1 0 step1

step1 1 step2

step2 – step3

step3 – step4

step4 – step5

step5 – step1

Transition function

Verilog


State Encoding

� Encoded in binary

� N states: use at least log2N bits

� Encoded value used in circuits for transition and output function

� encoding affects circuit complexity

� Optimal encoding is hard to find

� CAD tools can do this well

� One-hot works well in FPGAs

� Often use 000...0 for idle state

� reset state register to idle

Verilog


FSMs in Verilog

� Use parameters for state values

� Synthesis tool can choose an alternative

encoding

parameterparameterparameterparameter [2:0] step1 = 3'b000, step2 = 3'b001,step3 = 3'b010, step4 = 3'b011,

step5 = 3'b100;

regregregreg [2:0] current_state, next_state ;

...

Verilog


Multiplier Control in Verilog

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk orororor posedgeposedgeposedgeposedge reset) // State registerifififif (reset) current_state <= step1;elseelseelseelse current_state <= next_state;

alwaysalwaysalwaysalways @* // Next-state logiccasecasecasecase (current_state)step1: ifififif (!input_rdy) next_state = step1;

elseelseelseelse next_state = step2;step2: next_state = step3;step3: next_state = step4;step4: next_state = step5;step5: next_state = step1;

endcaseendcaseendcaseendcase

Verilog


Multiplier Control in Verilog

alwaysalwaysalwaysalways @* beginbeginbeginbegin // Output_logica_sel = 1'b0; b_sel = 1'b0; pp1_ce = 1'b0; pp2_ce = 1'b0;sub = 1'b0; p_r_ce = 1'b0; p_i_ce = 1'b0;casecasecasecase (current_state)step1: beginbeginbeginbegin

pp1_ce = 1'b1;endendendend

step2: beginbeginbeginbegina_sel = 1'b1; b_sel = 1'b1; pp2_ce = 1'b1;

endendendendstep3: beginbeginbeginbegin

b_sel = 1'b1; pp1_ce = 1'b1;sub = 1'b1; p_r_ce = 1'b1;

endendendendstep4: beginbeginbeginbegin

a_sel = 1'b1; pp2_ce = 1'b1;endendendend

step5: beginbeginbeginbeginp_i_ce = 1'b1;

endendendendendcaseendcaseendcaseendcase

endendendend

Verilog


State Transition Diagrams

� Bubbles to represent states

� Arcs to represent transitions

� Example

� S = {s1, s2, s3}

� Inputs (a1, a2):Σ = {(0,0), (0,1), (1,0), (1,1)}

� δ defined by diagram

s1 s2

s3

0, 0

0, 0

0, 1

1, 0

0, 1

1, 0

1, 1

1, 1

Verilog


State Transition Diagrams

� Annotate diagram to define output

function

� Annotate states for Moore-style outputs

� Annotate arcs for Mealy-style outputs

� Example

� x1, x2: Moore-style

� y1, y2, y3: Mealy-style

s1 s2

s3

0, 0 / 0, 0, 0

1, 0 0, 0

0, 1

0, 0 / 0, 0, 0

0, 1 / 0, 1, 1

/ 0, 1, 1

1, 0 / 1, 0, 0

0, 1 / 0, 1, 1

1, 0 / 1, 0, 0

1, 1 / 1, 1, 1

1, 1 / 1, 1, 1

Verilog


Multiplier Control Diagram

� Input: input_rdy

� Outputs

� a_sel, b_sel, pp1_ce, pp2_ce, sub, p_r_ce, p_i_ce

step10, 0, 1, 0, –, 0, 0

01 step2

1, 1, 0, 1, –, 0, 0

step41, 0, 0, 1, –, 0, 0

step5–, –, 0, 0, 0, 0, 1

step30, 1, 1, 0, 1, 1, 0

Verilog


Bubble Diagrams or Verilog?

� Many CAD tools provide editors for bubble diagrams

� Automatically generate Verilog for

simulation and synthesis

� Diagrams are visually appealing

� but can become unwieldy for complex

FSMs

� Your choice...

� or your manager's!

Verilog


Register Transfer Level

� RTL — a level of abstraction

� data stored in registers

� transferred via circuits that operate on

data

control section

outputsinputs

Verilog


Clocked Synchronous Timing

� Registers driven by a common clock

� Combinational circuits operate during clock

cycles (between rising clock edges)

tco + tpd + tsu < tc

Q1 D2tpdt

cotsu

Q1

clk

D2

tco

tc

tpd

tsu

tslack

Verilog


Control Path Timing

tco + tpd-s + tpd-o + tpd-c + tsu < tc

tco + tpd-s + tpd-ns + tsu < tc

Ignore tpd-s for a Moore FSM

tpd-s

tpd-c

tpd-o

tpd-ns

tco

tsu

tsu

Verilog


Timing Constraints

� Inequalities must hold for all paths

� If tco and tsu the same for all paths

� Combinational delays make the difference

� Critical path� The combinational path between registers with

the longest delay

� Determines minimum clock period for the entire system

� Focus on it to improve performance

� Reducing delay may make another path critical

Verilog


Interpretation of Constraints

1. Clock period depends on delays� System can operate at any frequency up

to a maximum

� OK for systems where high performance is not the main requirement

2. Delays must fit within a target clock period� Optimize critical paths to reduce delays if

necessary

� May require revising RTL organization

Verilog


Clock Skew

� Need to ensure clock edges arrive at all registers at the same time

� Use CAD tools to insert clock buffers and

route clock signal paths

Q1 D2Q1

clk1

clk2

D2

th

Verilog


Off-Chip Connections

� Delays going off-chip and inter-chip

� Input and output pad delays, wire delays

� Same timing rules apply

� Use input and output registers to avoid

adding external delay to critical path

Q1 D2

Verilog


Asynchronous Inputs

� External inputs can change at any time

� Might violate setup/hold time constraints

� Can induce metastable state in a flipflop

� Unbounded time to recover

� May violate setup/hold time

of subsequent flipflop21

2

ffk

eMTBF

f

tk

=

02>>k

0 1 0 1

Verilog


Synchronizers

� If input changes outside setup/hold window

� Change is simply delayed by one cycle

� If input changes during setup/hold window

� First flipflop has a whole cycle to resolve metastability

� See data sheets for metastability parameters

D Q

clk

D Q

clk

clk

asynch_insynch_in

Verilog


Switch Inputs and Debouncing

� Switches and push-buttons suffer from contact bounce

� Takes up to 10ms to settle

� Need to debounce to avoid false triggering

� Requires two inputs and two resistors

� Must use a break-before-make double-

throw switchQ

R

S

+V

Verilog


Switch Inputs and Debouncing

� Alternative� Use a single-throw switch

� Sample input at intervals longer than bounce time

� Look for two successive samples with the same value

� Assumption

� Extra circuitry inside the chip is cheaper than extra components and connections outside

+V

Verilog


Debouncing in Verilog

modulemodulemodulemodule debouncer ( outputoutputoutputoutput reg pb_debounced,inputinputinputinput pb,

inputinputinputinput clk, reset );

regregregreg [18:0] count500000; // values are in the range 0 to 499999wirewirewirewire clk_100Hz;regregregreg pb_sampled;

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk orororor posedgeposedgeposedgeposedge reset)ifififif (reset) count500000 <= 499999;elseelseelseelse ifififif (clk_100Hz) count500000 <= 499999;elseelseelseelse count500000 <= count500000 - 1;

assignassignassignassign clk_100Hz = count500000 == 0;

alwaysalwaysalwaysalways @(posedgeposedgeposedgeposedge clk)

ifififif (clk_100Hz) beginbeginbeginbeginifififif (pb == pb_sampled) pb_debounced <= pb;pb_sampled <= pb;

endendendend


Verilog


Verifying Sequential Circuits

� DUV may take multiple and varying number of cycles to produce output

� Checker needs to� synchronize with test generator� ensure DUV outputs occur when expected� ensure DUV outputs are correct� ensure no spurious outputs occur

Design UnderVerification

(DUV)

ApplyTest Cases Checker

Verification Testbench

Verilog


Example: Multiplier Testbench

`timescale 1ns/1ns

modulemodulemodulemodule multiplier_testbench;

parameterparameterparameterparameter t_c = 50;

regregregreg clk, reset;regregregreg input_rdy;wirewirewirewire signedsignedsignedsigned [3:-12] a_r, a_i, b_r, b_i;wirewirewirewire signedsignedsignedsigned [7:-24] p_r, p_i;

realrealrealreal real_a_r, real_a_i, real_b_r, real_b_i,real_p_r, real_p_i, err_p_r, err_p_i;

tasktasktasktask apply_test ( inputinputinputinput realrealrealreal a_r_test, a_i_test,b_r_test, b_i_test );

beginbeginbeginbeginreal_a_r = a_r_test; real_a_i = a_i_test;real_b_r = b_r_test; real_b_i = b_i_test;input_rdy = 1'b1;@(negedgenegedgenegedgenegedge clk) input_rdy = 1'b0;repeatrepeatrepeatrepeat (5) @(negedge clk);

endendendendendtaskendtaskendtaskendtask

Verilog



multiplier duv ( .clk(clk), .reset(reset),.input_rdy(input_rdy),.a_r(a_r), .a_i(a_i),.b_r(b_r), .b_i(b_i),.p_r(p_r), .p_i(p_i) );

alwaysalwaysalwaysalways beginbeginbeginbegin // Clock generator#(t_c/2) clk = 1'b1;#(t_c/2) clk = 1'b0;

endendendend

initialinitialinitialinitial beginbeginbeginbegin // Reset generatorreset <= 1'b1;#(2*t_c) reset = 1'b0;

endendendend

Verilog



initialinitialinitialinitial beginbeginbeginbegin // Apply test cases@(negedgenegedgenegedgenegedge reset)@(negedgenegedgenegedgenegedge clk)apply_test(0.0, 0.0, 1.0, 2.0);apply_test(1.0, 1.0, 1.0, 1.0);// further test cases ...$finish;

endendendend

assignassignassignassign a_r = $rtoi(real_a_r * 2**12);assignassignassignassign a_i = $rtoi(real_a_i * 2**12);assignassignassignassign b_r = $rtoi(real_b_r * 2**12);assignassignassignassign b_i = $rtoi(real_b_i * 2**12);

Verilog



alwaysalwaysalwaysalways @(posedge clk) // Check outputsifififif (input_rdy) beginbeginbeginbeginreal_p_r = real_a_r * real_b_r - real_a_i * real_b_i;real_p_i = real_a_r * real_b_i + real_a_i * real_b_r;repeatrepeatrepeatrepeat (5) @(negedge clk);err_p_r = $itor(p_r)/2**(-24) - real_p_r;err_p_i = $itor(p_i)/2**(-24) - real_p_i;ifififif (!( -(2.0**(-12)) < err_p_r && err_p_r < 2.0**(-12) &&

-(2.0**(-12)) < err_p_i && err_p_i < 2.0**(-12) ))$display("Result precision requirement not met");

endendendend


Verilog


Asynchronous Timing

� Clocked synchronous timing requires� global clock distribution with minimal skew

� path delay between registers < clock period

� Hard to achieve in complex multi-GHz systems

� Globally asynch, local synch (GALS) systems� Divide the systems into local clock domains

� Inter-domain signals treated as asynch inputs

� Simplifies clock managements and constraints

� Delays inter-domain communication

� Delay-insensitive asynchronous systems� no clock signals

Verilog


Other Clock-Related Issues

� Inter-chip clocking

� Distributing high-speed clocks on PCBs is hard

� Often use slower off-chip clock, with on-chip clock a multiple of off-chip clock

� Synchronize on-chip with phase-locked loop (PLL)

� In multi-PCB systems

� treat off-PCB signals as asynch inputs

� Low power design

� Continuous clocking wastes power

� Clock gating: turn off clock to idle subsystems

Verilog


Summary

� Registers for storing data

� synchronous and asynchronous control

� clock enable, reset, preset

� Latches: level-sensitive

� usually unintentional in Verilog

� Counters

� free-running dividers, terminal count,

reset, load, up/down

Verilog


Summary

� RTL organization of digital systems

� datapath and control section

� Finite-State Machine (FSM)

� states, inputs, transition/output functions

� Moore and Mealy FSMs

� bubble diagrams

� Clocked synch timing and constraints

� critical path and optimization

� Asynch inputs, switch debouncing

� Verification of sequential systems

Digital Design: An Embedded Systems Approach Using...

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