Digital Control of Electric Drives - O...

Czech Technical University in Prague – Faculty of Electrical Engineering

Digital Control of Electric Drives

Ver.1.01

Digital Signal Processor

J. Zdenek 2017

BE1M14DEP Digital Control of Electric Drives - 12 2

“Von Neumann“ Architecture Type (Not in DSP/DSC)

CPU Program

Memory

Data

Memory

I/O

ChannelsWorld

Input

Output

Common

Bus


“Harvard“ Architecture Type

Different Bus Width Possible


Modified “Harvard“ Architecture Type

Constants Read from Flash

Parallel Data Read/Write


“Von Neumann“ versus “Harvard“ Architecture

• “Von Neumann“

• Simpler structure• Shared instruction/data bus –

instruction/data parallel transport impossible

• Common instruction/data address space. Efficient memory partition possible (instruction/data/ stack)(required execution from RAM only).

• Sufficient stack area (stack depth) available.

• “Harvard“

• More complex structure• Separated instruction/data busses

– instruction/data parallel transport possible (higher computer speed)

• Separated instruction/data address spaces. Program memory (instructions) usually wider than data memory – compact one cycle instruction codes.

• Stack often outside of data memory (different width of program and data memory). Stack depth limited (hw stack on CPU) –if stack depth insufficient – stack data dumping to data memory necessary - slow)


Interrupt Service Cycle


Direct Memory Access Cycle


DMA - Principle


PIC32MZ (MIPS32 Core)


PIC32MZ

• Operating Conditions• 2.3V to 3.6V, -40ºC to +85ºC, DC to 200 MHz• 2.3V to 3.6V, -40ºC to +105ºC, DC to 180 MHz• 2.3V to 3.6V, -40ºC to +125ºC (Planned)

• Core: 200 MHz (up to 330 DMIPS) microAptiv™• 16 KB I-Cache, 4 KB D-Cache• MMU for optimum embedded OS execution• microMIPS™ mode for up to 35% smaller code size• DSP-enhanced core:

• Four 64-bit accumulators• Single-cycle MAC, saturating and fractional math

• Code-efficient (C and Assembly) architecture• Clock Management

• 0.9% internal oscillator• Programmable PLLs and oscillator clock sources• Fail-Safe Clock Monitor (FSCM)• Independent Watchdog Timers (WDT) and Deadman Timer (DMT)• Fast wake-up and start-up


PIC32MZ

• Power Management• Low-power modes (Sleep and Idle)

• Integrated Power-on Reset and Brown-out Reset

• Memory Interfaces• 50 MHz External Bus Interface (EBI)

• 50 MHz Serial Quad Interface (SQI)

• Audio and Graphics Interfaces• Graphics interfaces: EBI or PMP

• Audio data communication: I2S, LJ, and RJ

• Audio control interfaces: SPI and I2C™• Audio master clock: Fractional clock frequencies with USB

synchronization


PIC32MZ

• High-Speed (HS) Communication Interfaces (with Dedi cated DMA)• USB 2.0-compliant Hi-Speed On-The-Go (OTG) controller

• 10/100 Mbps Ethernet MAC with MII and RMII interface

• Security Features• Crypto Engine with a RNG for data encryption/decryption and

authentication (AES, 3DES, SHA, MD5, and HMAC)• Advanced memory protection:

• Peripheral and memory region access control

• Direct Memory Access (DMA)• Eight channels with automatic data size detection

• Programmable Cyclic Redundancy Check (CRC)


PIC32MZ

• Advanced Analog Features• 0-bit ADC resolution and up to 48 analog inputs• Flexible and independent ADC trigger sources• Two comparators with 32 programmable voltage references• Temperature sensor with ±2ºC accuracy

• Communication Interfaces• Two CAN modules (with dedicated DMA channels):• 2.0B Active with DeviceNet™ addressing support• Six UART modules (25 Mbps):• Supports LIN 1.2 and IrDA® protocols• Six 4-wire SPI modules• SQI configurable as an additional SPI module (50 MHz)• Five I2C modules (up to 1 Mbaud) with SMBus support• Parallel Master Port (PMP)• Peripheral Pin Select (PPS) to enable function remap


PIC32MZ

• Timers/Output Compare/Input Capture• Nine 16-bit or up to four 32-bit timers/counters• Nine Output Compare (OC) modules

• Nine Input Capture (IC) modules

• PPS to enable function remap• Real-Time Clock and Calendar (RTCC) module

• Input/Output• 5V-tolerant pins with up to 32 mA source/sink• Selectable open drain, pull-ups, and pull-downs

• External interrupts on all I/O pins


PIC32MZ

• Qualification and Class B Support• AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) Planned• AEC-Q100 REVG (Grade 1 -40ºC to +125ºC) Planned

• Class B Safety Library, IEC 60730

• Back-up internal oscillator• Debugger Development Support

• In-circuit and in-application programming

• 4-wire MIPS® Enhanced JTAG interface• Unlimited software and 12 complex breakpoints

• IEEE 1149.2-compatible (JTAG) boundary scan

• Non-intrusive hardware-based instruction trace


PIC32MZ

• Software and Tools Support• C/C++ compiler with native DSP/fractional support

• MPLAB® Harmony Integrated Software Framework

• TCP/IP, USB, Graphics, and mTouch™ middleware• MFi, Android™, and Bluetooth® audio frameworks

• FreeRTOS™, OPENRTOS®, µC/OS™, and other popular RTOS kernels


TMS320F28377


TMS320F28377

Features• TMS320C28x 32-Bit CPU

• 200 MHz• IEEE 754 Single-Precision Floating-Point Unit (FPU)• Trigonometric Math Unit (TMU)• Viterbi/Complex Math Unit (VCU-II)

• Programmable Control Law Accelerator (CLA)• 200 MHz• IEEE 754 Single-Precision Floating-Point Instructions• Executes Code Independently of Main CPU

• On-Chip Memory• 512KB (256KW) or 1MB (512KW) of Flash• (ECC-Protected)• 132KB (66KW) or 164KB (82KW) of RAM• (ECC-Protected or Parity-Protected)• Dual-Zone Security Supporting Third-Party Development


TMS320F28377

• Clock and System Control

• Two Internal Zero-Pin 10-MHz Oscillators• On-Chip Crystal Oscillator

• Windowed Watchdog Timer Module

• Missing Clock Detection Circuitry• 1.2-V Core, 3.3-V I/O Design


TMS320F28377

• System Peripherals

• Two External Memory Interfaces (EMIFs) WithASRAM and SDRAM Support

• 6-Channel Direct Memory Access (DMA) Controller

• Up to 169 Individually Programmable, Multiplexed General-Purpose Input/Output

• (GPIO) Pins With Input Filtering• Expanded Peripheral Interrupt Controller (ePIE)

• Multiple Low-Power Mode (LPM) Support With External Wakeup


TMS320F28377

Communications Peripherals

• USB 2.0 (MAC + PHY)• Support for 12-Pin 3.3 V-Compatible Universal

• Parallel Port (uPP) Interface

• Two Controller Area Network (CAN) Modules (Pin-Bootable)• Three High-Speed (up to 50-MHz) SPI Ports (Pin-Bootable)

• Two Multichannel Buffered Serial Ports (McBSPs)

• Four Serial Communications Interfaces (SCI/UART) (Pin-Bootable)• Two I2C Interfaces (Pin-Bootable)


TMS320F28377

Analog Subsystem• Up to Four Analog-to-Digital Converters (ADCs)

• 16-Bit Mode• 1.1 MSPS Each (up to 4.4-MSPS System Throughput)• Differential Inputs• Up to 12 External Channels

• 12-Bit Mode• 3.5 MSPS Each (up to 14-MSPS System Throughput)• Single-Ended Inputs• Up to 24 External Channels

• Single Sample-and-Hold (S/H) on Each ADC• Hardware-Integrated Post-Processing of ADC Conversions

• Saturating Offset Calibration• Error From Setpoint Calculation• High, Low, and Zero-Crossing Compare, with Interrupt Capability• Trigger-to-Sample Delay Capture

• Eight Windowed Comparators With 12-Bit Digital-to-Analog Converter (DAC) References

• Three 12-Bit Buffered DAC Outputs


Enhanced Control Peripherals

• 24 PWM Channels With Enhanced Features• 16 High-Resolution Pulse Width Modulator (HRPWM) Channels

• High Resolution on Both A and B Channels of 8 PWM Modules

• Dead-Band Support (on Both Standard and High Resolution)• Six Enhanced Capture (eCAP) Modules

• Three Enhanced Quadrature Encoder Pulse (eQEP) Modules

• Eight Sigma-Delta Filter Module (SDFM) Input Channels, 2 Parallel Filters per Channel

• Standard SDFM Data Filtering• Comparator Filter for Fast Action for Out of Range


TMS320F28377

Applications• Industrial Drives• Solar Micro Inverters and Converters

• Radar

• Digital Power• Smart Metering

• Automotive

• Transportation• Power Line Communications


AM3359 Sitara


AM3359 Sitara

Features

• Up to 1-GHz Sitara™ ARM® Cortex®-A8 32-Bit RISC Processor• NEON™ SIMD Coprocessor

• 32KB of L1 Instruction and 32KB of Data Cache with Single-Error Detection (Parity)

• 256KB of L2 Cache with Error Correcting Code of Running at 200 MHz (ECC)

• 176KB of On-Chip Boot ROM• 64KB of Dedicated RAM

• Emulation and Debug - JTAG

• Interrupt Controller (up to 128 Interrupt Requests)


AM3359 Sitara

• On-Chip Memory (Shared L3 RAM)

• 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM• Accessible to all Masters

• Supports Retention for Fast Wakeup

• External Memory Interfaces (EMIF)• mDDR(LPDDR), DDR2, DDR3, DDR3L Controller

• mDDR: 200-MHz Clock (400-MHz Data Rate)

• DDR2: 266-MHz Clock (532-MHz Data Rate)• DDR3: 400-MHz Clock (800-MHz Data Rate)

• DDR3L: 400-MHz Clock (800-MHz Data Rate)

• 16-Bit Data Bus• 1GB of Total Addressable Space

• Supports One x16 or Two x8 Memory Device Configurations


AM3359 Sitara

• External Memory Interfaces (EMIF) – continued

• General-Purpose Memory Controller (GPMC)• Flexible 8-Bit and 16-Bit Asynchronous Memory Interface with up

to Seven Chip• Selects (NAND, NOR, Muxed-NOR, SRAM)

• Uses BCH Code to Support 4-, 8-, or 16-Bit ECC

• Uses Hamming Code to Support 1-Bit ECC• Error Locator Module (ELM)

• Used in Conjunction with the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm

• Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms


AM3359 Sitara

• Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)

• Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More

• Two Programmable Real-Time Units (PRUs)• 32-Bit Load/Store RISC Processor Capable at 200 MHz

• 8KB of Instruction RAM with Single-Error Detection (Parity)

• Single-Cycle 32-Bit Multiplier with 64-Bit Accumulator• Enhanced GPIO Module Provides Shift- In/Out Support and

Parallel Latch on Signal• Three 120-Byte Register Banks Accessible by PRU

• Interrupt Controller Module (INTC) for Handling System Input Events

• Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS


AM3359 Sitara

• Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) – continued

• Peripherals Inside the PRU-ICSS:

• One UART Port with Flow Control Pins, Supports up to 12 Mbps• One Enhanced Capture (eCAP) Module

• Two MII Ethernet Ports that Support Industrial Ethernet, such asEtherCAT

• One MDIO Port


AM3359 Sitara

• Power

• Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic Control [WAKEUP])

• Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])

• Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (AdaptiveVoltage Scaling [AVS])

• Dynamic Voltage Frequency Scaling (DVFS)


AM3359 Sitara

• Real-Time Clock (RTC)

• Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information

• Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO• Independent Power-on-Reset (RTC_PWRONRSTn) Input

• Dedicated Input Pin (EXT_WAKEUP) for External Wake Events (GPIO) Pins

• Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)

• Programmable Alarm Can be Used with External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains


AM3359 Sitara

• Peripherals

• Up to Two USB 2.0 High-Speed OTG Ports with Integrated PHY

• Up to Two Industrial Gigabit Ethernet MACs (10,100, 1000 Mbps)• Integrated Switch – SGX530

• Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces

• Ethernet MACs and Switch Can Operate Independent of Other Functions

• IEEE 1588v2 Precision Time Protocol (PTP)• Up to Two Controller-Area Network (CAN) Ports

• Supports CAN Version 2 Parts A and B

• Up to Two Multichannel Audio Serial Ports (McASPs)• Transmit and Receive Clocks up to 50 MHz

• Up to Four Serial Data Pins per McASP Port with Independent TX and RX Clocks

• Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats

• Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)


AM3359 Sitara

• Peripherals - continued

• Up to Six UARTs• All UARTs Support IrDA and CIR Modes

• All UARTs Support RTS and CTS Flow Control

• UART1 Supports Full Modem Control• Up to Two Master and Slave McSPI Serial Interfaces

• Two Chip Selects

• Up to 48 MHz• Up to Three MMC, SD, SDIO Ports

• 1-, 4- and 8-Bit MMC, SD, SDIO Modes

• MMCSD0 has Dedicated Power Rail for1.8-V or 3.3-V Operation• Up to 48-MHz Data Transfer Rate

• Supports Card Detect and Write Protect

• Complies with MMC4.3, SD, SDIO 2.0 Specifications


AM3359 Sitara

• Peripherals - continued

• Up to Three I2C Master and Slave Interfaces• Standard Mode (up to 100 kHz)

• Fast Mode (up to 400 kHz)

• Up to Four Banks of General-Purpose I/O (GPIO) Pins• 32 GPIO Pins per Bank (Multiplexed with Other Functional Pins)

• GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)

• Up to Three External DMA Event Inputs That Can Also be Used as Interrupt Inputs

• Eight 32-Bit General-Purpose Timers• DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks

• DMTIMER4–DMTIMER7 are Pinned Out

• One Watchdog Timer


AM3359 Sitara

• Peripherals - continued• SGX530 3D Graphics Engine

• Tile-Based Architecture Delivering up to 20 Million Polygons per second

• Universal Scalable Shader Engine (USSE) isa Multithreaded Engine Incorporating Pixel And Vertex Shader Functionality

• Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0

• Industry Standard API Support of Direct3 Mobile, OGL-ES 1.1 and 2.0, OpenVG 1.0, and OpenMax

• Fine-Grained Task Switching, Load Balancing, and Power Management

• Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction

• Programmable High-Quality Image Anti-Aliasing• Fully Virtualized Memory Addressing for OS Operation in a

Unified Memory Architecture


AM3359 Sitara

• Peripherals - continued• LCD Controller

• Up to 24-Bit Data Output; 8 Bits per Pixel (with Maximum 126-MHz Pixel Clock)

• Device Part Number (Unique JTAG ID)• Integrated LCD Interface Display Driver (LIDD) Controller• Integrated Raster Controller• Integrated DMA Engine to Pull Data External Frame Buffer without

Burdening the• Processor via Interrupts or a Firmware Timer• 512-Word Deep Internal FIFO• Supported Display Types:

• Character Displays - Uses LIDD Controller to Program these Displays

• Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display

• Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel


AM3359 Sitara

• Peripherals – continued

• 12-Bit Successive Approximation Register (SAR) ADC• 200K Samples per Second

• Input Can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch

• Can be Configured to Operate as a 4-wire, Registers 5-wire, or 8-wire Resistive Touch Screen Controller (TSC) Interface

• Up to Three 32-Bit eCAP Modules

• Configurable as Three Capture Inputs or RNG) Three Auxiliary PWM Outputs


AM3359 Sitara


• Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs) • Dedicated 16-Bit Time-Base Counter with Time and

Frequency Controls• Configurable as Six Single-Ended, Six Dual-Symmetric, or Three

Dual-Edge Asymmetric Outputs

• Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules

• Device Identification

• Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable

• Production ID• Device Part Number (Unique JTAG ID)

• Device Revision (Readable by Host ARM)


AM3359 Sitara


• Debug Interface Support• JTAG and cJTAG for ARM (Cortex-A8 and PRU-ICSS Debug

• Supports Device Boundary Scan

• Supports IEEE 1500• DMA

• On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:

• Transfers to and from On-Chip Memories

• Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)


AM3359 Sitara


• Inter-Processor Communication (IPC)• Integrates Hardware-Based Mailbox for IPC and Spinlock for

Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS

• Mailbox Registers that Generate Interrupts

• Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)

• Spinlock has 128 Software-Assigned Lock Registers• Security Controller (TSC) Interface

• Crypto Hardware Accelerators (AES, SHA, PKA, RNG)

• Boot Modes• Boot Mode is Selected via Boot Configuration Pins Latched on

the Rising Edge of the PWRONRSTn Reset Input Pin


AM3359 Sitara

Applications• AC Analog Input Module• AC Drive Power Stage Module

• ATMs (Automated Teller Machines

• Analog Output Module• Audio Dock: Performance

• Barcode Scanner

• Brushless DC Motor Drives• CNC Control

• CPU (PLC Controller)

• Camera• Central Inverters

• Chemistry/Blood Gas Analyzers

• Communication Modul• Control Units for Rail Transport


AM3359 Sitara

Applications – cont.• Data Acquisition (DAQ)• Data Concentrators

• Digital Input Module

• Digital Output Module• Door & Window Sensor

• EPOS, ECR and Cash Drawer

• Electricity Meter• Ethernet Repeaters

• HVAC Gateway

• IP Network Camera• Industrial Monitor

• Industrial Robot CPU Board

• Industrial Robot Communication Module


AM3359 Sitara

Applications – cont.• Intrusion Control Panel• Micro Inverters

• Panel PLC

• People Counting• Portable Data Terminal

• Portable Monitor

• Power Line Communications• Process Analytics (pH, Gas, Concentration, Force & Humidity)

• Process BUS (IEC61850)

• Protection Relay - Bay control• Servo Drive Control Module

• Servo Drive Main Power Supply

• Servo Drive Position Feedback


AM3359 Sitara

Applications – cont.• Servo Drive Power Stage Module• Special Function Module

• Stepper Drives

• String Inverters• Temperature Transmitter

• Wireless Communications

• Wireless Controls• Wireless Headset & Headphones

Digital Control of Electric Drives

Digital Signal ProcessorEND

Czech Technical University in Prague – Faculty of Electrical Engineering

Digital Control of Electric Drives - O...

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