Digital Assignment - Design of a gray code Genertor … Jørgensen Digital Assignment Design of a...

NAPIER.

University

School of Engineering

Electronic Systems

Module : SE32102

Digital Assignment

Design of a Gray Code Generator and Decoder

By

Klaus Jørgensen.

Napier No. 04007824

Teacher.

Jay Hoy

U8

J

K C Q

QP

U1 SN7476

J

K C Q

QP

U2 SN7476

J

K C Q

QP

U3 SN7476

J

K C Q

QP

U4 SN7476

+Vcc

&

U6 SN7408&

U7 SN7408

&

U9 SN7408

&

U10 SN7408

&

U11 SN7408

&

U12 SN7408

=1

U13 !XOR

1

U14 SN7404

&

U15 SN7408

&

U16 SN7408

=1

U17 !XOR

=1

U18 !XOR

FA FB FC FD

Clock 1MHz=1

U19 !XOR

=1

U20 !XOR

=1

U21 !XOR

BA out binary

BB out binary

BC out binary

BD out binary

Flip-Flop A Flip-Flop B Flip-Flop C Flip-Flop D

Klaus Jørgensen Digital Assignment


/15

Abstract.:

In this paper is there a little background about the Gray code. There is also showed one way to build a Gray code generator from 0 to 15, with State Transition Diagram, State Table, Karnaugh maps, reduction of boolean algebra, circuit and simulations, the same is don for a Gray code to binary decoder, and the tow circuits is also tested together.



/15

Table of contents.: Introduction.:....................................................................................................................... 4

Theoretical Design of a Gray Code Generator. .................................................................. 5

State Transition Diagram. ............................................................................................... 5

State Table of the Gray code generator........................................................................... 6

Karnaugh maps for the Gray code generator. ................................................................. 6

Gray code generator Circuit schematic and Simulation. .................................................... 9

Gray Code to Binary Decoder........................................................................................... 10

State Transition Diagram. ............................................................................................. 10

State Table of the Gray code generator......................................................................... 10

Karnaugh maps for the Gray code to binary decoder. .................................................. 11

Gray code to binary decoder Circuit schematic and Simulation....................................... 12

Total circuit and simulation of Gray code generator and binary decoder......................... 13

Conclusion. ....................................................................................................................... 14

Reference. ......................................................................................................................... 15



/15

Introduction.: Gray code was invented for practical reasons. Because it only changes one bit at the time, it can be used to determine the position of a cogwheel on a big machine for instance. The gray code or binary code is printed on the cogwheel, and some sensors are reading the signals, and transmit the signal to the software, If the binary code is printed on the cogwheel, there is a bigger possibility for an error in the reading of the code, because the binary code at some times changes more then one bit at the time, for example the change from 7 (0111) to 8 (1000) figure 2, where all 4 bits has to change, there is a big possibility for an error, if there is a little delay in the circuit. If the gray code is used instead of the binary code there is a much smaller possibility for an error because the gray code only changes one bit at the time [3, 4]. Figure 1 shows an example of how the binary code or gray code can look like on a cogwheel.

Decimal Gray Code Input Binary Output 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 2 0 0 1 1 0 0 1 0 3 0 0 1 0 0 0 1 1 4 0 1 1 0 0 1 0 0 5 0 1 1 1 0 1 0 1 6 0 1 0 1 0 1 1 0 7 0 1 0 0 0 1 1 1 8 1 1 0 0 1 0 0 0 9 1 1 0 1 1 0 0 1

10 1 1 1 1 1 0 1 0 11 1 1 1 0 1 0 1 1 12 1 0 1 0 1 1 0 0 13 1 0 1 1 1 1 0 1 14 1 0 0 1 1 1 1 0 15 1 0 0 0 1 1 1 1

LSB (Least Significant Bit)

MSB (Most Significant Bit)

Binary code

Gray code

Figure 1

Figure 2



/15

Theoretical Design of a Gray Code Generator. The 16 bit Gray code generator is made by 4 JK flip-flops and 10 gates, one JK flip-flop for each output, QA is the MSB (Most Significant Bit) and QD is the LSB (Least Significant Bit). Figure 3 shows a chart of how the JK flip-flop works. Q is the Present state, Q+ is the Next stase, J and K is the inputs of the flip-flop, to get from Q to Q+, J and K have to get the value as shown in figure 3 the x is a don’t care state is can be 1 or 0 it doesn’t matter [1].

Q Q+ J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0

State Transition Diagram. To get a view of how the Gray code generator must work a State Transition diagram is made, it showed in figure 4

Figure 3

0

4

12

13

14

11

10

98

6

5

3

2

115

7

0000

0001

0011

0010

0110

0111

0101

01001100

1101

1111

1110

1010

1011

1001

1000

Figure 4



/15

State Table of the Gray code generator. Figure 5 shows the State table for the Gray code generator, it shows the Present, Next and the Change state of the Gray code generator.

Present State. Next State Change State QA QB QC QD QA+ QB+ QC+ QD+ JA KA JB KB JC KC JD KD0 0 0 0 0 0 0 0 1 0 x 0 x 0 x 1 x 1 0 0 0 1 0 0 1 1 0 x 0 x 1 x x 0 2 0 0 1 1 0 0 1 0 0 x 0 x x 0 x 1 3 0 0 1 0 0 1 1 0 0 x 1 x x 0 0 x 4 0 1 1 0 0 1 1 1 0 x x 0 x 0 1 x 5 0 1 1 1 0 1 0 1 0 x x 0 x 1 x 0 6 0 1 0 1 0 1 0 0 0 x x 0 0 x x 1 7 0 1 0 0 1 1 0 0 1 x x 0 0 x 0 x 8 1 1 0 0 1 1 0 1 x 0 x 0 0 x 1 x 9 1 1 0 1 1 1 1 1 x 0 x 0 1 x x 0

10 1 1 1 1 1 1 1 0 x 0 x 0 x 0 x 1 11 1 1 1 0 1 0 1 0 x 0 x 1 x 0 0 x 12 1 0 1 0 1 0 1 1 x 0 0 x x 0 1 x 13 1 0 1 1 1 0 0 1 x 0 0 x x 1 x 0 14 1 0 0 1 1 0 0 0 x 0 0 x 0 x x 1 15 1 0 0 0 0 0 0 0 x 1 0 x 0 x 0 x

Karnaugh maps for the Gray code generator. The karnaugh maps and the boolean algebra expression is shown below, with the circuit for the boolean algebra. JA QDQC\QAQB 0 0 0 1 1 1 1 0

0 0 0 1 x x 0 1 0 0 x x 1 1 0 0 x x 1 0 0 0 x x

QCQDQBJA = KA QDQC\QAQB 0 0 0 1 1 1 1 0

0 0 x x 0 1 0 1 x x 0 0 1 1 x x 0 0 1 0 x x 0 0

QBQCQDKA =

Figure 5

&

U5 SN7411

JA QB

QD

QC

Figure 6

&

U7 SN7411

KA

QB

QD

QC

Figure 7



/15

JB QDQC\QAQB 0 0 0 1 1 1 1 0

0 0 0 x x 0 0 1 1 x x 0 1 1 0 x x 0 1 0 0 x x 0

QDQCQAJB = KB QDQC\QAQB 0 0 0 1 1 1 1 0

0 0 x 0 0 x 0 1 x 0 1 x 1 1 x 0 0 x 1 0 x 0 0 x

QDQAQCKB = JC QDQC\QAQB 0 0 0 1 1 1 1 0

0 0 0 0 0 0 0 1 x x x x 1 1 x x x x 1 0 1 0 1 0

( ) QD*QBQA

QAQBQDQDQAQBJC

⊕

+=

KC QDQC\QAQB 0 0 0 1 1 1 1 0

0 0 x x x x 0 1 0 0 0 0 1 1 0 1 0 1 1 0 x x x x

( ) QD*QBQA QDQBQAQBQDQAKC

⊕+=

=1

U13 !XOR

&

U16 SN7408KC

QD

QB

QA

Figure 11

=1

U13 !XOR

1

U14 SN7404

&

U15 SN7408JC

QD

QB

QA

Figure 10

&

U9 SN7411

KB QA

QD

QC

Figure 9

&

U6 SN7411

JB QA

QD

QC

Figure 8



/15

JD QDQC\QAQB 0 0 0 1 1 1 1 0

0 0 1 0 1 0 0 1 0 1 0 1 1 1 x x x x 1 0 x x x x

( ) ( ) ( )( ) ( ) ( )( ) ( )( ) XNORXORCQBQA

QC*QBQAQC*QBQA

QC*QBQAQC*QBQAQC*QBQA

QC*QBQA QC*QAQBQC*QAQB

QCQBQAQCQAQBQBQCQAQAQBQCJD

+=⊕⊕

⇒⊕+⊕

⇒⊕=+

⇒⊕=+

⇒+++=

KD QDQC\QAQB 0 0 0 1 1 1 1 0

0 0 x x x x 0 1 x x x x 1 1 1 0 1 0 1 0 0 1 0 1

( ) ( ) ( )( ) ( ) ( )( ) ( )

XORXOR +⇒⊕⊕⇒⊕+⊕

⊕=+

⊕=+

⇒+++=

QCQBQA QC*QBQAQC*QBQA

QC*QBQAQC*QBQAQC*QBQA

QC*QBQAQC*QAQBQC*QAQB

QBQCQAQAQBQCQCQBQAQCQAQBKD

=1

U13 !XOR

=1

U18 !XORKD

QC

QB

QA

Figure 13

=1

U13 !XOR

=1

U17 !XORJD

QC

QB

QA

Figure 12



/15

Gray code generator Circuit schematic and Simulation. To make the Gray code generator on figure 14, there are used 4 Flip-Flops, 10 And-gates, 3 Or-gates and 1 inverter.

The simulation of the Gray code generator in figure 14 is shown in figure 15. The clock is on 1MHz, the length of one cluck pulse is 1µs.

• sMf

Tp µ11

11=⇒=

The simulation on figure 15 shows the same pattern as the State table for the Gray code generator in figure 5 on page 6.

T

Time (s)0.00 5.00u 10.00u 15.00u 20.00u

Clock

L

H

QA

L

H

QB

L

H

QC

L

H

QD

L

H

Figure 15

U8

J

K C Q

QP

U1 SN7476

J

K C Q

QP

U2 SN7476

J

K C Q

QP

U3 SN7476

J

K C Q

QP

U4 SN7476

+Vcc

=1

U13 !XOR

1

U14 SN7404

&

U15 SN7408

&

U16 SN7408

=1

U17 !XOR

=1

U18 !XOR

FA FB FC FD

Clock 1MHz

&

U5 SN7411

&

U7 SN7411

&

U6 SN7411

&

U9 SN7411

Flip-Flop A Flip-Flop B Flip-Flop C Flip-Flop D

Figure 14



/15

Gray Code to Binary Decoder.

State Transition Diagram. To get a view of how the Gray code to binary decoder must work a State Transition diagram is made, to se what the output of the Gray code to binary decoder shall show, it showed on figure 16.

State Table of the Gray code generator. Figure 17 shows the State table for the Gray code to binary decoder, it shows the input from the Gray code generator and the output from the Gray code to binary decoder.

Gray Code Input Binary Output A B C D QA QB QC QD 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 2 0 0 1 1 0 0 1 0 3 0 0 1 0 0 0 1 1 4 0 1 1 0 0 1 0 0 5 0 1 1 1 0 1 0 1 6 0 1 0 1 0 1 1 0 7 0 1 0 0 0 1 1 1 8 1 1 0 0 1 0 0 0 9 1 1 0 1 1 0 0 1 10 1 1 1 1 1 0 1 0 11 1 1 1 0 1 0 1 1 12 1 0 1 0 1 1 0 0 13 1 0 1 1 1 1 0 1 14 1 0 0 1 1 1 1 0 15 1 0 0 0 1 1 1 1

0

4

12

13

14

11

10

98

6

5

3

2

115

7

0000

0001

0010

0011

0100

0101

0110

01111000

1001

1010

1011

1100

1101

1110

1111

Figure 16

Figure 17



/15

Karnaugh maps for the Gray code to binary decoder. The karnaugh maps and the boolean algebra expression is shown below, with the circuit for the boolean algebra. QA

AQA =

QB DC\AB 0 0 0 1 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 0 0 1 0 1

XOR⇒⊕+=BA

BABAQB

QC DC\AB 0 0 0 1 1 1 1 0 0 0 0 1 0 1 0 1 1 0 1 0 1 1 1 0 1 0 1 0 0 1 0 1

( ) ( )

( )XORinput 3CBA

BABAC

*BA*C

BABA*CABAB*CQC

⇒⊕⊕⇒⊕+⊕⊕

⇒⊕+⊕

⇒+++=

BAC

QD DC\AB 0 0 0 1 1 1 1 0 0 0 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 0

( ) ( )( ) ( )

XORinput 4DCBA DC*BADC*BA

DC*BADC*AB

DC*BADC*AB

CDCD*BADCDC*AB

CDCD*BADCDC*ABQD

⇒⊕⊕⊕⇒⊕⊕+⊕⊕

⇒⊕+⊕

+⊕+⊕

⇒+++

++++=

DC\AB 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1

QA A

Figure 18

=1

U19 !XOR

QB A B

Figure 19

=1

U19 !XOR

=1

U20 !XOR

QC ABC

Figure 20

=1

U19 !XOR

=1

U20 !XOR

=1

U21 !XOR

QD A B C D

Figure 21



/15

Gray code to binary decoder Circuit schematic and Simulation. There is only used 3 Exclusive OR gates to make the Gray code to binary decoder, and it is showed in figure 22 and the simulations result is showed in figure 23 To make the simulation a 4-bit data generator was used to make the Gray code from 0 to 15, as it is showed in figure 17 on page 10.

=1

U19 !XOR

=1

U20 !XOR

=1

U21 !XOR

QA out binary

QB out binary

QC out binary

QD out binary

1234

U1 A B

C

D

Gray code generator

Figure 22

T

Time (s)0.00 5.00u 10.00u 15.00u 20.00u

A

B

C

D

QA out binary

QB out binary

QC out binary

QD out binary

Figure 23



/15

Total circuit and simulation of Gray code generator and binary decoder. The output FA, FB, FC and FD is the output from the JK flip-flops and is the put from the Gray code generator, the output BA, BB, BC and BD is the output from the Gray code to binary code decoder.

T

Tim

e (s

)0.

005.

00u

10.0

0u15

.00u

20.0

0u

BA

out

bin

ary

BB

out

bin

ary

BC

out

bin

ary

BD

out

bin

ary

FA

FB

FC

FD

Clo

ck 1

MH

z

Figure 24

U8

J KC

QQP

U1 S

N747

6

J KC

QQP

U2 S

N747

6

J KC

QQP

U3 S

N747

6

J KC

QQP

U4 S

N747

6

+Vc

c

=1U13

!XOR

1

U14

SN74

04

&

U15

SN74

08

&

U16

SN74

08

=1U17

!XOR

=1U18

!XOR

FAFB

FCFD

Cloc

k 1M

Hz=1U1

9 !X

OR

=1U20

!XOR

=1U21

!XOR

BA o

ut b

inar

y

BB o

ut b

inar

y

BC o

ut b

inar

y

BD o

ut b

inar

y

&

U5 S

N741

1

&

U7 S

N741

1

&

U6 S

N741

1

&

U9 S

N741

1

Flip

-Flo

p A

Flip

-Flo

p B

Flip

-Flo

p C

Fl

ip-F

lop

D



/15

Conclusion. The gray code generator is made of 4 JK flip-flops and 10 gates, U13 (Exclusive OR)and U14 (Inverter) makes an Exclusive NOR gate this it don because there is no Exclusive NOR gate in Tina, U17 and U18 was meant to be 3 inputs Exclusive OR gates but in Tina there only is 2 inputs Exclusive OR gates, if all this was change the numbers of gate still would be 10. If the gray code generator should be build in practical, the 4 And gates with 3 inputs (U5, U6, U7, U9) would be placed in 2 IC´s with each 3 And gates, and the 2 And gates with 2 inputs would be placed in one IC with 4 And gates, to save one IC, the 2 And gates with 2 inputs (U15, U16) can be switch with the 2 And gates with 3 inputs, and one input of each And gate, can be connected to the 5V power a logic 1. The gray code to binary code is made of 3 Exclusive OR gates with 2 inputs each, the decoder could have been made with 1 Exclusive OR gates with 2 inputs, 1 Exclusive OR gates with 3 inputs, Exclusive OR gates with 4 inputs, but this would not be are good way to make the circuit in practical, because the circuit would be made of 3 IC´s, if the circuit is made with 3 Exclusive OR gates with 2 inputs each there only have to be used one IC. The complete circuit on page 13 figure 24 works fine, it makes a gray code from 0 to 15 and the decoder from gray code to binary code also works, as the diagram of the outputs shows on page 13, figure 24. _________________________________

Klaus Jørgensen 23 November 2004



/15

Reference. 1. Digital teknik, by Leif Møller Andersen, (A Danish book).

ISBN : 87-600-0126-7

2. Introduction to Electrical Engineering, by Mulukutla S. Sarma,

ISBN : 0-19-513604-7

3. Digital System Design second edition, by Barry Wilkinson

ISBN : 0-13-220286-7

4. Digital Electronics an introduction to theory and practice second edition

by William H. Gothmann

ISBN : 0-13-212084-4

Digital Assignment - Design of a gray code Genertor … Jørgensen Digital Assignment Design of a...

Documents

Transcript of Digital Assignment - Design of a gray code Genertor … Jørgensen Digital Assignment Design of a...