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Diffusion Model of Nonlinear HPM Effects in Advanced Electronics

John Rodgers, Todd Firestone, Victor Granatstein,Steven Anlage and Renato de Moraes

Institute for Research in Electronics and Applied PhysicsUniversity of Maryland

College Park, MD 20742

rodgers@umd.edu

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Standard Form 298 (Rev. 8-98) Prescribed by ANSI Std Z39-18

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Outline• Overview of results and contributions by UMD HPM

Effects Research Group to the MURI Program– Results of experimental measurement and characterization of HPM

effects at the device and circuit levels.– Investigation of effects from complex HPM waveforms– HPM effects in electronic networks and systems.

• Model of HPM effects in semiconductor circuits– Complement to RCM analysis of complex structures– Simple, scalable and based on physical device parameters– Compatible with existing high-frequency circuit simulators– Accurate predictor of susceptibility in existing and advanced

circuits and systems

Effects Testing of Integrated Circuits

0

0.5

1

1.5

2

2.5

3

3.5

0 1 2 3 4 5

Time (μsec)

Volta

ge

Output Voltage

BB Input Voltage

DigitizingScope

SpectrumAnalyzer(Existing)

20 dBRF Amplifier

20 dB

Device UnderTestBias Tee

ProgrammablePulsed RF Source

BasebandInput

Signals

RF InputSignals

DigitizingScope

BasebandFilter

BasebandOutputSignals

RF OutputSignals

Control/Data AcquisitionWorkstation

Instrument Control and Data Bus

High-speed CMOS Gate

•Onset of effects 0.25 < VRF < 1 V

•Depend on RF frequency, pulse width, modulation, logic state, bias voltage, bus impedances, surrounding circuitry….

•Typically pulse widths > 100 nsec are required

Upset Threshold vs. Frequency in High-speed CMOS

0

1

2

3

4

5

0.8 1 1.2 1.4 1.6 1.8 2

Frequency [GHz]

RF

Am

plitu

de (V

) Circuit Upset

Circuit Marginally Functional

RF voltage at the input of a typical CMOS

Expanded view showing actual RF cycles.

Zero Baseline

0

0.5

1

0 1 2 3 4 5

Time (μsec)

BB

Inpu

t Vol

tage

Bandwidth Limited Voltage

Examples of Effects in Advanced CMOS

0

0.5

1

1.5

2

2.5

3

3.5

0 1 2 3 4 5 6

Time (μsec)

Volta

ge

Vout

Vin

-2

-1

0

1

2

3

4

5

0 10 20 30

Time (μsec)

Volta

ge

VoutVin

0

0.5

1

1.5

2

2.5

3

3.5

0 5 10 15 20Time [μsec]

Volta

ge [V

]

Vin

Vout

Prompt State Error

Bias Shift & Persistent Latching

Oscillations

-1

0

1

2

3

4

5

0 5 10 15 20

Time (μsec)

Volta

ge VoutVin

Instability

Mapping RF effects in integrated circuits

High-speed CMOS Advanced Low-voltage CMOS

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Examples of ESD protection in integrated circuits

Electrostatic discharge protection devices are integrated into virtually all integrated circuits: discrete, logic, analog, RFIC, mixed signal

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Physical Layout of ESD Protection Device

Input Pad

Multi-finger Junctions

Substrate (ground) Contact

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Electrical and Physical Characteristicsof ESD Devices

Typical range of voltages relevant for HPM effects

Input Pad

Ground (Vss)

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Simplified Schematic of a CMOS Circuit

Resonant circuits consisting of lumped and distributed parasitic elements

Lparasitic

ESDDiode

RF Pulse ESDDiode

Vcc

C Bypass

ESDDiode

Transmit Gate

Bus LineZinput

Bus LineZoutput

RF Pulse

Receive Gate

Lparasitic

Lparasitic

Impedance at the input of high-speed CMOS logic circuit

1

10

100

1000

0 0.5 1 1.5 2

Frequency [GHz]

Impe

danc

e [O

hms]

Vbias= -0.70

Vbias= -0.60

Vbias= -0.50

Vbias= -0.40

Vbias= 0.0

Vbias= +2.0

•When driven at resonance, the diode current and the rectified voltage increase.

The ESD diodes down-convert the modulation frequencies off the microwave carrier

0

10

0

Frequency

Am

plitu

de

0

10

0 2000

FrequencyA

mpl

itude

Baseband

RF Harmonics

These frequencies trigger CMOS operation

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Comparison of measured and simulated response using model parameters extracted from small-signal measurements

High-speed CMOS Logic Advanced Low-voltage CMOS

This behavior has been observed and studied in a wide variety of circuits.

-2

0

2

4

6

8

10

12

0 1000 2000 3000 4000Time (arb)

Out

put V

olta

ge (V

)

Vrf= 10 mVVrf= 50 mVVrf = 100 mVVrf= 200 mV

0

2

4

6

8

10

12

0 200 400 600 800 1000Frequency [MHz]

Out

put D

evia

tion

[V] Vrf=50 mV

Vrf= 100 mV

Vrf= 200 mV

-10

-8

-6

-4

-2

0

2

0 50 100 150 200

Time (μsec)

Out

put V

olta

ge (V

)

0

2

4

6

8

0 100 200 300 400 500

RF Amplitude (mV)

Bas

eban

d Vo

ltage

(V)

BB_AmplBB_meanSquare Law

Discrete (JFET) Analog (Op Amp)

Are these parasitic diodes good rectifiers at microwave frequencies (f > 300 MHz)?

DC I-V Curve

-50

-25

0

25

50

-1.00 0.00 1.00 2.00

Diode Voltage (V)

Dio

de C

urre

nt ( μ

A)

• W. Crevier, “Rectification Equivalence: A method for characterizing semiconductor rectification,” Titan-Jaycorinternal report to DTRA, December, 1996.

•M. L Forcier, R. E. Richardson, “ Microwave rectification RFI response in field-effect transistors,” IEEE Trans. Electromag. Comp., vol. EMC-21, no. 4, Nov. 1979.

•D. J. Kenneally, G. O. Head, S. C. Anderson, “EMI noise susceptibility of ESD protect buffers in selected MOS devices,” Proc. IEEE Int. Conf. Electromag. Comp., Wakefield, MA, August, 1985, pp. 251-261.

RF Voltage at input terminal

Static Bias Point0

0.5

1

1.5

2

2.5

1 10 100 1000 10000

Frequency (MHz)

Nor

mal

ized

Vol

tage

CD4000TrendFast CMOS

CD 4000

High-speed CMOS

The “rectification” model does not a complete the picture

ggNMOS

Lp

CoreLogic

Input

Package

Lp Diffusion Model

Model of Drain-Bulk Diode in CMOS

High-Frequency Analysis of D-B Junctions

2

2

2

( , ) ( , ) ( , )

( 1)

1

d

p

qVp kT

diffp D

DD

D

p x t p x t p x tDt x

D nI qA eL N

iY G jv

τ

ωτ

∂Δ ∂ Δ Δ= −

∂ ∂

= −

= = +

DC I-V Curve

-50

-25

0

25

50

-1.00 0.00 1.00 2.00

Diode Voltage (V)

Dio

de C

urre

nt ( μ

A)

Time-dependent

Diffusion Equation

Solution for “Abrupt”Boundary Conditions

High-frequency Admittance

D-B Junction

High-Frequency Admittance of D-B Junctions (Is= 10-15 A, Vth= 0.025 V, τ = 5 nsec)

0

1

2

3

4

5

6

1 10 100 1000 10000

Frequency (MHz)

Cap

acita

nce

(pF)

0

0.01

0.02

0.03

0.04

Con

duct

ance

(S)

CapacitanceConductance

Comparison of measured and calculated D-B sensitivity in advanced low-voltage CMOS (τ = 5 nsec)

0

0.02

0.04

0.06

0.08

10 100 1000 10000Frequency (MHz)

Del

ta V

(V)

MeasuredCalculated

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Comparison of the D-B junction sensitivity in micron-scale logic

0

0.5

1

1.5

2

2.5

0 1000 2000 3000 4000

Frequency (MHz)

RF-

to-B

B V

olta

ge T

rans

fer

0.13 Micron ProcessorHigh-speed_CMOSCD 4000

Overview of studies of HPM upset in electronic systems

View of the assembled LAN switch Chassis cover removed

Power Supply

Power Bus

EMI Gasket

•Systems consist of many circuits with internal resonances interconnected by transmission lines within complex cavities.

•What parts of the system are most likely to be upset once RF penetrates the enclosure?

Distribution of parasitic resonant frequencies and quality factors in a digital communications system

0

2

4

6

8

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Resonant Frequency (GHz)

Qua

lity

Fact

or

0

200

400

600

800

0.4 0.8 1.0 1.2 1.7 1.9 3.0

Pin

Cou

ntI/O

Logic

System Controller

CPU

Memory

View of the IC layout on the motherboard of a programmable LAN

switch

Results from small-signal measurements of parasitic resonances

in the IC’s of a functional set

Characteristics of electronic systems

LAN switch with coaxial RF ports PC with waveguide port

• Most electronic systems contain modular components that are packaged according to standardized form factors (4U, 19” bays, ATX, etc.)

•Does this present any universal conditions or likely avenues for HPM attack?

•The enclosures are clearly natural microwave resonators.

Results of S-parameter measurements in an operating LAN switch

• Port #1 is a dipole launching antenna and port #2 is connected to the main +12 VDC power bus on the motherboard

-50

-40

-30

-20

-10

0

0 1 2 3 4Frequency (GHz)

Ref

l / T

rans

Coe

f (dB

)

S_11

S_21

Port #1Port #2

• Strong resonances are observed across L-band (~1-2 GHz)

RF Surface Current Density for Various TEM Eigenmodeson the Motherboard

f= 1.284 GHz f= 1.502 GHz

f= 1.654 GHzf= 1.591 GHz

Results from Upset Studies in a LAN Switch

•At upset, the RF caused the switching power supply to either completely shut down or output the incorrect voltage for times that were 100 – 1000 times the RF pulse width.

•This forced the microcontroller to completely reboot the system.

-12

-8

-4

0

4

8

12

1 1.5 2 2.5 3

Frequency (GHz)

DC

Vol

tage

Dev

iatio

n at

Ups

et (V

)

0

0.1

0.2

0.3

0.4

0.5

0.6

RF

Am

plitu

de a

t Ups

et

DC_VoltageRF_Ampl

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Schematic of a typical switching power supply

Rectified RF voltage at the feedback pin fools the comparator into detecting an over-voltage condition. It then sends a shutdown signal to the power controller via an opto-isolator

The power controller feedback is designed to shutdown the system (~ 30 sec) even if the “fault” is momentary (microseconds).

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Conclusions• RF rectification by ESD protection diodes and parasitic resonances have

been identified as major susceptibility issues.• The RF characteristics of these devices can be accurately described

using lumped-element circuit models with simple high-frequency diode parameters.

• Upset can be easily predicted in terms of the high-frequency transfer characteristics of the circuit and the RF voltage, frequency andmodulation at the circuit terminals.

• In systems, the problem requires an EM or RCM treatment.• Power controllers with feedback have been identified as a major and

universal problem.• An informed basis for developing effects sources:

– L-band– Wideband or chaotic modulation– 10-100 MW Power levels

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Possible Solutions• Low-voltage differential

signaling between critical communications nodes

• New concepts for opto-isolation, low-power diodes, single photon detectors, etc.

• Power supply redesign

• New ESD circuits and structures

LVDS Input Lines

Core Logic

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Students and Academics

•Student Research Assistants: Kathryn Chang, R. Mac Laren,

•Sponsored research: Calvin Cheung

•REU Interns: L. Goodman, M. Adan, K. Konstantine, S. Vora,

•UMD ENEE 499 Advanced Lab, “HPM Effects in Communications Electronics: B. Yeshitla, H. Lee, M. Stamm, M. Brill

•UMD Gemstone Honors Program

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Publications, Invited Talks, Mini-courses 2004-present

1. T.M. Firestone, J. Rodgers and V.L. Granatstein, “Response of CMOS Logic with Electrostatic Discharge Protection to Pulsed Microwave Excitation Submitted to IEEE Trans. on Circuits and Systems.

2. T. M. Firestone, “RF Induced Nonlinear Effects in High-Speed Electronics" Masters of Science Thesis, University of Maryland, May 2004.

3. J. Rodgers, T. Firestone, V. L. Granatstein, V. Dronov, T. M. Antonsen, Jr., and E. Ott, “Study and applications of wideband oscillations in high-power pulsed traveling-wave tubes,” Proceedings of the Sixth International Vacuum Electronics Conference IVEC 2005, Noordwijk, The Netherlands, April 2005.

4. J. Rodgers, “HPM upset in communications systems," Invited talk presented at the Defense Threat Reduction Agency workshop on Microwave Effects, Sept., 2005, Alb. NM.

5. J. Rodgers, “Nonlinear and chaotic effects in communications electronics from high-power microwave pulses,” Invited one-day minicourse presented to Defense Intelligence Agency 09 August, 2005, Hunstville, AL.

6. J. Rodgers, “Stochastic microwave sources for effects applications," invited talk presented at the Defense Threat Reduction Agency workshop on Microwave Effects, Sept., 2005, Alb. NM.