Different File Formats (file extensions)

There are different type of the files generated during a design cycle or data received by the library vendor/foundry. Few of them having specific extension. Just to know the extension, you can easily identity the type of content in that file.

I am listing down of the file extension. Please let me know if you find any extension is missing. I will add those later on.

File Extensions:

*.v - Verilog source file. Normally it’s a source file your write. Design Compiler, and IC Compiler can use this format for the gate-level netlist.

*.vg, .g.v - Verilog gate-level netlist file. Sometimes people use these file extension to differentiate source files and gate-level netlists.

*.svf - Automated setup file. This file helps Formality process design changes caused by other tools used in the design flow. Formality uses this file to assist the compare point matching and verification process. This information facilitates alignment of compare points in the designs that you are verifying. For each automated setup file that you load, Formality processes the content and stores the information for use during the name-based compare point matching period.

 *.ddc - Synopsys internal database format. This format is recommended by Synopsys to hand gate-level netlists.

 *.vcd - Value Change Dump format. This format is used to save signal transition trace information. This format is in text format, therefore, the trace file in this format can get very large quickly. There are tools like vcd2vpd, vpd2vcd, and vcd2saif switch back and forth between different formats.

*.vpd - VCD Plus. This is a proprietary compressed binary trace format from Synopsys. This file format is used to save signal transition trace information as well.

 *.saif - Switching Activity Interchange Format. It’s another format to save signal transition trace information. SAIF files support signals and ports for monitoring as well as constructs such as generates, enumerated types, records, array of arrays, and integers.

 *.tcl - Tool Command Language (Tcl) scripts. Tcl is used to drive Synopsys tools.  *.sdc - Synopsys Design Constraints . SDC is a Tcl-based format. All commands in an

SDC file conform to the Tcl syntax rules. You use an SDC file to communicate the design intent, including timing and area requirements between EDA tools. An SDC file contains the following information: SDC version, SDC units, design constraints, and comments. 

 *.lib - Technology Library source file. Technology libraries contain information about the characteristics and functions of each cell provided in a semiconductor vendor’s library. Semiconductor vendors maintain and distribute the technology libraries. In our case the vendor is Synopsys. Cell characteristics include information such as cell names, pin names, area, delay arcs, and pin loading. The technology library also defines the conditions that must be met for a functional design (for example, the maximum transition time for nets). These conditions are called design rule constraints. In addition to cell

information and design rule constraints, technology libraries specify the operating conditions and wire load models specific to that technology.

 *.db - Technology Library. This is a compiled version of *.lib in Synopsys database format.

 *.plib - Physical Library source file. Physical libraries contain process information, and physical layout information of the cells. This information is required for floor planning, RC estimation and extraction, placement, and routing.

 *.pdb - Physical Library. This is a compiled version of *.plib in Synopsys database format.

 *.slib - Symbol Library source file. Symbol libraries contain definitions of the graphic symbols that represent library cells in the design schematics. Semiconductor vendors maintain and distribute the symbol libraries. Design Compiler uses symbol libraries to generate the design schematic. You must use Design Vision to view the design schematic. When you generate the design schematic, Design Compiler performs a one-to-one mapping of cells in the netlist to cells in the symbol library.

 *.sdb - Symbol Library. This is a compiled version of *.slib in Synopsys database format.

 *.sldb - DesignWare Library. This file contains information about DesignWare libraries.

 *.def - Design Exchange Format. This format is often used in Cadence tools to represent physical layout. Synopsys tools normally use Milkyway format to save designs.

 *.lef - Library Exchange Format. Standard cells are often saved in this format. Cadence tools also often use this format. Synopsys tools normally use Milkyway format for standard cells.

 *.rpt - Reports. This is not a proprietary format, it’s just a text format which saves generated reports by the tools when you use the automated makefiles and scripts.

 *.tf - Vendor Technology File. This file contains technology-specific information such as the names, characteristics (physical and electrical) for each metal layer, and design rules. These information are required to route a design.

 *.itf - Interconnect Technology File. This file contains a description of the process crosssection and connectivity section. It also describes the thicknesses and physical attributes of the conductor and dielectric layers.

 *.map - Mapping file. This file aligns names in the vendor technology file with the names in the process *.itf file.

 *.tluplus - TLU+ file. These files are generated from the *.itf files. TLUPlus models are a set of models containing advanced process effects that can be used by the parasitic extractors in Synopsys place-and-route tools for modeling.

 *.spef - Standard Parasitic Exchange Format. File format to save parasitic information extracted by the place and route tool.

 *.sbpf - Synopsys Binary Parasitic Format. A Synopsys proprietary compressed binary format of the *.spef. Size of the file shrinks quite a bit using this format.

*.mw( Milkyway database) The Milkyway database consists of libraries that contain information about your design. Libraries contain information about design cells, standard cells, macro cells, and so on. They contain physical descriptions, such as metal, diffusion, and polygon geometries. Libraries also contain logical information (functionality and timing characteristics) for every cell in the library. Finally, libraries contain technology

information required for design and fabrication. Milkyway provides two types of libraries that you can use: reference libraries and design libraries. Reference libraries contain standard cells and hard or soft macro cells, which are typically created by vendors. Reference libraries contain physical information necessary for design implementation. Physical information includes the routing directions and the placement unit tile dimensions, which is the width and height of the smallest instance that can be placed. A design library contains a design cell. The design cell might contain references to multiple reference libraries (standard cells and macro cells). Also, a design library can be a reference library for another design library. The Milkyway library is stored as a UNIX directory with subdirectories, and every library is managed by the Milkyway Environment. The top-level directory name corresponds to the name of the Milkyway library. Library subdirectories are classified into different views containing the appropriate information relevant to the library cells or the designs. In a Milkyway library there are different views for each cell, for example, NOR1.CEL and NOR1.FRAM. This is unlike a .db formatted library where all the cells are in a single binary file. With a .db library, the entire library has to be read into memory. In the Milkyway Environment, the Synopsys tool loads the library data relevant to the design as needed, reducing memory usage. The most commonly used Milkyway views are CEL and FRAM. CEL is the full layout view, and FRAM is the abstract view for place and route operations.

 simv - Compiled simulator. This is the output of vcs. In order to simulate, run the simulator by ./simv at the command line.

 alib-52 - characterized target technology library. A pseudo library which has mappings from Boolean functional circuits to actual gates from the target library. This library provides Design Compiler with greater flexibility and a larger solution space to explore tradeoffs between area and delay during optimization.

VLSI Short Forms

ASIC Application Specific Integration CircuitATPG Automatic Test Pattern GenerationAOCV Advance On Chip VariationBC Best CaseCCS Composite Current SourceCG Composite GrainCMP Chemical Mechanical PlanarizationCTS Clock Tree Synthesis CAD Computer Aided DesignDDC Design Compiler Database (Synopsys specific)DEF Design Exchange FormatDFM Design For ManufactureDRC Design Rule Check DFT Design For TestDSPF Detailed Standard Parasitic FormatECO Engineering Change OrderEM Electro magneticESD Electro-Static DischargeEDA Electronic Design automation

EDIF Electronic Design Interchange FormatGDSII Graphic Data System IIHVT High VtHDLs Hardware Descriptive language IMD Inter-Metal DielectricILD Inter Layer DielectricIO Input OutputITF Interconnect Technology FileIC Integrated CircuitLEF Library Exchange FormatLIB LibraryLVS Layout Vs SchematicLSI Low Scale IntegrationMCMMMulti-Corner Multi-ModeNDR Non default RuleNLDM Non-Linear Delay modelsOPC Optical Proximity CorrectionPG pin Power and Ground PinPLIB Physical LibraryPLL Phase Lock LoopPVT Pressure Voltage TemperaturePDEF Physical Design Exchange FormatQOR Quality Of ResultRAM Random Access memoryROM Read Only MemoryRDL Re-Distribution layerRTL Register Transfer LanguageRSPF Reduced Standard Parasitic FormatSAIF Switching Activity Interchange FormatSDF Standard Delay FormatSOC System On ChipSOI Silicon On InsulatorSPEF Standard Parasitic Exchange Format.SPICE Simulation Program for Integrated Circuits EmphasisSSI Small Scale IntegrationSPF Standard Parasitic FormatSBPF Synopsys Binary Parasitic FormatSDC Synopsys Design ConstraintTLF Timing Library FormatTTL Transistor-Transistor LogicTF Technology FileUPF Unified Power FormatULSI Ultra Large Scale IntegrationVHDL Verilog Hardware Descriptive languageVLSI Very large Scale Integration

Backend physical design Interview Questions

I have listed below a set of common interview questions asked mainly in interviews related to physical design or backend activities in ASIC or VLSI chip design process. Typically these interviews start with questions on physical design(PD) flow and goes on to deeper details.

* What is signal integrity? How it affects Timing?

* What is IR drop? How to avoid .how it affects timing?

* What is EM and it effects?

* What is floor plan and power plan?

* What are types of routing?

* What is a grid .why we need and different types of grids?

* What is core and how u will decide w/h ratio for core?

* What is effective utilization and chip utilization?

* What is latency? Give the types?

* What is LEF?

* What is DEF?

* What are the steps involved in designing an optimal pad ring?

* What are the steps that you have done in the design flow?

* What are the issues in floor plan?

* How can you estimate area of block?

* How much aspect ratio should be kept (or have you kept) and what is the utilization?

* How to calculate core ring and stripe widths?

* What if hot spot found in some area of block? How you tackle this?

* After adding stripes also if you have hot spot what to do?

* What is threshold voltage? How it affect timing?

* What is content of lib, lef, sdc?

* What is meant my 9 track, 12 track standard cells?

* What is scan chain? What if scan chain not detached and reordered? Is it compulsory?

* What is setup and hold? Why there are ? What if setup and hold violates?

* In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?

* How R and C values are affecting time?

* How ohm (R), fared (C) is related to second (T)?

* What is transition? What if transition time is more?

* What is difference between normal buffer and clock buffer?

* What is antenna effect? How it is avoided?

* What is ESD?

* What is cross talk? How can you avoid?

* How double spacing will avoid cross talk?

* What is difference between HFN synthesis and CTS?

* What is hold problem? How can you avoid it?

* For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?

* What is partial floor plan?

* What parameters (or aspects) differentiate Chip Design & Block level design??

* How do you place macros in a full chip design?

* Differentiate between a Hierarchical Design and flat design?

* Which is more complicated when u have a 48 MHz and 500 MHz clock design?

* Name few tools which you used for physical verification?

* What are the input files will you give for primetime correlation?

* What are the algorithms used while routing? Will it optimize wire length?

* How will you decide the Pin location in block level design?

* If the routing congestion exists between two macros, then what will you do?

* How will you place the macros?

* How will you decide the die size?

* If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?

* If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?

* In your project what is die size, number of metal layers, technology, foundry, number of clocks?

* How many macros in your design?

* What is each macro size and no. of standard cell count?

* How did u handle the Clock in your design?

* What are the Input needs for your design?

* What is SDC constraint file contains?

* How did you do power planning?

* How to find total chip power?

* How to calculate core ring width, macro ring width and strap or trunk width?

* How to find number of power pad and IO power pads?

* What are the problems faced related to timing?

* How did u resolve the setup and hold problem?

* If in your design 10000 and more numbers of problems come, then what you will do?

* In which layer do you prefer for clock routing and why?

* If in your design has reset pin, then it’ll affect input pin or output pin or both?

* During power analysis, if you are facing IR drop problem, then how did u avoid?

* Define antenna problem and how did u resolve these problem?

* How delays vary with different PVT conditions? Show the graph.

* Explain the flow of physical design and inputs and outputs for each step in flow.

* What is cell delay and net delay?

* What are delay models and what is the difference between them?

* What is wire load model?

* What does SDC constraints has?

* Why higher metal layers are preferred for Vdd and Vss?

* What is logic optimization and give some methods of logic optimization.

* What is the significance of negative slack?

* How the width of metal and number of straps calculated for power and ground?

* What is negative slack ? How it affects timing?

* What is track assignment?

* What is grided and gridless routing?

* What is a macro and standard cell?

* What is congestion?

* Whether congestion is related to placement or routing?

* What are clock trees?

* What are clock tree types?

* Which layer is used for clock routing and why?

* What is cloning and buffering?

* What are placement blockages?

* How slow and fast transition at inputs effect timing for gates?

* What is antenna effect?

* What are DFM issues?

* What is .lib, LEF, DEF, .tf?

* What is the difference between synthesis and simulation?

* What is metal density, metal slotting rule?

* What is OPC, PSM?

* Why clock is not synthesized in DC?

* What are high-Vt and low-Vt cells?

* What corner cells contains?

* What is the difference between core filler cells and metal fillers?

* How to decide number of pads in chip level design?

* What is tie-high and tie-low cells and where it is used

Soft Macro Vs Hard macro?

Soft macro Vs Hard macro?

Soft macro and Hard macro are categorized as IP's while being optimized for power, area and performance. When buying IP and evaluation study is usually made to weigh advantages and disadvantages of one type of macro over the other like hardware compatibility issues like the different I/O standards within the design, and compatibility to reuse methodology followed by design houses.

Soft macros?

Soft macros are used in SOC implementations. Soft macros are in synthesizable RTL form, are more flexible than Hard macros in terms of reconfigurability. Soft macros are not specific to any manufacturing process and have the disadvantage of being unpredictable in terms of timing, area, performance, or power. Soft macros carry greater IP protection risks because RTL source code is more portable and therefore, less easily protected than either a netlist or physical layout data. Soft macros are editable and can contain standard cells, hard macros, or other soft macros.

Hard macro?

Hard macos are targeted for specific IC manufacturing technology. They are block level designs which are optimized for power or area or timing and silicon tested. While accomplishing physical design it is possible to only access pins of hard macros unlike soft macros which allows us to manipulate the RTL. Hard macro is a block that is generated in a methodology other than place and route ( i.e. using full custom design methodology) and is imported into the physical design database (eg. Volcano in Magma) as a GDS2 file.

Note:

Firm macros are in netlist format and are optimized for performance,area and power using a specific technology node. Firm macros are more flexible and portable than hard macros. Firm macros are more predictable in terms of performance and area when comparing with soft macros.

2of3 majority gates: