Diff Between Pakage and Include

Another frequently asked question: Should I import my classes froma package or `include them? To answer this properly, you need toknow more about SystemVerilogs type system, especially thedierence between its strong and weak typing systems.In programming languages, weak typing is characterized by implicit or ad-hocconversions without explicit casting between values of dierent data types.Verilogs bit vectors, or integral types, represent these weak typing aspects byimplicitly padding and truncating values to be the proper bit lengths at leastproper by Verilog standards. If you perform a bitwise AND of a 7-bit and 8-bitvector, Verilog implicitly zero pads an 8th bit to the 7-bit operand and returns an8-bit result. In contrast using VHDL, you would have to explicitly state whetheryou wanted the 7-bit operand to be padded, or the 8-bit operand to be truncatedso that you have an expression with operands of equal size.

With a few exceptions, all other types in SystemVerilog follow strong typingrules. Strong typing rules require explicit conversions or casts when assigning orexpressing operands of unequal types. And understanding what SystemVerilogconsiders equivalent types is key to understanding the eect of importing a classfrom a package versus including it from a le.

Inheritance aside, SystemVerilog uses the name of a type alone to determine typeequivalence of a class. For example, suppose I have these two class denitions Aand B below:

class A;int i;endclass : A

class B;int i;endclass : B

SystemVerilog considers these two class denitions unequal types because theyhave dierent names, even though their contents, or class bodies, are identical.The name of a class includes more than just the simple names A and B; thenames also include the scope where the denition is declared. When you declarea class in a package, the package name becomes a prex to the class name:

package P;class A;int i;endclass : AA a1;endpackage : P

package Q;class A;int i;endclass : AA a1;endpackage : Q

Now there are two denitions of class A, one called P::A and the other calledQ::A. And the variables P::a1 and Q::a1 are type incompatible referencing twodierent class As. Re-writing the above example using an include le creates the

SystemVerilog Coding Guidelines: Package import versus`include

VERIFICATION HORIZONS BLOG

Share

Posted July 13th, 2010, byDave Rich

IEEE 1800, S, SystemVerilog,Verication

21 Comments

POST AUTHOR

POST TAGS

POST COMMENTS

This blog will provide anonline forum to provideweekly updates onconcepts, values,standards, methodologiesand examples to assistwith the understanding ofwhat advanced functionalverication technologiescan do and how to mosteectively apply them.We're looking forward toyour comments andsuggestions on the poststo make this a useful tool.

ABOUT VERIFICATIONHORIZONS BLOG

@dennisbrophyTweets

54 minutes ago

about 23 hours ago

2 days ago

I love @Uber_SF! Sign upusing my promo code andget $20 o your rst ride:http://t.co/hiGLZk6GRQ

After 37 years, we haveTriple Crown Winner!http://t.co/qoRysr22RI

RT @IEEESA: GuidingTechnology Policy for theInternet: An IEEE initiativewill focus on governance,#cybersecurity privacy http://t.co/

same situation two incompatible class denitions.

File A.sv File P.sv File Q.sv


package P;ìnclude A.sv"A a1;endpackage : P

package Q;ìnclude A.sv"A a1;endpackage : Q

After ìncluding class A into each package, you wind up with two denitions ofclass A. Using ìnclude is just a shortcut for cut and pasting text in a le.Importing a name from a package does not duplicate text; it makes that namevisible from another package without copying the denition.

File A.sv File P.sv File R.sv File S.sv


package P;ìnclude A.sv"endpackage : P

package R;import P::A;A a1;endpackage : R

package S;import P::A;A a1;endpackage : S

Class A is declared in package P, and only in package P. The variables R::a1 andS::a1 are type compatible because they are both of type P::A. The fact that classA was ìncluded from another le once it is expanded is no longer relevant onceyou consider the placement of the text from the le.

When you get compiler errors claiming that two types are incompatible eventhough they appear to have the same name, make sure you consider the scopewhere the types are declared as part of the full name. Class names declared in amodule are prexed by the module instance name, so the same moduleinstantiated multiple times will create unique class names, all incompatible types.

For further information about packages, check out the June VericationHorizons article entitled Using SystemVerilog Packages in Real VericationProjects.

Dave Rich

2 days ago

Follow Follow @dennisbrophy@dennisbrophy

RT @Gizmodo: The world'srst 10K TV is here and it'stotally unnecessaryhttp://t.co/Yj4tZXPAGdhttp://t.co/yESLNHupDL

@dave_59 Tweets

1 day ago

2 days ago

2 days ago

9 days ago

Follow Follow @dave_59@dave_59

RT @mentor_graphics:The Mixels are making theirway to San Francisco for#52DAC! Get yoursMonday-Wednesday atMentor booth 1432http://t.

Stop by and say hi@52ndDAC VericationAcademy Booth 2408 June8-9th 3-6 both days. Bring agood #SystemVerilog or#UVM question

RT @dennisbrophy: ItsTime for a New VericationDebug Data API. Learnmore at #52DACVerication Academy Booth2408 June 9th 5pm. http:

RT @DoulosLtd: NextDoulos training webinar:#SystemVerilog Synthesisfor @XilinxInc FPGAs.Register now for free!http://t.co/of0dmdIvcI

@jhupcey Tweets

2 days ago

RT @mentor_graphics:The Mixels are making theirway to San Francisco for#52DAC! Get yoursMonday-Wednesday atMentor booth 1432http://t.

"Yikes - #52DAC is Mondayand I haven't asked myboss for time o!" NP - usethe Justication Toolkit nowhttp://t.co/J1YeeIz0Qa#SemiEDA

2 days ago

4 days ago

10 days ago

Follow Follow @jhupcey@jhupcey

@mentor_graphics' MarkEslinger putting thenishing touches on his#52DAC VericationAcademy presentation nextwkhttp://t.co/OBvaDthmw6

#52DAC is in 2 weeks &Uhaven't spoken to UR bossyet? NP: use the coverletter &points in theJusticationToolkit:https://t.co/8z0y7FQHCs

LinksARM SoC DesignGabe on EDAOVM ForumSystemVerilog ForumThe Standards GameUVM ForumVerication Guild

MORE BLOG POSTS

The reports of OVMs death are greatly exaggerated (withapologies to Mark Twain)

Redening Verication Performance (Part 1)

21 comments on this post | Add Your Own

Commented on July 13, 2010 at 11:11 pmBy Greg Jaxon

Excellent illustration, Dave!

What you say about classes also applies to most structs, unions, and enums, too.

One situation to watch is `includes into the $unit scope (outside any module or other part description).Whether the same include le brought into the $unit scope of distinct les can create matching types is adelicate matter; users probably should not expect SV implementations to agree on every case of this.

Good thing packages are so easy to use to get this right!

Commented on July 17, 2010 at 11:34 amBy Vishnu

COMMENTS

Excelent Article Dave

Commented on February 8, 2011 at 6:57 amBy Pranav Joshi

This is an excellent piece of explanation. I must use this to train engineers of my team.

Commented on June 28, 2011 at 5:07 pmBy geonerstiem

thanks

Commented on July 7, 2011 at 1:40 amBy MBS

good article, thanks or sharing, Dave.

Commented on September 9, 2011 at 12:00 pmBy Mark Curry

In the nal solution why bother using the include at all? The les not included anywhere else just putthe denition in the P package and be done with it.

Commented on September 9, 2011 at 1:02 pmBy Dave Rich

Hi Mark,When you package starts having class A, B, C, etc. you need separate les for better revision control.Then ìnclude shows the required le dependencies and compilation order.

Commented on April 16, 2012 at 3:42 pmBy omer

Hello Dave,

Thank you very much for progressive explanation. I have been trying to understand the dierencebetween the two a while now as I am new to OOP.

Take care

Commented on September 12, 2012 at 10:01 amBy Dave Rich

You can certainly use extern to separate class declarations from method declarations, but the methodsmust be dened before closing the scope. So everything has to be inside the package.For examplepackage p;ìnclude myclass_declarations.svhìnclude myclass_methods.svhendpackage

Commented on July 3, 2013 at 9:57 pmBy MBC

Hi Dave,

can you give an example of how P::A is type incompatible with Q::A (when you are showing the eects ofìnclude).

It would be nice if you can show a snippet of code that demonstrates the type incompatibility issuebetween the two variables.

Commented on July 8, 2013 at 7:15 amBy Dave Rich

Shaun,

The code shown in the example showing the eects of ìnclude behaves exactly as the previous examplewhere package P and Q are dened without ìnclude. So if you had

P::A handle_a1;Q::A handle_a2;handle_a1 = new();handle_a2=handle_a1; // this is illegal

Commented on September 16, 2013 at 2:40 pmBy Linh Nguyen

Very clear, thank you!

Commented on January 21, 2014 at 6:24 amBy Surya

HI Dave,

Thats a great explanation. Here is some issue I am facing with my compiler (vcs):

package test_lib_pkg;

import uvm_pkg::*;ìnclude uvm_macros.svh

import bus_agent_pkg::*;import bus_seq_lib_pkg::*;

ìnclude bus_test_base.sv

endpackage

My compiler give me an error saying, le could not be found when this included le is not in the same diras my Makele is, or else if both are in the same dir it comiples without error. Now how do I tell mycompiler to look into the same dir where my pakage les are ?

Commented on January 21, 2014 at 8:17 amBy Dave Rich

This is a tool issue, not a language issue. Please contact your vendor for support.

Commented on April 24, 2014 at 10:18 amBy Soha Sayed

Thank you DAVE .. you are a life saver .. CHAPEAU!

Recent PostsIts Time for a New Verication Debug Data

ArchivesJune 2015

TagsStandards

Commented on May 27, 2014 at 12:18 amBy mukesh

Hi Dave,Thanx for ur wonderful explanation .

Commented on August 26, 2014 at 9:04 amBy Cadence stops support for importing packages in class ? | eecad

[] http://blogs.mentor.com/vericationhorizons/blog/2010/07/13/package-import-versus-include/ []

Commented on September 20, 2014 at 8:23 amBy Christopher

Thanks for nally talking about > SystemVerilog CodingGuidelines: Package import versus ìnclude

Commented on March 10, 2015 at 7:46 pmBy SystemVerilog Coding Guidelines: Package import versus ìnclude Verication Horizons BLOG ASIC Craftsman ()

[] SystemVerilog Coding Guidelines: Package import versus ìnclude Verication Horizons BLOG. []

Commented on March 13, 2015 at 12:59 amBy Yogaraj

Hi Dave,Can you explain me the relationship between comparison scope and comparison unit with respect toimport package and include

Commented on March 16, 2015 at 9:55 amBy Dave Rich

Hi Yogaraj,

I assume you meant compilation not comparison. If so, please read http://go.mentor.com/unit-vs-rootand let me know if you have more questions. And remember, ìnclude is just a text processor that knowsnothing about the text it is including.

Add Your Comment Name (required)

Mail (will not be published) (required)

Submit Comment

API (DDA)Accellera Portable Stimulus Working GroupAccepting Technology ContributionsPart 6: The 2014 Wilson Research GroupFunctional Verication StudyAn Agile Evolution in SoC Verication Panel@ DACUVM Debug. A contest using class basedtestbench debugNo to Know VIPPart 5: The 2014 Wilson Research GroupFunctional Verication StudyASYNC 2015: The Most Important CDCConference Youve Never Heard OfVerication Academy: The Place to Meet atDACPart 4: The 2014 Wilson Research GroupFunctional Verication Study

May 2015UVM Debug. A contest using class based

testbench debug

No to Know VIP

Part 5: The 2014 Wilson Research GroupFunctional Verication Study

ASYNC 2015: The Most Important CDCConference Youve Never Heard Of

Verication Academy: The Place to Meetat DACApril 2015


DVCon, Reuse, and Software-DrivenVerication

Do Formal Apps Help D&V EngineersCross the Chasm Into Direct FormalProperty Checking? This Oracle Case StudySuggests They Do (Part 2 of 2)

Do Formal Apps Help D&V EngineersCross the Chasm Into Direct FormalProperty Checking? This Oracle Case StudySuggests They Do (Part 1 of 2)

20 Years Ago 10 Years Ago Tomorrow(DAC)

Part 3: The 2014 Wilson Research GroupFunctional Verication StudyMarch 2015

March 2015 Edition of VericationHorizons Available Online!

Part 2: The 2014 Wilson Research GroupFunctional Verication StudyFebruary 2015

Is Gate-Level Simulation Still RequiredNowadays??

From Tightly Coupled (Loosely Bolted) toVerication Convergence!

Portable Stimulus at DVCon

Portable Stimulus: A Small Step inStandardization

Part 1: The 2014 Wilson Research GroupFunctional Verication StudyJanuary 2015

Understanding and Minimizing Study Bias

Prologue: The 2014 Wilson ResearchGroup Functional Verication Study

Who Knew VIP?

3 Notable Formal-Related ConferencePapers of 2014December 2014

Latest Issue of Verication HorizonsAvailable!November 2014

SystemVerilog Testbench Debug Are wehaving fun yet?

ARM Techcon Paper Report: HowMicrosoft Saved 4 Man-Months MeetingTheir Coverage Closure Goals UsingAutomated Verication Management &Formal Apps

Preparing for the Perfect Storm withNew-School Verication Techniques

MORE

SystemVerilogUVMAccellerafunctional vericationVericationVerication AcademyOVMIEEESimulation

Its Time for a New Verication Debug DataAPI (DDA)

Accellera Portable Stimulus Working GroupAccepting Technology Contributions


An Agile Evolution in SoC Verication Panel@ DAC

On-Demand Webinar: UVM Sequences inDepthOctober 2014

DVCon India: A Smashing Hit!September 2014

Portable and Productive Test Creationwith Graph-Based Stimulus

Supporting A Season of LearningAugust 2014

DVCon Goes Global!

Better Late Than Never: MagicalVerication Horizons DAC EditionJuly 2014

Accellera Approves UVM 1.2May 2014

Getting More Value from your StimulusConstraints

The FPGA Verication Window Is OpenApril 2014

UVM DVCon 2014 Tutorial Video Online

Mentor Enterprise Verication PlatformDebutsMarch 2014

New Verication Academy ABV Course

DVCon 2014 Issue of VericationHorizons Now AvailableFebruary 2014

DVConThe FREE Side

More DVConMore Mentor Tutorials!

UVM 1.2: Open Public Review

DVCon 2014: Standards on Display

Just because FPGAs are programmabledoesnt mean verication is deadJanuary 2014

Managing Verication CoverageInformationNovember 2013

Epilogue: The 2012 Wilson ResearchGroup Functional Verication Study

New Verication Horizons Issue AvailableOctober 2013

Happy Halloween from ARM TechCon

IEEE Standards Association Symposiumon EDA Interoperability

STMicroelectronics: Simulation +Emulation = Verication SuccessSeptember 2013

A Decade of SystemVerilog: UnifyingDesign and Verication?

Part 12: The 2012 Wilson Research GroupFunctional Verication StudyAugust 2013




Part 8: The 2012 Wilson Research GroupFunctional Verication StudyJuly 2013


Walking in the Desert or Drinking from aFire Hose?


A Short Class on SystemVerilog Classes


Part 4: The 2012 Wilson Research GroupFunctional Verication StudyJune 2013


Part 2: The 2012 Wilson Research GroupFunctional Verication StudyMay 2013

Texas-Sized DAC Edition of VericationHorizons Now Up on Verication Academy

IEEE 1801-2013 UPF Standard IsPublished


Whats the deal with those wires andregs in VerilogApril 2013

Getting AMPed Up on the IEEE Low-Power Standard

Prologue: The 2012 Wilson ResearchGroup Functional Verication StudyMarch 2013

Even More UVM Debug in Questa 10.2

IEEE Approves New Low Power StandardFebruary 2013

Verication Horizons DVCon Issue NowAvailable

Get your IEEE 1800-2012 SystemVerilogLRM at no charge

IEEE 1800-2012 SystemVerilog StandardIs Published

See You at DVCon 2013!

Get Ready for SystemVerilog 2012January 2013

VHDL Update Comes to VericationAcademy!December 2012

IEEE Approves Revised SystemVerilogStandardNovember 2012

Coverage Cookbook DebutsOctober 2012

IoT: Internet of Things

Check out the October, 2012 VericationHorizons

Improving simulation results with formal-based technology

Introducing Verication Academy 2.0September 2012

OVM Gets ConnectedAugust 2012

OpenStand & EDA StandardizationJuly 2012

Synthesizing Hardware Assertions andPost-Silicon Debug

Virtual Emulation for Debugging

Verication Academy: Up Close &Personal

SystemC Standardization CycleCompletes

Verication Standards Take Another StepForward

New UVM Recipe of the Month:Scoreboarding in UVMJune 2012

Intelligent Testbench Automation Catching on FastMay 2012

Two Articles You Need to Check Out

O to DAC!

Dave Rich Featured on EEWebMarch 2012

How Did I Get Here?February 2012

Expanding the Verication Academy!

Get on the Fast Track to AdvancedVerication with UVM Express

Introducing UVM Connect

Tornado Alert!!!

UVM: Some Thoughts Before DVCon

UVM at DVCon 2012January 2012

SystemC 2011 Standard Published

Verication solutions that help reducebug costDecember 2011

Instant Replay for Debugging SoC LevelSimulations

2011 IEEE Design Automation StandardsAwardsNovember 2011

Getting started with the UVM Using theRegister Modeling package

TLM Becomes an IEEE StandardOctober 2011

Worlds Standards Day 2011

VHS or Betamax?

Verication Issues Take Center StageSeptember 2011

New UVM Recipe-of-the-Month: SequenceLayeringJuly 2011

Combining Intelligent TestbenchAutomation with Constrained RandomTesting

Going from Standards Development toStandards Practice

Verication Academy Now IncludesOVMWorld ContentJune 2011

Intelligent Testbench AutomationDelivers 10X to 100X Faster FunctionalVerication


Verication Horizons DAC Issue NowAvailable Online

Accellera & OSCI Unite

The IEEEs Most Popular EDA Standards

UVM Register Kit Available for OVM 2.1.2May 2011


Getting Your Standards Update @ DAC

2011April 2011

User-2-Users Functional VericationTrack



SystemC Day 2011 Videos Available Now



Part 3: The 2010 Wilson Research GroupFunctional Verication StudyMarch 2011



Prologue: The 2010 Wilson ResearchGroup Functional Verication Study

Language Transitions: The Dawning ofAge of Aquarius

Using the UVM libraries with QuestaFebruary 2011

DVCon: The Present and the Future

Free at Last! UVM1.0 is Here!

Parameterized Classes, Static Membersand the Factory Macros

IEEE Standards in IndiaJanuary 2011

Accellera Approves New Co-EmulationStandardDecember 2010

New Verication Horizons: MethodologiesDont Have to be Scary

The Survey Says: Verication PlanningOctober 2010

Towards UVM Register PackageInteroperability

IECs 47th General Assembly MeetingOpens

UVM: Giving Users What They WantSeptember 2010

UVM Takes Shape in the Accellera VIP-TSC

Accellera VIP-TSC Selects RAL for UVM1.0 Register Package

OVM Cookbook Available fromOVMWorld.org

UVM Register Package Candidate NewsAugust 2010

Redening Verication Performance (Part2)July 2010

Making formal property checking easy touse

Redening Verication Performance (Part1)

SystemVerilog Coding Guidelines:Package import versus `includeJune 2010

The reports of OVMs death are greatlyexaggerated (with apologies to MarkTwain)

New Verication Academy Advanced OVM

(&UVM) Module

OVM/UVM @DAC: The Dog That DidntBark

DAC: Day 1; An Ode to an Old Friend

UVM: Joint Statement Issued by Mentor,Cadence & Synopsys

Static Verication

OVM/UVM at DAC 2010

DAC Panel: Bridging Pre-SiliconVerication and Post-Silicon Validation

Accelleras DAC Breakfast & PanelDiscussionMay 2010

Easier UVM Testbench Construction UVM Sequence Layering

North American SystemC User Group(NASCUG) Meeting at DAC

An Extension to UVM: The UVM Container

UVM Register Package 2.0 Available forDownload

Accelleras OVM: Omnimodus VericationMethodology

High-Level Design Validation and Test(HLDVT) 2010

New OVM Sequence Layering Package For Easier Tests

OVM 2.0 Register Package Released

OVM Extensions for Testbench ReuseApril 2010

SystemC Day Videos from DVConAvailable Now

On Committees and Motivations

The Final Signatures (the meeting duringthe meeting)

UVM Adoption: Go Native-UVM or useOVM Compatibility Kit?

UVM-EA (Early Adopter) Starter KitAvailable for Download

Accellera Adopts OVM 2.1.1 for itsUniversal Verication Methodology (UVM)March 2010

The Art of Deprecation

OVM 2.1.1 Now Ready for Download

February 2010 Verication HorizonsNewsletter Now Available

IEEE Standards Meetings in IndiaFebruary 2010

I Do It

SystemVerilog: A time for change? Maybenot.

Partners Oer Support for OVM 1.0Register Package

SystemC Day at DVCon

OVM/VMM Interoperability Kit: Its Ready!January 2010

Three Perfect 10s

OVM 1.0 Register Package Released

Accellera Adopts OVM

SystemC (IEEE Std. 1666) Comes toYouTube

Debugging requires a multifacetedsolutionDecember 2009

A Clihanger ABV Seminar, Jan 19, SantaClara, CA

Truth in Labeling: VMM2.0

IEEE Std. 1800-2009 (SystemVerilog)Ready for Purchase & Download

December Verication Horizons Issue Out

Evolution is a tinkerer

It Is Better to Give than It Is to Receive

Zombie Alert! (Can the CEDA DTC UserVoice Be Heard When They Wont Let YouListen)

DVCon is Just Around the Corner

The Standards Corner Becomes a Blog

I Am Honored to Honor

IEEE Standards Association AwardsCeremony

ABV and being from Missouri

Time hogs, blogs, and evolvingunderdogs

Full House and this is no gamble!

Welcome to the Verication HorizonsBlog!September 2009

SystemVerilog: The ner details of $unitversus $root.

SystemVerilog Coding GuidelinesJuly 2009

The Language versus The MethodologyMay 2009

Are Program Blocks Necessary?

Diff Between Pakage and Include

Documents

Transcript of Diff Between Pakage and Include