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DFM: A Foundry Perspective on the Need for Standards

Tim Farrell, IBM27 September 2006

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Agenda

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Base Assumptions

� We all want to make money.

� Foundry

� EDA

� Fabless semiconductor makers.

� Reduced cost contributes to profitability.

� Competition spurs lower cost.

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Farrell’s corollary:

We will not harm the design in pursuit of DFM !

The Goal of DfM

Improve product profitability in light of increasing design- and process-complexity by optimizing tradeoffs between design- and process-cost, layout-density, chip-performance and -power, wafer-yield, and manufacturing-risk.

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Current Environment

� The Foundry� Process models are notoriously numerically inefficient.

� Process models primarily support unit process development.

� Process models if applied to design is usually done post design (eg. OPC, wire spreading).

� Enables use of COT.

� Fabless design� Design flows often use a variety of point use tools.

� Highly variable priorities: density, performance, low power, etc..

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Evolution of Design Focus and Kits

0.25um0.35um 65nm90nm0.13um0.18um

SI Integrity

Power Optimization

Rule BaseDFM

45nm

Model BaseDFM

Reference Flows &Design Enablement Kit• DRC• LVS• PEX

DFM Rule & Utility Kit• DFM Guidelines• DFM DRC rules• DFM P&R tech file• DFM utilities

DFM Model Kit• Defect Model• Litho Model• CMP Model• Statistical Model

Design Kits Road Map

For random yield

For systematic yield

For parametric yield

Timing Closure

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DFM Solutions in Today�s Design Flows

Data Preparation

Chip Design

Cell / IP Design

Fail

Layout Modification

Layout Modification

OPC Optimization

OPC Optimization

Shape simulationShape

simulation

Mask tape-outMask tape-out

Pass

GDS IIGDS II

OPCOPC

ORCORC

Power Calculation

Power Calculation

Timing ClosureTiming Closure

Cell DesignCell Design

Place & RoutingPlace & Routing

Cell / IP DFM Review• Yield Analyzer (Mentor)

- DFM Checking Deck at Cell Level

• Yield Analyzer (Ponte)- CAA at Cell Level

• Calibre LFD (Mentor)- LFD at Cell level

Cell / IP DFM Review• Yield Analyzer (Mentor)

- DFM Checking Deck at Cell Level

• Yield Analyzer (Ponte)- CAA at Cell Level

• Calibre LFD (Mentor)- LFD at Cell level

DFM Optimization.

• Blaze MO (Blaze)- Leakage reduction & Yield

Optimization

DFM Optimization.

• Blaze MO (Blaze)- Leakage reduction & Yield

Optimization

Physical Implementation• SOC Encounter (Cadence)• BlastFusion (Magma)• Astro (Synopsys)- OPC aware P&R

• CMP Simulation (Cadence)

Physical Implementation• SOC Encounter (Cadence)• BlastFusion (Magma)• Astro (Synopsys)- OPC aware P&R

• CMP Simulation (Cadence)

Shape Simulation• In-shape (Clearshape)• Calibre LFD (Mentor)

- Chip Level shape simulation

Shape Simulation• In-shape (Clearshape)• Calibre LFD (Mentor)

- Chip Level shape simulation

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Implications of Model Based DFM

� Foundry� COT enablement could drive support of multiple process modeling

tools.� Release of sensitive process information.

� EDA suppliers� Information must now flow between point use tools.� Increased number of point use tools that will need to communicate with

each other.� Start-ups claiming new functionality and value.

� Fabless design:� May need to become the “integrator” if they do not use full flow

solutions available only from large EDA suppliers.� Increased complexity at introducing unique new value add point tools

Disruption – an additional degree of freedom resulting in an increase in the quantity of applications, suppliers, foundry data, information flow, and tool interactions that will need to be supported – COST !

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The do nothing option� Foundry implications:

� Process models required for each customer’s unique tools.

� Cost increased by the # of new tools & applications to be supported.

� Fabless design implications:� Integration (and support ?) between each new unique tool

combination.

� Increased cost at bringing on a second supplier.

� Increased inertia to be overcome should change be needed.

� EDA suppliers:� Implementation and support of communication between each

unique point tool combination.

� Inertia that prevents cooperation between competitors.

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Proprietary Standards Approach

� Foundry defined:� Increased cost for a fabless design team to pursue a

second supplier.

� Requires EDA to support multiple proprietary standards.

� Fabless designer defined:� Foundry required to support multiple redundant tools and

protocols.

� Requires EDA to support multiple proprietary standards.

� EDA defined:� Limited to suppliers with full design flow tool suite.

� Limits market opportunity.

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Open Standards Approach

� Standard interface:

� Eliminates need for EDA supplier supported multiple protocols.

� Facilitates innovation and introduction of new functionality.

� Decreased hurdle rate to introduce a second source foundry.

� Standard model forms per process operation:

� Minimizes foundry costs for model builds.

� Best utilizes existing information.

� EDA value add would be on the functions using the information.

� Specifications addressing the trade-off between run time and model accuracy are required.

� Inclusion of RETs, OPC, and cheese/fill ?

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Closing Remarks

� Model based DFM greatly increases the quantity of information to be used within a design flow and the number of tools that will need to interact with each other.

� Open standards can reduce the number of combinations requiring support to help enable introduction of model based DFM.

� Fewer combinations reduces the cost for all participants: EDA, Foundry, and Fabless Design.

� Standardization should enable innovation and collaboration.

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