Devices and Design Asic

7/30/2019 Devices and Design Asic

1/6

Abstract

This paper provides an overview of the steps involved in the application specific integrated

circuit (ASIC) design.

The first section, Introduction, defines ASIC and describes the various types of AISC design

processes.

The second section, Terminology, defines the key terms that are encountered during the design

process.

The third section, Methodology, covers the four major phases of ASIC design design entry

and analysis; technology optimization and floorplanning; design verification; and layout, and is

illustrated with real design examples.

The fourth and the last section, Fabrication, describes the fabrication

Introduction

Any IC other than a general purpose IC which contains the functionality of thousands of gates is

usually called an ASIC (Application Specific Integrated Circuit). An ASIC is a collection of logic

and memory circuits on a single silicon die. AISCs are used in a wide variety of products

ranging from consumer products such as video games, digital cameras, automobiles and

personal computer, to high-end technology products such as workstations and supercomputers.

The following paragraphs describe the types of AISCs.

1. Full-Custom ASIC: For this type of ASIC, the designer designs all or some of the logic

cells, layout for that one chip. The designer does not use predefined gates in the design.

Every part of the design is done from the scratch.


2/6

2. Standard Cell ASIC: The designer uses predesigned logic cells such as AND gate, NOR

gate, etc. These gates are called Standard Cells. The advantage of Standard Cell ASICs

is that the designers save time, money and reduce the risk by using a predesigned and

pre-tested Standard Cell Library. Also each Standard Cell can be optimized individually.

The Standard Cell Libraries are designed using the Full Custom Methodology, but you

can use these already designed libraries in the design. This design style gives a

designer the same flexibility as the Full Custom design, but reduces the risk.

3. Gate Array ASIC: In this type of ASIC, the transistors are predefined in the silicon wafer.

The predefined pattern of transistors on the gate array is called a base array and the

smallest element in the base array is called a base cell. The base cell layout is same for

each logic cell, only the interconnect between the cells and inside the cells is

customized. The following are the types of gate arrays:

a. Channeled Gate Array

b. Channel less Gate Array

c. Structured Gate Array

When designing a chip, the following objectives are taken into consideration:

1. Speed

2. Area

3. Power

4. Time to Market

Terminology

ASICs are logic chips designed to perform a specific function and thereby meet the specific

needs of their application. Designers implement their designs in a single silicon die by mapping

their functions to a set of predesigned, preverified logic circuits provided by the ASIC vendor.


3/6

These circuits are referred to as the ASIC vendors library, and are described in the ASIC

vendors databook. These circuits range from the simplest functions, such as inverters, NANDs

and NORs, flip-flops and latches, to more complex structures such as memory arrays, adders,

counters and phase-lock loops. Vendors keep on adding highly complex circuits to their ASIC

libraries. These complex designs are referred to as cores and are fast becoming a major

differentiator among ASIC vendors.

ASIC Vendor Selection Criteria

An ASIC designer, seeking to create a new design and select an appropriate ASIC vendor,

should consider the following criteria:

ASIC library content and characteristics:

The designer has to determine if the library contains the logic circuits needed to

implement the design and if the circuits are fast enough.

Design turn-around-time:

The time that will be taken by the ASIC vendor to fabricate, package, and test the part

once the design is completed.

Price of the die:

The amount the AISC will cost forms an important factor to all designers but varies

depending upon the market the AISC is intended to target.

Power consumption:

The importance of power utilization has greatly increased over the past several years,

and is very crucial in battery powered applications like cell phones and laptops.

Design methodology:

Design Views


4/6

During the course of the design process, the design data exists in several different formats or

views. As the design progresses, it becomes less abstract and more specific to, and optimized

for, a particular technology. Each step in the design methodology serves a different purpose and

requires unique tools. These views evolve through three major phases:

In the first phase, the design is realized primarily as a technology independent Hardware

Description Language (HDL), a format very similar to a programming language, to

describe the designs functionality.

In the second phase the design is realized as technology dependent netlist that consists

of a series of instances of circuits from the ASIC vendors library , interconnected in a

manner to implement the functionality described in the previous views.

In the last phase the design is realized as a physical view, in which the logic circuits

describes in the previous view are physically placed on a piece of silicon, called a die,

and interconnected by various layers of wiring.

Methodology

There are four basic steps that an ASIC must go through in order to create a working silicon:

1. design entry and analysis

2. technology optimization and floorplanning

3. design verification

4. layout

Design Entry

The designers first task is to describe the designs intended function. Typ ically this functionality

is specified in a document, which is written in a natural language such as English, in order to

facilitate its development as well as to make it accessible to review by all the team members.


5/6

Once the specification is finalized, the designer then translated the specification into a form that

can be understood by software tools in order to direct the creation of silicon. The two principal

design description methods are:

Hardware Description Language, generally used for larger designs, and

Schematic Capture, an older method, suitable for smaller designs, used less often today

The two dominant HDLs are Verilog and VHDL. Both are languages much like programming

languages, but they have been specifically designed specifically for describing hardware

behavior.

HDLs allow designers to describe the function of their designs at a higher level, often

independent of the eventual implementation in silicon.

With schematic capture, graphical representations of the logic functions are placed on a

computer screen and are manually connected by the designer. In this case the higher level

description possible with HDLs is sacrificed.

Design Entry Examples

Sampl e HDL

Sample Schematic

Design Analysis

After entering a design in an HDL, the designer begins the process of analyzing what was

entered to determine if it correctly implements the intended function. This is done through

simulation, which evaluates how a design behaves. Figure below represents the traditional

simulation process. The HDL, which describes the design function, is read into the simulator tool

along with a set of input vectors created by the designer. The simulator generates output


6/6

vectors that are captured and evaluated against a set of expected values. If the output values

match the expected values, then the simulation passes; if the output values differ, then the

simulation is said to fail and the design needs to be corrected.

Techn ology Optimizat ion

Technology optimization takes a technology independent description of a design, and maps it to

a library of logic circuits provided by an ASIC vendor, thereby making the design technology

dependent. The optimization process is divided into subprocesses: logic synthesis; test

insertion; clock planning and insertion; and floorplanning.

Devices and Design Asic

Documents

Transcript of Devices and Design Asic