Device and Circuit Simulation of Printed Polymer Electronics

Organic Electronics 8 (2007) 431–438

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Device and circuit simulation of printed polymer electronics

Matthias Bartzsch a,*, Heiko Kempa b, Michael Otto c, Arved Hubler a,Dirk Zielke d

a Chemnitz University of Technology, Institute for Print and Media Technology, Reichenhainer Strasse 70, D-09107 Chemnitz, Germanyb Fraunhofer Institute Reliability and Microintegration, Branch Lab Chemnitz Reichenhainer Strasse 88, D-09126 Chemnitz, Germany

c Printed Systems GmbH Altchemnitzer Strasse 27, D-09120 Chemnitz, Germanyd University of Applied Sciences Bielefeld, Department of Electrical Engineering and Information Technologies,

Wilhelm-Bertelsmann-Strasse 10, D-33602 Bielefeld, Germany

Received 23 October 2006; received in revised form 8 February 2007; accepted 13 February 2007Available online 20 February 2007

Abstract

For the electrical simulation of all printed polymer circuits an AIM-SPICE model was developed, which is based on ana-silicon approach. By fitting the parameters to the behaviour of our polymer devices, we obtain a model, which allows tomodel all-printed polymer transistors and circuits.� 2007 Elsevier B.V. All rights reserved.

PACS: 72.80.Le; 85.40.�e; 85.30.Tv

Keywords: Organic electronics; Printed electronics; Device simulation; Organic field effect transistor (OFET)

1. Introduction

The technology for printed organic electronicshas rapidly developed in recent years. First devicesand circuits for applications like RFID have beenpresented [1,2]. Due to intrinsic drawbacks oforganic materials compared to their inorganic coun-terparts in terms of electronic properties, futureapplications are foreseeable in fields where low-costmanufacture is more important than extremely highperformance [3]. Mass printing technologies are

1566-1199/$ - see front matter � 2007 Elsevier B.V. All rights reserved

doi:10.1016/j.orgel.2007.02.005

* Corresponding author. Tel.: +49 (0) 371 531 32126; fax: + 49(0) 371 531 23619.

E-mail address: [email protected] (M.Bartzsch).

most promising in this context, as their main advan-tage compared to other fabrication methods, e.g.lithographic structuring used in silicon-based indus-try, is the possibility to produce a huge amount ofsamples with one printing form [4].

To avoid a ‘‘trial and error strategy’’ whichwould involve the fabrication of many differentprinting forms, it is helpful to have some reliableand easy to use simulation tools for printed circuitsat hand. By means of simulations the device and cir-cuit layout can be verified and optimized withoutperforming a large number of cost and time con-suming experiments. In order to support our dailywork in roll-to-roll printing of organic circuits, wehave developed an easy to use and easy to parame-terize model which describes the static and dynamic

.

mailto:[email protected]

432 M. Bartzsch et al. / Organic Electronics 8 (2007) 431–438

behaviour of organic devices and circuits with suffi-cient accuracy.

2. Experimental

Our transistors and circuits were fabricated solelyby means of fast, continuous mass-printing pro-cesses on a printing machine which was especiallydesigned and set up for the purpose of printing elec-tronic devices (Fig. 1). The machine is capable of allconventional mass-printing techniques due to itsmodular setup, i.e. offset, flexographic and gravureprinting and has a small web width of 35 mm inorder to work with small amounts of experimentalmaterials.

The thin-film transistors (TFTs) are built up intop-gate configuration on a PET-substrate. Sourceand drain electrodes are offset printed from are-formulation of a water-based dispersion of poly-(3,4-ethylenedioxythiophene) doped with poly-(styrene-sulfonate) (PEDOT:PSS, Baytron P�).Poly(9,9-dioctylfluorene-co-bithiophene) (F8T2)solved in xylene was gravure printed as semicon-ducting layer. For the gate dielectric a double layerapproach with a low-k and a high-k dielectric wasused [5]. Veres et al. [6] found that a semiconduc-tor/low-k dielectric interface shows superior proper-ties in terms of field effect mobility compared tosemiconductor/high-k dielectric interfaces. Thiseffect has also been observed in our device setup[5]. However, due to the high roughness of oursource/drain structures, an additional layer of a

Fig. 1. Laboratory printing machine for the fabrication of all-printed electronic devices.

high-k dielectric material has been deposited ontop of the low-k dielectric in order to guarantee suf-ficient insulation and capacitance. A combination ofgravure and flexographic printing processes wasused to deposit the dielectrics. The gate electrodeswere manually dispensed from carbon black. Detailsof the involved printing processes will be describedelsewhere [7].

The transistors had a channel length of 100 lmand a channel width of 30,000 lm. In order to dem-onstrate the applicability of our model for logic cir-cuits we have chosen a seven-stage ring oscillator asa demonstrator (Fig. 2). The ring oscillator incorpo-rated eight inverter stages, where one of them wasused as a buffer stage for uncoupling of the signal.Each inverter stage consisted of a load and a drivetransistor with a channel width of 6000 lm and30,000 lm, respectively. The channel length was100 lm for both the load and the drive transistor.

Standard characterizations of the individualTFTs and inverter stages were carried out usingtwo Keithley source meters, whereby the measuredtransistors and inverters, respectively, were electri-cally separated from the surrounding circuitry.The ring oscillator signal was traced with a Keithleysource meter controlled by an appropriate software,making use of its large input impedance. All mea-surements were carried out in a Suess Microtechprobe station.

Fig. 3 shows the output characteristics variationof the D-TFTs of an oscillator circuit. The variationof approx. 25% in the output characteristics ismainly a consequence of two effects. The first oneis the non-uniformity of the semiconducting layerwhich causes voids because of wetting problems.Because of this effect the effective channel width isreduced. The second effect that influences the varia-

Fig. 2. Circuitry of the seven-stage ring oscillator (top) andschematic of a printed ring oscillator (bottom).

Fig. 3. Output characteristics of the D-TFTs at VGS = �60 V.

M. Bartzsch et al. / Organic Electronics 8 (2007) 431–438 433

tion of transistor characteristics is the variation inthe thickness of the insulating layer.

2.1. Device model

For the simulation of the behaviour of organicfield effect transistors (OFETs) usually a commonset of equations known as gradual channel (orShockley) approximation is used. Within this frame-work, the drain current (ID) can be described asfunction of the drain/source voltage (VDS) and thegate/source voltage (VGS):

ID ¼

0 jV DSj < jV THj

l � e0er

tox

� WL

V DS V GS � V TH �V DS

2

� �jV GS � V THj > jV DSj

l � e0er

tox

� W2 � L � V GS � V THð Þ2 jV GS � V THj < jV DSj

8>>>>><>>>>>:

ð1Þ

where l is the mobility, tox and er the thickness andrelative dielectric constant of the gate oxide, VTH

the threshold voltage and W and L are the channelwidth and length.

This model describes the above threshold regionwell, as long as the source/drain-contact exhibitsohmic characteristics [8]. However, for the sub-threshold behaviour of an OFET the parasiticeffects like surface traps and gate-voltage-dependentmobility have to be considered.

A number of physical approaches which describethe carrier concentration in different organic semi-conductors have been reported [8–11]. However,the parameters for these models are hard to deter-mine and the models are unhandy for circuit simu-lations. On the other hand, there are papers,which show that the behaviour of organic semicon-ductors is similar to that of amorphous silicon [12–14]. For this reason we attempt to describe our

printed TFTs with an a-silicon model developedby Lee et al. [15]. It is based on the assumption thatthe drain current ID is composed of two contribu-tions, i.e.

ID ¼ I leakage þ Iab ð2ÞOne of them is due to the accumulation of carriers(Iab), while the other one is due to the intrinsic con-ductivity of the organic semiconductor (Ileakage). Aninversion of carriers is not included in this model asthis effect is not observed in a-silicon as well as inorganic semiconductors.

The accumulation current Iab can be calculatedfrom the carrier concentration ns. The carrier con-centration ns is composed of the free carrier concen-tration nsa and the carriers from deep traps nsb

ns ¼nsa � nsb

nsa þ nsb

ð3Þ

In order to calculate the free carrier concentration,the carrier equilibrium approach is used

nsa ¼e0er � V gte

e � tox

V gte

VAA

� �GAMMA

ð4Þ

where e is the elementary charge, VAA the charac-teristic voltage for field effect mobility and GAM-MA the power law mobility parameter. Vgte isgiven by

V gte ¼VMIN

21þ V gt

VMINþ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiDELTA2 þ V gt

VMIN� 1

� �2s2

435ð5Þ

where VMIN is the convergence parameter, DEL-TA the transition width parameter and

V gt ¼ V GS � V TH ð6ÞIn order to determine the trap carrier concentrationnsb a special approach for a-silicon [15] is used. Theconductivity of the channel gchi can be calculatedusing the carrier concentration ns,

gchi ¼ e � ns � W � l=L ð7Þ

Taking into account the resistance of the drain andsource areas (RD and RS), the effective conductivitygch is given by

gch ¼gchi

1þ gchiðRSþRDÞ ð8Þ

so that the contribution of the drain current Iab canbe written as

Iab ¼ gchV dseð1þ LAMDA � V dsÞ ð9Þ

Fig. 4. Mean value of the mobility of the D-TFTs as a functionof the gate voltage.

Table 1Fitted model parameters

Parameter Value Description

l 1.66 · 10�3 cm2/Vs MobilityAlphasat 0.48 Saturation modulation

parameterLambda 0.0042 V�1 Output conductance

parameterM 2.88 Knee shape parameterDefo 0.6 eV Dark fermi level positionVFB �65.60 V Flat band voltageV0 0.14 V Characteristic voltage for

deep statesVTH 2.97 V Threshold voltageSIGMA0 1.19 · 10�3 A Minimum leakage current

parameter

Fig. 5. Simulated and measured output characteristics of atypical D-TFT.


with

V dse ¼V DS

1þ V DS=V SATEð ÞM� �1=M

ð10Þ

and

V SATE ¼ ALPHASAT � V gte ð11Þwhere LAMBDA is the output conductance param-eter, M the knee shape parameter and ALPHASATthe saturation modulation parameter.

The leakage current Ileakage is due to the intrinsicconductivity of the organic semiconductor and canbe described as

I leakage ¼ SIGMA0 � V DS ð12Þwhere SIGMA0 is the minimum leakage currentparameter.

2.2. Parameter extraction

The simulations of our devices were carried outusing the Spice-version of AIM-Software. The soft-ware includes various TFT models for amorphousas well as for poly-silicon. For our purpose theAFET 15 model was used, which was originallydeveloped for amorphous silicon TFTs.

The parameters for the AFET 15 model weredetermined in two steps. Firstly, the mobility wascalculated from the measured output and transfercharacteristics. In order to do so, the mobility isderived from Eq. (1):

l ¼ oIDS

oV G

LWCiV DS

for jV GS � V THj > jV DSj ð13Þ

and

l ¼ offiffiffiffiffiffiffiIDS

p

oV G

� �22L

WCi

for jV GS � V THj < jV DSj

ð14ÞThe mean value of the mobility of the D-TFTsis shown in Fig. 4. The mobility strongly dependson the gate voltage, a behaviour which is oftenreported for organic [16,17] as well as for a-silicon[11] TFTs.

In a second step the parameter extractor of AIM-Spice was used to fit the whole parameter set for theAFET 15 model. While the AFET 15 model is validfor n-semiconductors, it had to be taken intoaccount that F8T2 is a p-type semiconductor, i.e.all currents and voltages had to change sign. Theobtained values for the fit parameters are summa-rized in Table 1.

With these values, a good agreement betweensimulation and experimental results could beachieved. Figs. 5 and 6 show the output and transfercharacteristics, respectively, of the F8T2-model-TFT and the means of the measured values of thedrive transistors.

Fig. 6. Simulated and measured transfer characteristics of atypical D-TFT.

Table 2AFET 15 model parameter fit for a F8T2 transistor

Parameter Value

RI 198 kX m2

CI 7.1 lF/m2

SigmaI 3.97 · 10�13 A

Fig. 8. SPICE model for an inverter with F8T2-TFTs.

Fig. 9. Measured inverter transfer characteristics and simulationswith different load resistances.


2.3. Circuit simulations

For the purpose of circuit simulations the TFT-model was extended with parasitic gate/source andgate/drain resistors and capacities in order todescribe the non ideal organic insulator (Fig. 7).Furthermore it was necessary to parameterize theleakage current.

In order to calculate the parasitic elements asfunctions of the channel width and length, the fol-lowing linear approaches were used

CGS ¼ CGD ¼ CI � W � F ð15Þ

RGS ¼ RGD ¼RI

W � ðF þ LÞ ð16Þ

SIGMA0 ¼ sigmaI

WL

ð17Þ

Here, W, L and F are the channel width and lengthand the finger width, respectively of the TFT. Theobtained fit parameters are summarized in Table 2.

Using the described transistor model, a singleinverter stage was simulated. The SPICE model ofan inverter is shown in Fig. 8. Fig. 9 shows the sim-ulated as well as the measured characteristics.Although the agreement of the simulation with theexperimental results is satisfactory, unfortunately

Fig. 7. Equivalent circuit of the F8T2-TFT.

there is a large variation of the characteristicsamong different inverters, which is due to the varia-tion of the transistor characteristics (see Fig. 3).However, it can be seen from Fig. 9 that the H-levelof the inverter is strongly depending on the outputload. Obviously, an 11 GX load resistance isapprox. equal to the input resistance (which is deter-mined by the gate/source resistance) of a followinginverter stage.

The results of a simulation of a chain of 7 inter-connected inverters are shown in Figs. 10 and 11 forsupply voltages of �40 and �80 V, respectively.Simulated transfer characteristics after the 1st,

Fig. 10. Transfer characteristics of 7 interconnected inverters atUSS = �40 V.

Fig. 11. Simulated transfer characteristics of 7 interconnectedinverters at USS = �80 V.

Fig. 12. CV-measurement of the gate capacitance of a typical D-TFT.


2nd, . . ., 7th inverter stages are plotted. For com-parison, the measured characteristics after 7 invert-ers is included in Fig. 10.

For a supply voltage of 40 V (Fig. 10) there ishardly any interval in which the inverter gain (theslope of the output characteristics, dVout/dVin) ishigher than 1. Therefore, the inverter chain doesnot work as an amplifier and no oscillation can besustained. This situation is different for a supplyvoltage of �80 V (Fig. 11). Here the output swingof inverter 7 is higher than the input swing (the gainis higher than 1) within the input voltage range of�12 to �52 V. In this interval the amplificationafter all inverter stages is higher than one (the max-imum gain is about 10) and, thus, if the output of

inverter 7 is fed back into the input of inverter 1,the circuit is oscillating with this amplitude (seeFig. 13). Provided that the amplification of theinverter chain is greater then one, the oscillator fre-quency is strongly dependent on the gate capaci-tance, which results from two contributions. Onecontribution is the overlap capacitance betweenthe gate and the drain/source electrode structuresand the second contribution is the gate-channelcapacitance. Fig. 12 shows the quasistatically mea-sured gate capacitance of a typical D-TFT. It canbe seen that the capacitance is strongly dependenton the gate/source-voltage. However, the low gatecapacitance at positive gate voltages reflects theoverlap capacitance, whereas the increase of thegate capacitance towards negative gate voltages isdue to the channel capacitance, which increasesupon accumulation of charge carriers.

The initial increase of the capacitance when mea-sured towards positive gate voltages (circles inFig. 12) is due to a measurement artifact which isbased on the initial load of the capacitor duringthe start phases. This initial load to a voltage of�60 V has not been completely finished, when theCV-measurement is started. Thus, the first measure-ment points are corrupted by the initial load cur-rent. Another artifact is the significant decreasefor higher (positive) voltages which can not beexplained yet and is also not seen in simulation.Nevertheless, the simulated CV-curve, which is alsoplotted in Fig. 12, is in reasonable agreement withthe experimental data, at least for negative gatevoltages. This result confirms our approach to usethe a-silicon trap distribution model [15].

Using the F8T2 transistor model we were able tosimulate the printed ring oscillator circuit and pre-dict the supply voltage that is needed for the oscilla-

Fig. 13. Spice simulation of a 7 stage ring oscillator for differentsupply voltages for RL =1.

Table 3Comparison of simulated and measured frequency and amplitudeof a seven-stage ring oscillator

Supplyvoltage

Simulated Measured

RL =1 RL = 1 GX

f inHz

VO, PP

in Vf inHz

VO, PP

in Vf inHz

VO, PP

in V

�40 V – – – – – –�60 V 1.1 20 1.2 11 1.1 11�80 V 1.8 35 2.1 25 2.5 17


tion. In Fig. 13 the simulated output signal isshown. The amplitude of the oscillation is in a goodagreement with the prediction from the static simu-lations (see Figs. 10 and 11). However the amplitudeof the measured output signal is lower (Fig. 14). Thereason for this deviation could be an input resis-tance of our measurement equipment, which weestimate to be approx. 1 GX. This load on the out-put of the oscillator can be responsible for the loweroscillation amplitude and a slightly higherfrequency.

Table 3 shows the simulated and measured fre-quencies and amplitudes of our ring oscillator fordifferent load resistance. A reasonable agreementbetween simulated and measured values can beobserved.

Fig. 14. Measured output signal of a 7 stage ring oscillator fordifferent supply voltages.

3. Conclusions

We have developed an easy to use model in orderto describe the behaviour of printed organic circuitswhich is based on an existing model for a-silicon[15]. With the model it is possible to simulate deviceparameters of printed transistors and inverters withhigh accuracy. Furthermore, more complex circuitscan be easily simulated both in terms of static anddynamic behaviour. Qualitative agreement withexperimental data is obtained in this case, howeversome quantitative deviations occur which are sub-ject to future study. We have also used the modelfor devices based on poly(3-hexylthiophene)(P3HT) and poly(triarylamin) (PTAA) with similarresults.

Future development of circuit simulation shouldbe aimed at the requirements of the fabrication ofmore complex circuits. Furthermore, it is desirableto model the trap-behaviour with a specific poly-mer-related approach, taking advantage of theparameters having a physical background and thusallowing for an understanding of the interrelationof technological changes and parameter variations.

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Device and Circuit Simulation of Printed Polymer Electronics

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