Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low,...

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Company Public NXP, the NXP logo, and NXP secure connections for a smarter world are trademarks of NXP B.V. All other product or service names are the property of their respective owners. © 2018 NXP B.V. Product Marketing Manager Industrial Applications Digital Networking Jeff Steinheider Deterministic Processing and Ethernet for Industry 4.0 September 2018 | AMF-NET-T3270

Transcript of Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low,...

Page 1: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

Company Public – NXP, the NXP logo, and NXP secure connections for a smarter world are trademarks of NXP

B.V. All other product or service names are the property of their respective owners. © 2018 NXP B.V.

Product Marketing Manager – Industrial Applications

Digital Networking

Jeff Steinheider

Deterministic Processing and Ethernet for Industry 4.0

September 2018 | AMF-NET-T3270

Page 2: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 1COMPANY PUBLIC 1

• Industrial Application Requirements

• Deterministic Computing

• Protecting Industrial Devices

• Time Synchronization

• Deterministic Networking

Agenda

Page 3: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 2

Industrial Applications for Layerscape Solutions

Factory and Infrastructure

Production and & Facility Monitoring

Manufacturing Control

Process Control

Water Treatment, Oil & Gas

Energy Generation, Transmission & Distribution

Military and Aerospace

Drones

Avionics Control

Military Vehicles

Transport

Rail Systems

Mobility and Logistics

Industrial Vehicles

Buildings

Control

Automation

Industrial Networking

IoT Gateways

Industrial Gateways

Industrial Switches

Routers

Access Points

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COMPANY PUBLIC 3

Manufacturing Automation/Smart Grid Requirements

Control

Processor

(LS1)

Communications IC

Motors,

Drives(LPC15xxx, Kinetis)

Control loops run every 25-150 usecs

Requires low, deterministic latency

All elements must be synchronized

Control loop period determines how fast and how

smoothly a mechanical system can run

PCIe or 16 bit parallel bus

Depends on data sizes and system architecture

Communications IC

Will be replaced by TSN

Processor Requires Real-Time Performance

Traditionally supported via RTOS

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COMPANY PUBLIC 4

LS1028A

• Cortex-A72

• 2 cores

• 1.6GHz

• 4-9W

• Integrated TSN switch

LS1043A

• Cortex-A53

• 2-4 cores

• 1.6GHz

• 1/10G Ethernet, USB, PCI

• 5-10W

LS1046A

• Cortex-A72

• 2-4 cores

• 1.8GHz

• 1/10 G Ethernet, USB, PCI

• 10-12W

LS1088A

• Cortex-A53

• 4-8 cores

• 1.6GHz

• 1/10 G Ethernet, USB, PCI

• 8-16W

Video/image

processing,

large-scale

analytics, TSN

ethernet,

Gateway

applications

LS1012A

• Cortex-A53

• 1 core

• 1GHz

• 1-2W

• Ethernet, USB, PCI

LS1021A

• Cortex-A7

• 2 cores

• 1GHz

• 2W

• Ethernet, USB, PCI

Large-scale

video/image

processing,

data

aggregation,

backhaul

Data acquisition,

analytics,

monitoring,

remote control

LS2088A

• Cortex-A72

• 4-8 cores

• 2.0GHz

• 8 x 10GE

• 20-35W

LX2160A

• Cortex-A72

• 8-16 cores

• 2.2GHz

• 10/25/40/100 GE

• 31W

Layerscape - A Broad and Scalable Edge Computing

Portfolio

• All LS-series processors have rich set of IO – USB, PCIE, SATA, GPIO, I2C, SPI, UART

• All support Trust Architecture for platform security

• Support both embedded and PC Linux distros

• Support industrial temperature ranges

• Support long lifecycles

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COMPANY PUBLIC 5

A

B

C

D

E

F

GBuilt-in TSN and

IEEE1588 Support

Built-in industrial-grade

security

Support for various

industrial networking

protocols

Built-in graphic display

support for HMI

Applications

Open Software

Repository and

Community

Hard real-time

applications support

Manageable via industrial control

and networking protocols

Open

Industrial

OpenIL.org

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COMPANY PUBLIC 6

802.11ac/n

ARM CPUsup to 100K Coremark

Available

PCIe

Packet Engine

2-20Gbps

Ethernet Controllers

2x 1GE -> 2x 10GE

Security

EngineBLE/Zigbee/

Thread

NFC

4G

OpenIL for Industrial Automation

DeterminismXenomai Linux, Bare Metal Framework

IEEE 1588, TSN

SecuritySE Linux

OP-TEE

Scalable Hardware

Open Industrial Linux SDK

LS1046

LS1043

LS1012

LS1021

Networking, Security drivers

Customer Applications

TS

N, IE

EE

1588

Trust Architecture

Xenomai SE LinuxBare Metal

Framework

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COMPANY PUBLIC 7

OpenIL Running on Scalable Portfolio of Devices

LS1021A

• Cortex-A7

• 2 cores

• 1.2GHz

• 2W

• Ethernet, USB, PCI

LS1043A

• Cortex-A53

• 2-4 cores

• 1.6GHz

• 1/10G Ethernet, USB, PCI

• 5-10W

LS1046A

• Cortex-A72

• 2-4 cores

• 1.8GHz

• 1/10 G Ethernet, USB, PCI

• 10-12W

LS1028A

• Cortex-A72

• 2 cores

• 1.3GHz

• 4-9W

• Integrated TSN switch

• 2D/3D GPU

i.MX 6Dual/6Quad

• Cortex-A9

• 2-4 cores

• 800 MHz (Industrial)

• 2D/3D GPULS1012A

• Cortex-A53

• 1 core

• 1GHz

• 1-2W

• Ethernet, USB, PCI

Currently Supported Devices

Single to Quad Core

32 and 64 bit Arm

New Device Support in 2H 2018

Adding 3D GPU

Adding Integrated TSN

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COMPANY PUBLIC 8

One Package - Four SoC Options

4x A53 1.6 GHz

4.2 W Typical

26,650 Coremark

Per core SpecINT

Per core SpecFP

2x A53 1.0 GHz

2.5 W Typical

8,360 Coremark

Per core SpecINT

Per core SpecFP

4x A72 1.8 GHz

8.5 W Typical

45,330 Coremark

Per core SpecINT

Per core SpecFP

2x A72 1.2 GHz

5.6 W Typical

15,000 Coremark

Per core SpecINT

Per core SpecFP

23mm x 23mm

780 pin

FC-PBGA Package

LS1043

LS1023

LS1046

LS1026

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COMPANY PUBLIC 9

Deterministic Computing

Page 11: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 10

Deterministic Computing for Industrial Workloads

3 Levels of Real-Time Performance:

• Xenomai Mercury (PREEMPT-RT Patches)

− LS10XX (Q1 2017)

• Xenomai Cobalt (Real-Time Co-Kernel)

− LS10XX (Q2 2017)

• Bare-Metal Framework

− LS10XX (Available Now!)

• Run management, communication software in

Linux on 1 core

• Real-time applications running with RTOS

(Xenomai) or Bare-Metal on other cores

SoC

Linux RTOS RTOSBare-

Metal

Core 1 Core 2 Core 3 Core 4

I/O - Ethernet, PCIe

Acceleration Acceleration

Heterogeneous Software Model

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COMPANY PUBLIC 11

Xenomai Latency Distribution on LS1043A

1 10

141

353

84

7 3 10

50

100

150

200

250

300

350

400

0.4 0.44 0.48 0.52 0.56 0.6 0.64 0.68

Max Latency Samples Distribution

Max Latency (us)

• Xenomai Cobalt 64-bit

mode on LS1043A @ 1.6

GHz

• Measured using Xenomai

latency tool

• Jitter < 450 ns

• Max latency of 680 ns

latency min (us) latency avg (us) latency max (us) Duration

0.24 0.279 0.68 00:10:00

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COMPANY PUBLIC 12

Protecting Industrial DevicesRoot of Trust

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COMPANY PUBLIC 13

PreBoot Loader

Internal BootROM

SEC Engine

Crypto, RNG

Security

sub-system

AIOP

Trust Architecture Provides a Trusted PlatformHardware based security features to ease the

development of trustworthy systemsAll QorIQ SoCs support Trust Architecture

Manufacturing

Protection

8

Secure

Boot

1Secure

Storage2

Key

Protection

3

Key

Revocation

4

Secure

Debug

5

Tamper

Detection

6

Strong

Partitioning

7Coherent Interconnect

Security Fuses

Power Mgmt

SD/MMC

USB SATA

DUARTSPI

CCSR GPIO

IFC

QMan

BMan

Watchpoint

PerfMonitor

CoreNetTrace

Aurora

Real Time Debug

Clocks/Reset

DDRController

General

Purpose

Processor

General

Purpose

Processor

I2C

Eth,

PCI

FMAN

WRIOP

IOMMU

HV MMUHV MMU

IOMMU

Mgmt Control

Secure Keys

UID, Runtime

Integrity Check

Data-path

sub-system

Secure Debug

Controller

Security Monitor

Battery Back-up

Tamper

Detect(s)

Page 15: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 14

Runtime Access Control with SELinux

• Improved access control

• Policies control file access, network resources, and IPC

− Finer grain access control

• Use cases:

− Prevent remote login for certain types of users

− Restrict access to files from the web

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COMPANY PUBLIC 15

Time Synchronizationlinuxptp

Page 17: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 16

Layerscape Arm® MPUs With IEEE 1588 Hardware

• Scalable family of ARM SoCs

• IEEE 1588 Hardware Time Stamping

−Hardware 2-Step supported in all devices

−1-Step supported in LS1028 Family

• IEEE 1588 Timing Logic

−Use internal or external clock source

−Generate periodic phase aligned pulse

signals for external devicesLS1021A

• Cortex-A7

• 2 cores

• 1.2GHz

• 2W

• Ethernet, USB, PCI

LS1028A

• Cortex-A72

• 2 cores

• 1.3GHz

• 4-9W

• Integrated TSN switch

LS1043A

• Cortex-A53

• 2-4 cores

• 1.6GHz

• 1/10G Ethernet, USB, PCI

• 5-10W

LS1046A

• Cortex-A72

• 2-4 cores

• 1.8GHz

• 1/10 G Ethernet, USB, PCI

• 10-12W

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COMPANY PUBLIC 17

1588 Clock Circuits Available in Layerscape SoCs

Use either internal or external

clock to generate 1588 nominal

frequency

Timestamping

value used for Tx

and Rx packets

Generate phase

aligned periodic

pulses

Page 19: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 18

IEEE 1588 for Timing Synchronization

linuxptp support:

LS1021A

LS1043A

LS1046A

Master/Slave

Boundary Clock Mode

802.1AS End Station

Synchronization within +/- 23 nsec for

back to back boards

Example configurations and test results

Page 20: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 19

1588 Performance

Timing settles within 5 seconds Accuracy within ±23 nsec

Offset from Master, Startup Offset from Master, Stable State

Page 21: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 20

Deterministic Networking

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COMPANY PUBLIC 21

Embedded Time-Sensitive Networking (TSN)

• Converge OT and IT traffic in a single network

• Determinist Ethernet at gigabit speeds

• Reduce network delays, improve robustness

• Embedded in Multi-processor SoCs

TSNFieldbus

Protocols

Proprietary

Industrial

Ethernet

Gigabit Ethernet

SEC

GPU

ARM®

V8

L2 CacheD

D

R

ARM®

V8

Eth

Cont.

4 Port

TSN

Ethernet

Switch

TSN

Eth

Cont.Standard

IP Traffic

Page 23: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 22

802.1.Qbv – Time Aware Shaping

• Different priority traffic

allocated for each queue

• Queue gate schedule

synchronized to global time

• 8 Queues availableTalker

Schedule when queues open

to send traffic, synchronized

with 802.1AS

Queue Gate

Queue Gate

Queue Gate

Queue Gate

Queue Gate

Queue Gate

Queue Gate

Queue Gate

Schedule

c

O

c

c

O

c

c

c

c

O

c

c

O

c

c

c

O

c

c

c

c

c

c

c

c

c

O

O

c

O

c

c

c

c

c

c

c

c

O

O

O – Gate open

c – Gate closed

Time

Page 24: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 23

802.1CB – Frame Replication and Elimination for Reliability

A’

A’’

B’

B’’

ListenerTalker

Talker replicates Ethernet

frames and sends over

multiple paths to Listener

• Listener provides first Ethernet

frame that arrives to application

• Listener removes duplicates

• TSN hardware performs

replication/elimination

• Zero time failover if 1 path fails

• No need for upper level retry

mechanisms

• Simpler code base with

reliability

Page 25: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 24

802.1Qbu – Frame Pre-emption

TalkerQueue Gate

Queue GateTalker

Queue Gate

Queue Gate

Pre-emptable Traffic

Express Traffic

Pre-emptable Traffic

Express Traffic

Start to transmit frame of

pre-emptable traffic

Interrupt pre-emptable

frame with express frame.

Will transmit remaining pre-

emptable frame once

express frame complete

• Ensure zero delay for express traffic

• Efficient use of bandwidth for pre-emptable traffic

• Used with TAS, or stand-alone

Page 26: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 25

LS1021ATSN – TSN Solution Reference Design

• Synchronization with IEEE® 1588

• 4 Switched Gigabit Ethernet TSN interfaces

− Time Aware Shaping

− Per-Stream Filtering and Policing

• Arduino Shield for IoTWireless Integration

• Expandable IO – mini PCIe, SATA, USB 3.0, SD Card, GPIO

NXP Industrial

Linux

TSN

Configuration

Software

Wireless Drivers

Customer

Control

Application

Xenomai

Real Time

Kernel

Netconf/YangIEEE® 1588/

802.1AS

gPTP

Transport

Protocols

TSN Solution

LS1021ATSN Reference DesignIndustrial Linux SDK

Available Now – $829

Page 27: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 26

Single Board TSN Demonstration

• 3 host Linux machines connected

through a switch

• 2 TCP flows competing for bandwidth

• Flows bottlenecked because they are

sharing the same link towards Host 2

• Combined throughput cannot exceed

1000Mbps

• Utilize TSN features to isolate flows

− Ingress Policing: rate-limit traffic coming

from Host 3

− Time Gating: schedule the 2 flows on

different time slots

Page 28: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 27

Start TSN on LS1021A-TSN – Enhance with LS1028A

LS1021A-TSN

TSN Features

• Time Aware Shaper (802.1Qbv)

• Per-Stream Filtering & Policing (802.1Qci)

• Credit Based Shaper (802.1Qav)

• Time Synchronization (802.1AS)

LS1028A

New TSN Features

• Frame Pre-emption (802.1Qbu)

• Frame Replication and Elimination (802.1CB)

• Cut-through Switching

• Cyclic Queuing and Forwarding (802.1Qch)

• 802.1AS-Rev

Supported by one SDK – Open Industrial Linux

Page 29: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 28

LS1028A Reference Design

Front Panel Back Panel

2x CAN FD Interfaces 2x UART

Up to 4K

Display via

DisplayPort

USB 3.0

Type C and Type

A

Full Size SD

Card Slot

4 Switched

1G/100M/10M

TSN Ethernet

Ports

1G/100M/10M

TSN Ethernet

Controller

Compelling Combination of IO, Computing and TSN

• Internal M.2 PCIe, SATA slots

• 2x mikroBUS™ sockets for Click Boards

Page 30: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 29

• Industrial Control, PLCs, Gateways

• Automotive

• Professional Audio/Video

• IoT Gateways

• Human Machine Interface

Coherent Interconnect (CCI-400)

16/32-bit DDR3L/4

Memory Controller (ECC)48 KB L1-I

32 KB L1-D

1MB L2 - Cache

Core Complex

ARM

Cortex –A72

ARM Trust Zone

Secure Boot

Security Engine

Standard interfaces

6x SAI, 2x CAN-FD

FlexSPI

2x SD/SDIO/eMMC

2x UART, 6x LPUART

8x I2C, GPIO

3x SPI

8x Flex Timer

Security

Power Management

Multimedia interfaces

4K LCD Controller

eDP/DP Phy

PCIe

3.0

SATA

3

USB

3.0

w/PHY

PCIe

3.0

USB

3.0

w/PHY

256KB SRAM2.5 GbE

2.5 GbE

2.5 GbE

1 GbE

2.5 GbE

2.5 TSN GbE

TS

N S

witch

ARM

Cortex –A72

Accelerators and Memory

ControlHigh Speed

interfaces

Networking

Elements

3D GPU

48 KB L1-I

32 KB L1-D

Target Applications:

LS1028A: Dual ARM Cortex A72 Processor

Package

• 17x17mm, 0.75mm pitch FC-PBGA

Core complex

• 2x 64-bit Cortex-A72 with Neon SIMD engine

• Speed up to 1300 MHz

• Parity and ECC protected 48 KB L1 instruction and 32 KB L1 data cache

• 1 MB L2 cache with ECC protection

Basic peripheral and Interconnect

• 2x USB 3.0 OTG controllers with integrated PHY

• 2x eSDHC controllers supporting SD/SDIO 4.0

• 2x CAN-FD controllers

• 8x UART serial ports

Networking elements

• Four Port TSN Ethernet Switch up to 2.5 Gbps on each port

• Up to four SGMII supporting 1 Gbps

• Up to one USXGMII supporting 2.5 Gbps

• Up to one QSGMII

• Up to one RGMII

• 2x PCI Express Gen 3 controllers

• 1x SATA Gen 3.0 controller

Accelerators and Memory Control

• 1x 16/32-bit DDR3L/4 Controller with ECC support up to 1.6 GT/s

• Time Sensitive Networking (TSN) Ethernet Switch

• Security Engine (SEC)

• QorIQ Trust architecture: Secure boot, ARM Trust zone and security monitor

Qualification

• Commercial and extended temperature (support for 125C Tj)

Power

• 5W TDP

Page 31: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 30

OPC UA over TSN for Industry 4.0 Communications

• OpenIL integrates with

Open62541

− Open source C implementation of OPC

UA

− Mozilla Public License v2.0

− server side capabilities

• LS1021A Running OPC UA

Server

− Providing switch statistics

− Access via FreeOpcUa Client GUI

Page 32: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

COMPANY PUBLIC 31

Layerscape for Industry 4.0

Open

Industrial

✓ Open Industrial Linux growing to support more SoCs

• Coverage across Layerscape and i.MX

✓ Deterministic Processing

• Xenomai Linux

• Bare Metal Framework

✓ Secure industrial systems with root of trust and

SELinux

✓ Synchronized and Deterministic Networking

• 1588

• TSN

Page 34: Deterministic Processing and Ethernet for Industry 4 · 2020. 9. 18. · Requires low, deterministic latency All elements must be synchronized Control loop period determines how fast

NXP, the NXP logo, and NXP secure connections for a smarter world are trademarks of NXP B.V. All other product or service names are the property of their respective owners. © 2018 NXP B.V.

www.nxp.com