Designing with the Nios II Processor and SOPC Builder...
Transcript of Designing with the Nios II Processor and SOPC Builder...
Designing with the Nios II Processor
and SOPC Builder
Exercise Manual
Software Requirements: Quartus II 8.1
ModelSim 6.3g (for Quartus II 8.1)
Nios II 8.1
Altera Megacores IP 8.1
Hardware Requirements:
This lab guide is set up to allow you to use the following boards:
Nios Development Kits: Stratix 1S10 and 1S10ES
Stratix 1S40
Stratix II 2S60 and Stratix 2S60ES
Cyclone 1C20
Cyclone II 2C35 and 2C35ES
Cyclone III Starter FPGA and Nios II Embedded
Evaluation Kits (NEEK)
Lead-Free (rohs) Kits: Stratix II 2S60 and Stratix 2S60ES
Cyclone II 2C35 and 2C35ES
Cyclone III FPGA Starter Kit
Cyclone III Nios II Evaluation (NEEK) Kit
DSP Development Kits: Stratix II 2S60 and 2S60ES
Exercise Manual Designing with the Nios II Processor & SOPC Builder
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Exercise Manual Designing with the Nios II Processor & SOPC Builder
Copyright © 2009 Altera Corporation
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Lab 1
Creating a Nios II
Processor System
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Exercise Manual Designing with the Nios II Processor & SOPC Builder
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Objectives:
Over the course of the lab today, you will create an embedded hardware system and run some
software code on it. As the lab progresses, you will continue to modify your hardware system
to incorporate new features as you learn about them in class.
This lab guide is set up to allow you to use any one of the following development kits, so,
some written steps will pertain to one type of board; other steps to another type of board.
You can tell when type of kit your are using by looking at the labelling on the FPGA package
on your kit. Failing that, the instructor should be able to advise you. The kits fall into two
main categories as shown below:
Nios II Processor Development Kits:
Stratix Stratix II
Stratix 1S10 Stratix II 2S60
Stratix 1S10ES Stratix II 2S60ES
Stratix 1S40 Stratix II 2S60 rohs (new lead-free kit)
Cyclone Cyclone II Cyclone III
Cyclone 1C20 Cyclone II 2C35 FPGA Starter Kit
Cyclone II 2C35ES Nios II Evaluation (NEEK)
-and-
DSP Development Kits:
Stratix II
Stratix II 2S60
2S60ES
Note: It is unlikely that you will using a DSP kit unless you are also taking the DSP class.
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Step 1: Set Up Embedded Hardware Design Project
Hardware set up requirements:
• USB-Blaster, ByteBlaster, ByteBlaster II, or Byte Blaster MV programming cable
connected between computer and JTAG connection header on development board
• Power supply connected to the board
Typical Nios II Processor Development Kit
1. Insert the CD Rom from the back of your handout into the computer provided.
2. Open the CD Rom for viewing, and double-click on the .exe file you see. It will be called
“NII_SOPCBuilder_2Day_<ver>.exe.”
This is a self-extracting zip file that will unzip the files you need for today into the folder
called, C:\altera_trn\Nios II_HW\NiosII_2Day.
3. Navigate into that directory and then into Day1.
In this directory, you will find several sub-directories for each of the different types of
development boards supported for this class. Inside each respective project folder is a
sub-directory called niosII_lab that contains the partially completed Quartus II project
that you will use as your starting point today.
Note: Do not connect
LCD display to board even
though it is shown in the
figure – you will not be
using it today.
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4. Navigate into the appropriate project folder for your particular development kit: (Refer to
the illustrated directory structure below for help or consult instructor.)
You will have to check the part on your board to confirm this. Also, please note whether
your part ends with ES or not or whether it is a Rohs kit.
Lab Directory Structure and Working Area
for Stratix II 2S60ES kit Nios II Processor Development Kit
5. Change directory into nios_II_lab located inside your particular kit’s project folder.
Start the Quartus II Software by double-clicking on the project file located therein:
(ie. niosII_lab.qpf)
DSP Kits Folder
Nios Kits Folders
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6. Assign device family and pinout settings to your Quartus II project by sourcing the
TCL script provided in your working directory (see over).
From the Tools menu select Tcl Scripts,
and then from the Project folder choose
the setup script for your development
board (eg. Setup_Cyclone_2C35.tcl,
etc.), and click Run.
This will automatically assign the relevant
device settings and pin-outs to the
Quartus II project for the particular FPGA
development board you are using.
If you are unsure about which kit you are
using, please check FPGA on
development board or consult your
instructor.
Note: As an alternative, you may also source the Tcl script from the Tcl command prompt
in Quartus II by typing “source” followed by the name of the script.
For example: “source Setup_StratixII_2S60_rohs.tcl”.
7. Save your updated project settings: File > Save Project.
8. Next, you will start building your embedded system:
It will be composed of the following components:
Nios II CPU
Tightly-coupled on-chip instruction memory
External SRAM or SSRAM memory controller
External Flash memory controller
One or more tri-state bridge components to interface with the memory
components on the tri-state bus or busses on your board
JTAG UART peripheral
(cont. over)
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.
.
.
PIO peripherals, configured to interface to LEDs, buttons, and a seven segment
display if your board has one
System clock timer
High resolution timer
System ID peripheral
PLL
Note: Some of these component’s settings will depend on what kit you have. Please
follow the instructions for your particular board, and choose appropriately. Consult
with the instructor if you are not sure which board you have.
In essence, you will be building a system that looks like this:
Outline of Hardware System
9. Start SOPC Builder from Tools => SOPC Builder… and enter the system name, niosII,
when the next window pops up. You can choose VHDL or Verilog (whichever you
prefer) as the implementation language. The blank SOPC builder window will open.
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10. The Device Family should match the FPGA you are using (eg. Stratix II EP2S60.
Ensure the External Clock frequency is set to 50 MHz for all kits (except the Stratix II
DSP kits, whose input frequency is to be set to 100 MHz).
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Step 2: Add Nios II Processor to System
1. From the left hand window pane select Nios II Processor and click Add. Select Nios
II/s for the processor core. Select DSP Block as the Hardware Multiply option for all
Stratix boards, Embedded Multipliers for all Cyclone II and Cyclone III boards, or
Logic Elements for Cyclone boards.
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2. Click on the Caches and Memory Interfaces tab. Set the Instruction Cache size to
4Kbytes and include one tightly coupled memory instruction master port.
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3. Now, click on the JTAG Debug Module tab. Select the JTAG Target Connection
Download Level 3 option. This will provide us with all the debug options listed on that
tab.
4. Click Finish. This will add it to the SOPC Builder system.
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5. Rename the processor, if necessary, by right clicking on it and selecting Rename.
Type in cpu and hit enter.
Note: It is essential for you to enter the
names of all peripherals and memories
EXACTLY as shown in the lab guide since
these components will be referenced later
on in the C–code. Also, be sure that you
type each name using the correct CASE.
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Step 3: Add Avalon-MM Tristate Bridge (or Bridges) to System
1. You will now add the appropriate number of Avalon-MM-to-tri-state bus-bridging
peripheral/s required to let you access the various memory chips on your board. (After
this you will add the appropriate memory interface controllers, themselves.)
You will find the Avalon-MM Tri-State Bridge peripheral in the Bridges and
Adapters section of the SOPC Builder pick-list under Memory-Mapped components.
For all the boards, you will add at least one tri-state bridge. Others will require two tri-
state bridges. Follow the upcoming steps to see what is required of your board.
2. For all boards, add an Avalon-MM Tri-State Bridge peripheral to the design. Select
the Registered option, and click Finish.
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3. Then, re-name the peripheral to, ext_ram_bus.
4. For certain kits, you will have to add an additional tri-state bridge:
From the Nios II Development Kit Pool: Cyclone II 2C35
Cyclone II 2C35ES
Stratix II 2S60 rohs
(Note: do not add second bridge
for the non-rohs Stratix II kits)
From the DSP Development Kits: Stratix II 2S60 and 2S60ES
If you have one of the kits listed above, highlight the Avalon-MM Tri-State Bridge
peripheral, click Add, select the Registered option, and click Finish. Rename this
second tri-state bridge peripheral ext_flash_bus.
Note:
The reason that you will add a second tri-sate bridge for these particular boards is
because they contain two tri-state memory buses – one for the flash and another for
everything else on the PCB. All other kits share one tri-state bus for everything, so
they only require one bridge. Please consult your instructor if you are unclear.
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Step 4: Add Flash Memory to System
1. From the left hand window pane go to the Memory and Memory Controllers > Flash
folder, highlight the Flash Memory (CFI) component, and click Add. Then, choose the
appropriate type of flash memory for your particular board from the Presets category
(see below for choices):
For all Stratix II and Cyclone II Nios Development Kits add:
AMD29LV128M-123R (BYTE-Mode) preset
Address width of 24 and data width of 8
For Cyclone III Kits add:
Intel 128P30 preset
Address width of 23 and data width of 16
For all Stratix I and Cyclone I Development Kits add:
AMD29LV065D-120R preset
address width of 23 and a data width of 8
For Stratix II DSP Development Kits add:
AMD29LV128M-123R (BYTE-Mode) preset
Address width of 24 and data width of 8
Eg.
Accept the defaults, click Finish.
Then, rename the memory to
ext_flash.
Exercise Manual Designing with the Nios II Processor & SOPC Builder
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Step 5: Add Static RAM to System
Note: You will perform either Step 1 or Step 2, depending on what board you have.
1. For all boards except the Cyclone II, Cylclone III, and Stratix II rohs Nios II
boards, you will now add an SRAM memory controller. (If you have one of those
boards, please skip to the next step and add an SSRAM component.)
Otherwise, from the Memories and Memory Controller > SRAM folder in the SOPC
Builder pick list, select IDT71V416 SRAM, and click Add. (You can increase the width
of the pick-list window to help you find the components if you want to.) Select a memory
size of 1024 kB.
Click Finish, and rename the memory ext_ram.
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2. If you have a Cyclone II, Cyclone III, or Stratix II rohs Nios II boards, then add an
SSRAM memory controller instead, and accept the defaults.
Select Cypress CY71380C SSRAM from the Memories and Memory Controller >
SRAM folder, and click Add. Choose the settings shown below. (If you are using a
Cyclone III device, choose a 1 MB memory.)
Click Finish and then rename the memory ext_ssram.
Choose 1 MB for
Cyclone III Boards
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3. Now, highlight the RAM component you just created, and move it up directly underneath
the ext_ram_bus peripheral using the Move Up button located at the bottom of the work
space. (Note: Doing this is not absolutely necessary but will help keep the System
Contents page nice and tidy as you start adding more components and adjusting master-
slave connections.)
4. Ensure that the appropriate master slave connections are set in the connections panel in
SOPC Builder. That is, the “ext_ram_bus” peripheral tri-state master should master the
“ext_ram” (or “ext_ssram”) memory, and the “ext_flash_bus,” if present, should master
“ext_flash” memory. To do this, go to the View menu in SOPC Builder, and unless it is
already done so for you, turn on Show Connections Column. (A check mark will
appear beside your selection.)
Experiment by moving your mouse over the connection panel the view to highlight either
the interconnects or the master-slave connections. You can click on the circles in the
interconnect to make or sever the connections. Black dots mean that the connection will
be made; while white dots mean that no connection will be made (see below and see
over).
move mouse to change
connection view as shown
Edit Mode View Mode
Exercise Manual Designing with the Nios II Processor & SOPC Builder
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Connections for the Cyclone II and Stratix II rohs Nios II kits:
Connections for all other Nios II kits: (including the Cyclone III kits)
Connections for the Stratix II DSP kits:
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Step 6: Set Connection Properties For Shared Avalon-Tristate Bridge
1. For the following boards only, set the ext_ram_bus tri-state bridge peripheral to
share address ports between the ext_ram and the ext_flash peripherals as shown below:
Cyclone 1C20
Cyclone III FPGA Starter kit
Nios II Evaluation (NEEK)
Stratix 1S10 and 1S10ES
Stratix 1S40
Stratix 2S60 and 2S60ES
Note: Double-click on the peripheral
To open it for editing.
This is required for these kits because they have only one tri-state peripheral, so you have
to share some pins through it.
Then click Finish.
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Step 7: Add JTAG UART to System
1. From the left hand window pane find the JTAG UART from the Interface Protocols >
Serial folder and click Add. Accept the defaults. (The screen should appear as shown.)
The peripheral should be named jtag_uart.
Exercise Manual Designing with the Nios II Processor & SOPC Builder
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Step 8: Add a PIO to Control the Seven Segment Display
1. From the pick list, look in the Peripherals > Microcontroller Peripherals folder, select
PIO (Parallel I/O), and click Add. Enter a width of 16 bits, with output ports only.
Click Finish.
Rename this peripheral seven_seg_pio.
Note:
Do not worry about the error messages you see in SOPC Builder yet. You will deal
with them later.
Note: Skip this step for
any Cyclone III
boards because
they do not have
a seven segment
display.
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Step 9: Add Another PIO to Control the LEDs
1. Add a second PIO (Parallel I/O) peripheral with a width of 8 bits (or 4 bits for the
Cyclone III boards), with output ports only set. Click Finish. Rename this peripheral
led_pio.
Choose 4 for
Cyclone III Boards
Exercise Manual Designing with the Nios II Processor & SOPC Builder
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Step 10: Add Another PIO to Control the “SW” Buttons
1. Select yet one more PIO (Parallel I/O) and Add it to your system. Choose width 4 bits
this time, with Input ports only selected, and click Finish. Rename the peripheral
button_pio.
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Step 11: Add Timers to System
1. Select the Interval Timer from the Microcontroller Peripherals folder and click Add.
Select the Full-Featured Preset, and click Finish. After the timer has been added to your
system, rename it to sys_clk_timer.
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2. From the left hand window pane add another Interval Timer to the system. Change the
Preset to Full-featured and the period to usec. Then click Finish. (You are going to use
this later when you time the speed of some of our software functions.)
Rename the timer to high_res_timer.
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Step 12: Add System ID Peripheral to System
1. Locate the System ID Peripheral from the Peripherals > Debug and Performance
folder in the pick list, and Add it to your system. (Note: it is recommended that every
SOPC Builder design that you create has a system ID peripheral!)
Rename it to sysid.
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Step 13: Add PLL Peripheral to System
1. Now, Add the Altera PLL component to the project from the PLL folder. Then launch
the ALTPLL MegaWizard and configure the PLL using the settings shown below.
(Note: You navigate through the Wizard using the Next button.)
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You will accept most of the default PLL settings. The settings that you have to
observe and possibly change are listed in the following table:
Note: For the PLLs that require two tap outputs, C0 and C1, you must manually
enable a second tap inside the PLL MegaWizard. To do this, simply click on the
“Use this clock” check box on the appropriate Output Clocks page of the
Megawizard.
* These kits require two PLL output taps *Please consult with instructor if
you are confused as to which board
you are using and the settings you
need to choose
*
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After you configure the PLL to match the setting shown above, select Finish. The
final page of the PLL Wizard should resemble the following: (Note: there will be
some minor differences depending on what language you have chosen or development
kit you are using for your project.)
Select Finish again and then Finish one more time to add the component to the SOPC
Builder system; then re-name it, pll.
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Double click on “pll_c0”in the Name column in the Clock Settings window in the
top right corner of the SOPC Builder tool, and type over the text to re-name it
sys_clk. (If you generated a second PLL output tap, then also re-name pll_c1 to
ssram_clk.) The system Clock window should appear as follows:
Cyclone II and Stratix II rohs Nios II Development Kits:
Cyclone III Development Kits
All other Nios II Kits (including non-rohs Stratix II):
Stratix II DSP Development Kits:
2. Now, click in the Clock column for all peripherals (except the pll) and change their
driving clocks to sys_clk.
ie.
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Step 14: Establish IRQ Priorities
1. Assign the IRQ numbers: Go to the System menu and select Auto-Assign IRQs to
establish some basic IRQ assignments. Then, take a look at the IRQ values that
result. Edit them to ensure that the sys_clk_timer gets priority 0 (highest priority)
and JTAG_UART gets priority 2 (lowest priority).
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Step 15: Add Tightly Coupled On-Chip Memory to System
1. Now, add the tightly coupled on-chip memory to attach to the processor. From the
pick list, look inside the Memories and Memory Controllers > On-Chip folder, and
select On Chip Memory (RAM or ROM) and click Add.
If you have a Startix II device on your board, set the memory block type to M4K.
For other devices, leave it as the default. Keep the memory width at 32 bits, and
ensure the Total Memory Size to 4 kbytes (ie. 4096 bytes).
Finally, enable Dual-Port Access.
Click Finish, and rename the peripheral tightly_coupled_instruction_memory.
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2. Change the clock driving both tightly coupled memory ports to sys_clk, if necessary, and
using the Move up button, move the peripheral up in the system contents page until it
resides directly underneath the cpu. (This will make it easier to see its connections to the
cpu.)
3. Ensure that the appropriate master/slave connections are made between the cpu and the
Tightly Coupled Memory.
Toggling the System Interconnect Fabric Connections:
Click your mouse on the appropriate dots in the tightly coupled memory’s connectivity
diagram in order to toggle the connections as shown below: (Note: the connected state is
solid; while the disconnected state is white.)
Port S1 of the tightly_coupled_instruction_memory should be connected to the cpu’s
tightly_coupled_instruction_master_0 master port, and port S2 should connect to the
cpu’s data_master port.
4. You will now change the base addresses of the tightly coupled master ports (S1 and S2)
so that they do not overlap any of the other peripherals in the design.
5. As a first step, go to the System menu and choose Auto Assign Base Addresses for the
system. A number of error messages will disappear.
6. Next, look in the SOPC Builder message window (toward the top), and find the cpu
warning message that suggests where you can locate your tightly coupled memories in the
memory map to produce optimal performance. You will have to scroll the message
window to the right to see the entire message.
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For instance, it may suggest that you locate both ports of the tightly
_coupled_instruction_memory to at least base address 0x02402000. Whatever the
case, double-click in the Base address box and edit the values to their recommended
settings as shown.
Then lock the values (right-click > Lock Base Address).
Example:
Step 16: Take a Look at Your System
1. To again ensure that all base addresses are valid, go to the system menu or right click on
any one of the base addresses in the table and select Auto-Assign Base Addresses.
2. Your SOPC Builder System Contents page should now appear similar to the following:
For the Nios II Cyclone II and Stratix II rohs kits:
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For the Cyclone III kits:
For all other Nios II kits:
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For the Stratix II DSP kits:
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Step 17: Establish Reset and Exception Handler Locations
1. Now, you will go back and set the exception and reset addresses for the Nios II
processor. Double-click on the “cpu” peripheral, and look at the bottom of the Core
configuration page: This is where you can establish the reset and exception addresses of
the CPU.
Select:
ext_flash for the Reset Address and
ext_ram (or ext_ssram) for the Exception Address
Click Finish.
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2. In the System Contents tab Warning and Message area, check to see if you have any
remaining memory address violations. If you do, then go to the System menu one more
time, and select Auto-Assign Base Addresses. This should get rid of them.
3. In SOPC Builder, click Next to go to the System Generation tab, and uncheck the
Simulation checkbox if it is checked.
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4. Save your SOPC Builder system (File > Save).
5. Next, click Generate. SOPC Builder will now create the parameterized SOPC system.
Note: If you happen to receive a warning message in SOPC Builder that prevents you
from generating the system, check to make sure that all the peripherals are connected to
sys_clk. For example, you might encounter a message like:
the cpu/tightly_coupled_instruction_master_0 may connect to 1 slave only
If setting sys_clk does not solve your problem, you may have to close SOPC Builder and
then re-open it again in order to register the change you just made.
6. After SOPC Builder has finished generating your embedded sub-system, open the
niosII_lab.bdf schematic in Quartus II using File->Open or by double-clicking on it in
the Project Navigator:
7. Zoom in or out in the schematic, as needed, using the magnifying glass utility. The
schematic editor should resemble the following: (Note: There will be some variation in
the schematic depending on what kit you have.)
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8. Then switch back to the Selection Tool arrow, and double-click anywhere on the
schematic editor to open the Symbol viewer.
Once in Symbol viewer, Open the Project folder, and click on the niosII symbol.
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9. The block symbols for each, respective, system should appear as follows:
Cyclone II and Stratix II rohs Nios II development kit systems:
clk
reset_n
in_port_to_the_button_pio[3..0]
ssram_clk
sys_clk
address_to_the_ext_flash[23..0]
read_n_to_the_ext_flash
select_n_to_the_ext_flash
w rite_n_to_the_ext_f lash
address_to_the_ext_ssram[20..0]
adsc_n_to_the_ext_ssram
bw _n_to_the_ext_ssram[3..0]
bw e_n_to_the_ext_ssram
chipenable1_n_to_the_ext_ssram
outputenable_n_to_the_ext_ssram
out_port_from_the_led_pio[7..0]
out_port_from_the_seven_seg_pio[15..0]
data_to_and_from_the_ext_flash[7..0]
data_to_and_from_the_ext_ssram[31..0]
NiosII
inst
Cyclone III systems:
clk
reset_n
in_port_to_the_button_pio[3..0]
sys_clk
be_n_to_the_ext_ram[3..0]
ext_ram_bus_address[22..0]
read_n_to_the_ext_f lash
read_n_to_the_ext_ram
select_n_to_the_ext_flash
select_n_to_the_ext_ram
w rite_n_to_the_ext_f lash
w rite_n_to_the_ext_ram
out_port_from_the_led_pio[7..0]
out_port_from_the_seven_seg_pio[15..0]
ext_ram_bus_data[31..0]
niosII
inst
DSP board systems:
clk
reset_n
in_port_to_the_button_pio[3..0]
sys_clk
address_to_the_ext_f lash[23..0]
read_n_to_the_ext_f lash
select_n_to_the_ext_f lash
w rite_n_to_the_ext_f lash
address_to_the_ext_ram[19..0]
be_n_to_the_ext_ram[3..0]
read_n_to_the_ext_ram
select_n_to_the_ext_ram
w rite_n_to_the_ext_ram
out_port_from_the_led_pio[7..0]
out_port_from_the_seven_seg_pio[15..0]
data_to_and_from_the_ext_flash[7..0]
data_to_and_from_the_ext_ram[31..0]
NiosII
inst
All other Nios II development kit systems:
10. Add the niosII component to your Quartus II project by pressing OK; then drop the
symbol into your schematic so that it’s pins line up exactly with the pin placements as
shown below. These pinouts have already been done for you.
Note: If the pins do not all line up exactly, then you will need to go back to SOPC
Builder and re-check your work.
Cyclone II and Stratix II rohs Nios II Development Kit systems will resemble this figure:
(Please refer to the schematic that corresponds to your particular development kit.)
Exercise Manual Designing with the Nios II Processor & SOPC Builder
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All Cyclone III Kit systems will resemble this figure:
All other Nios II Development kit systems will resemble this figure:
Exception: For the regular (ie. non-rohs) Stratix II Nios II development kits, the bus
width of the flash address is actually 24 bits (ie. ext_ram_bus_address[23..0]) because of
the flash selection you chose.
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While Stratix II DSP Development Kit systems will look like this:
11. Save the schematic (File > Save).
12. Save the Quartus II project (File > Save Project).
13. .Start compilation in Quartus II. by selecting Start Compilation from the Processing
menu.
14. When compilation completes, select OK.
You will continue from this point during the next lab.
END OF LAB 1
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Exercise Manual Designing with the Nios II Processor & SOPC Builder
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Lab 2
Software Flow
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Exercise Manual Designing with the Nios II Processor & SOPC Builder
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1. You will now download the Nios II FPGA design created in the previous lab to the Nios
development board.
Within Quartus II, go to the Tools menu, and select the Programmer. (If the .sof file
for your project does not populate the File field then click on the Add File button .
Then select file niosII_lab.sof and click Open.)
2. Tick the Program/Configure checkbox for that .sof file, and then click the Start
Programming icon .
If the Start Programming button is not enabled, make sure your Hardware Setup field (at
the top of the Programmer window) reads USB-Blaster or Byteblaster. If not, click on
the Hardware Setup button and choose USB-Blaster or Byteblaster from the drop-down
menu, and click Close.
3. Launch the Nios II IDE from SOPC Builder (see Nios II menu > Nios II IDE). Select
OK if the Nios II IDE Workspace Launcher dialog box appears.
4. Go to the Nios II IDE Workbench, and create a new software project by selecting New-
>Project from the File menu. Select Nios II C/C++ Application, and press Next.
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5. In the second page of the wizard, type niosII_training_project as the name of the
application to be created. Then verify that the .ptf file from your SOPC Builder session
(niosII.ptf) has automatically populated the SOPC Builder System field in the Select
Target Hardware pane.
6. Now, select the Blank Project template from the Select Project Template panel on the
left hand side of the window. The New Project window should now resemble the
following:
Exercise Manual Designing with the Nios II Processor & SOPC Builder
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7. Press Next, and select:
Create a new system library named: niosII_training_project_syslib.
Then, click Finish.
8. You have now created two new projects in the Nios II IDE - a Nios II C/C++
Application project and a system library project. However, the Nios II C/C++
Application project is blank and you need to add some source code to it.
To add the file, simple.c, to the project, first expand the niosII_training_project folder
in the Nios II IDE.
Then, from within Windows, browse to
~NiosII_2Day\<your_particular_kit>\nios_II_lab\software, and find simple.c.
Exercise Manual Designing with the Nios II Processor & SOPC Builder
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Drag simple.c into the niosII_training_project folder in the Nios II IDE as illustrated:
9. Now, highlight the niosII_training_project_syslib folder, right-click, and select
Properties.
Then, choose System Library from the left hand side of the Properties window. Ensure
that the stdout, stderr and stdin devices are set to jtag_uart and that the System clock
timer is set to sys_clk_timer.
For all boards except the Cyclone II board, set the Read-only data, Read/write memory,
and Program Memory fields to ext_ram. (For Cyclone II, set it to ext_ssram.)
Please refer to the figure on the next page.
drag
Exercise Manual Designing with the Nios II Processor & SOPC Builder
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10. Click OK.
11. Compile the program by highlighting the niosII_training_project folder in the Nios II
C/C++ Projects window; then right-click and select Build Project.
Note: You can choose to run this command in the background when prompted. This will
free up the tool, letting you continue to use it for other tasks; whereas, running it in the
foreground causes you wait for it to complete.
12. After the compiler has finished, download and run the program on the development
board:
Highlight the niosII_training_project folder then right-click and select
Run As-> Nios II Hardware. (see over)
Note 1: If Run terminates before the code downloads to your board, and you get a
message pertaining to the JTAG download cable. then select Run > Run…
and from the Target Connection tab choose the appropriate download cable
that you are using and then press Apply and Run (or see instructor).
Note 2: The Nios II IDE will actually Build the project automatically for you if you
just click Run As -> Nios II Hardware without you having to explicitly go
through the Build step. You can enable or disable this option in the Window
> Preferences.
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This will download the program to the development board. You should observe that the
console window in the Nios II IDE displays the printf statement (“Simple”) from the
simple.c file.
Press of any of the four buttons on the board (located under the LEDs) to shift the LED
pattern to the right.
0, 1, 2, 3
LEDs shift to the right
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13. Now, let’s run the debugger on this design and step through some code. Start the
debugger by once again highlighting the niosII_training_project software project folder,
then right-clicking on it, and selecting Debug As-> Nios II Hardware. The debugger
will launch, connect to the target, and download the program ready for debug.
Choose, Yes to switch perspectives when prompted.
14. Turn on line numbers in the C file editor. To do this, go to the Window menu, and select
Preferences. Open the General folder followed by the Editors sub-folder. Select Text
Editor; then check Show line numbers. Press OK.
15. Set breakpoints on line 22 and line 37 (on the first “if” and the second “while” stmt.).
To set a breakpoint, simply place the cursor on the line number or grey area next to it, and
double-click. A circle should now appear next to the line number indicating that a
breakpoint is set.
16. Click on the resume button .
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17. Now, go to the Variables window, and view the contents of the buttons variable. Notice
that the button value has been read (ie. whatever the “none-pressed” value is).
18. Click resume again. Since the if expression is false (ie. no buttons are pressed) the
statements within the curly braces are not executed, and thus you will not break on line
37. Instead you will break again on line 22.
19. Hold down the right-most button on the board and click resume. Notice that a new value
is stored in the buttons variable. (The value of led indicates its position on the board.)
20. Continue to hold down right-most button and click resume again.
Since a button was pressed when you advanced the debugger this time, the breakpoint on
line 37 is now caught, so the if condition must be true. Notice that the illuminated LED
has also changed position and the led variable has changed.
21. Release the button, and click on the resume button until the program returns to line 22.
22. Within the Variables window, select and highlight the value of buttons. Then, manually
change it to 0xe, and hit Enter. Click resume. Notice that the if statement is executed
again due to the change you just made, and you end up on line 37.
Editing the variable values in this way is useful because it gives you a way to emulate
external hardware events or other conditions that may otherwise be difficult to replicate!
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23. Now terminate and remove the program. Go to the Debug sub-menu menu; right-
click on the software project thread, and select Terminate and Remove.
END OF LAB 2