Designing Clocked Synchronous State Machine
23
Design a clocked synchronous state machine which accepts two serial strings of digits of arbitrary length, starting with LSB and produces the sum and carry of the two bit streams as its output. The input bit streams could come from two shift registers clocked simultaneously. While Performing addition there is a possibility of a carry being generated. This carry if generated should be taken care of while adding the next LSB Let the inputs be X and Y Let the outputs be S and C Assuming Moore Machine Design
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Transcript of Designing Clocked Synchronous State Machine
Design a clocked synchronous state machine
which accepts two serial strings of digits of
arbitrary length, starting with LSB and produces
the sum and carry of the two bit streams as its
output. The input bit streams could come from two
shift registers clocked simultaneously. While
Performing addition there is a possibility of a carry
being generated. This carry if generated should be
taken care of while adding the next LSB
Let the inputs be X and YLet the outputs be S and C
Assuming Moore Machine Design
Obtaining the state DiagramAssume initial condition to be SC = 00Let the state be represented by state AIf XY = 00, then output SC = 00, Same state A
= 01, then output SC = 10, goes to state B= 10, then output SC = 10, goes to state B= 11, then output SC = 01, goes to state C
11
01,1000
00
A
10
B
01
C
Obtaining the state DiagramAssume machine has moved to state BIf XY = 00, then output SC = 00, goes to state A
= 01, then output SC = 10, same state B= 10, then output SC = 10, same state B= 11, then output SC = 01, goes to state C
11
01,1001,10
11
000000
A
10
B
01
C
Obtaining the state DiagramAssume machine has moved to state CIf XY = 00, then output SC = 10, goes to state B
= 01, then output SC = 01, same state C= 10, then output SC = 01, same state C= 11, then output SC = 11, goes to state D
11
01,1001,10
11
00
11
00
01,1000
00
A10
B
01
C11
D
Obtaining the state DiagramAssume machine has moved to state DIf XY = 00, then output SC = 10, goes to state B
= 01, then output SC = 01, goes to state C= 10, then output SC = 01, goes to state C= 11, then output SC = 11, same state D
11
01,1000 01,10
1101,1000
01,10
11
0011
0000
A
10
B
01
C
11
D
Obtaining the state/output table
State/output table
State Input XY
S 00 01 10 11
A A B B C
B A B B C
C B C C D
D B C C D
Next State S*
Output
SC
00
10
01
11
Assigning state variable to obtain transition/output
table Transition/output table
Encoding A = 00, B = 01C = 10, D = 11 Choosing D type flip flops
State Input XY
Q1Q0 00 01 10 11
00 00 01 01 10
01 00 01 01 10
10 01 10 10 11
11 01 10 10 11
Next State Q1*Q0*
Output
SC
00
10
01
11
Constructing the excitation table
Excitation/output table
State Input XY
Q1Q0 00 01 10 11
00 00 01 01 10
01 00 01 01 10
10 01 10 10 11
11 01 10 10 11
Output
SC
00
10
01
11
D1D0
Transferring onto K-maps to derive excitation
equations Excitation table
State Input XY
Q1Q0 00 01 11 10
00 0 0 1 0
01 0 0 1 0
11 0 1 1 1
10 0 1 1 1
YQXQYXD 111
Transferring onto K-maps to derive excitation
equations Excitation table
State Input XY
Q1Q0 00 01 11 10
00 0 1 0 1
01 0 1 0 1
11 1 0 1 0
10 1 0 1 0
10 QYXD
Output equationsExcitation/output table
State Input XY
Q1Q0 00 01 10 11
00 00 01 01 10
01 00 01 01 10
10 01 10 10 11
11 01 10 10 11
Output
SC
00
10
01
11
0QS 1QC
Circuit (logic) diagram
excitation equations
output equations
D Q
Q
X
S
Y Q1
C
Clk
0QS 1QC
111 QYQXYXD 10 QYXD
D Q
Q
Q0D0
D1 Q1
Design a clocked synchronous state machine
which outputs a logic ‘1’ whenever the input
sequence 0101 is detected, and which outputs a
‘0’ otherwise. The input is supplied serially one
bit at a time. The machine should also detect
overlapping sequences as shown below.
Input 001010100010100
Output 000010100000100
Let the input be X and output be Z
Assuming Mealy machine design
Obtaining the state Diagram
Assume initial condition to be Z = 0Let the initial state be represented by state A If X = 0, then output Z = 0, goes to state B
= 1, then output Z = 0, Same state A
A B
0/01/0
X/Z
Obtaining the state Diagram
Assume machine has moved to state B If X = 0, then output Z = 0, Same state B
= 1, then output Z = 0, goes to state C
A B
0/01/0
X/Z
C
0/0
1/0
Obtaining the state Diagram
Assume machine has moved to state C If X = 0, then output Z = 0, goes to state D
= 1, then output Z = 0, goes to state A
A B
0/01/0
X/Z
C
0/0
1/0
D
1/0
0/0
Obtaining the state Diagram
Assume machine has moved to state D If X = 0, then output Z = 0, goes to state B
= 1, then output Z = 1, goes to state C
A B
0/01/0
X/Z
C
0/0
1/0
D
1/0
0/0
1/1
0/0
Obtaining the state/output table
State/output table
Next State S*, Z
State Input X
S 0 1
A B,0 A,0
B B,0 C,0
C D,0 A,0
D B,0 C,1
Assigning state variable to obtain transition/output
tableTransition/output table
Next State Q1*Q0*, Z
Encoding A = 00B = 01 C = 10D = 11
Choosing D type flip flop
State Input X
Q1Q0 0 1
00 01,0 00,0
01 01,0 10,0
10 11,0 00,0
11 01,0 10,1
Constructing the excitation table
Excitation/output table
D1D0, Z
State Input X
Q1Q0 0 1
00 01,0 00,0
01 01,0 10,0
10 11,0 00,0
11 01,0 10,1
Transferring onto K-maps to derive excitation &
output equationsExcitation/output table
D1D0, Z
State Input X
Q1Q0 0 1
00 01,0 00,0
01 01,0 10,0
10 11,0 00,0
11 01,0 10,1
State Input X
Q1Q0 0 1
00 0 0
01 0 1
11 0 1
10 1 0
D1
State Input X
Q1Q0 0 1
00 1 0
01 1 0
11 1 0
10 1 0
D0
XQQXQD 0101 XD 0
Transferring onto K-maps to derive excitation &
output equationsExcitation/output table
D1D0, Z
State Input X
Q1Q0 0 1
00 01,0 00,0
01 01,0 10,0
10 11,0 00,0
11 01,0 10,1
State Input X
Q1Q0 0 1
00 0 0
01 0 0
11 0 1
10 0 0
ZXQQZ 01
Circuit (logic) diagram
excitation equation
output equations
XQQXQD 0101XD 0
XQQZ 01
D Q
Q
Q0Z
Q0' Q1
Clk
D Q
Q
Q0D0
D1 Q1
X'X
