Design Sensitivities to Variability: Extrapolations and Assessments in Nanometer VLSI Y. Kevin Cao...
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Transcript of Design Sensitivities to Variability: Extrapolations and Assessments in Nanometer VLSI Y. Kevin Cao...
Design Sensitivities to Design Sensitivities to Variability: Extrapolations Variability: Extrapolations
and Assessments in and Assessments in Nanometer VLSINanometer VLSI
Y. Kevin Cao*, Puneet Gupta+, Andrew Kahng+,
Dennis Sylvester#, Jie Yang#
*UC Berkeley EECS Dept. +UC San Diego ECE Dept.
#U. Michigan EECS Dept.
2
IntroductionIntroduction
Why process variability is important now: Optical lithography: feature
size limited by diffraction, starting with 0.35 μm generation
Same patterns look the same? ITRS: one of the biggest
challenges is Lgate control Affects both circuit’s
performance and yield 0.35 μm global line width
3
MotivationMotivation
Necessity of Design Sensitivity Study Cost of corrections
May be proportional to complexity of masks Not all corrections are implementable Previous studies
Lacking quantified projections of variation in scaled technology
Overly simplified circuit topologies and performance models
Ignoring physical correlations
4
Interpretation of ResultsInterpretation of Results
Returns for alternative process improvements measured as Selling point yield
Selling point: delay point which gives 99.7% parametric yield with all parameters varying nominally
Required guardbanding 3/mean is taken as the required guardbanding,
assuming 99.7% to be the target parametric yield and the delay distribution to be Gaussian
Contributes insights to the impact of process variation through the next two ITRS technology nodes
5
Correlation SpecificationCorrelation Specification
Vth0 = (Tox, Nch, Leff, and Xt) Perfect correlation between NMOS and
PMOS within a gate Negative correlation between metal
width and spacing variation as well as ILD and H variation
Spatial correlation among devices and interconnect Correlation coefficient linear decays with
distance
f
6
Comparison with plotsComparison with plots
“No correlation coefficient model” is about 6% optimistic
We could lose 14% more from the “perfectcorrelation model”
950 1000 1050 1100 1150 1200 1250 13000
100
200
300
400
500
600
700
800
900
Perfect correlation3/mean=15.52%
0 correlation3/mean=12.75%
RLC simulationSpatial correlation3/mean=13.56%
No
. o
f D
ata
Po
ints
(T
ota
l=5
00
0)
Global Delay (ps)100nm
7
Required GuardbandingRequired Guardbanding
The guardbanding value drops from 18.5% for 180nm to 13% for 70nm
Effect of process control Leff control has the
most impact Intense sensitivity to
Vdd
180nm 130nm 100nm 70nm10
15
20
25
30
35
Req
uir
ed
Gu
ard
ban
din
g (
%)
Technology
Baseline L
eff(0.5)
Leff
(2) Vdd(0.5) Vdd(2)
Effect of process control on required guardbanding to achieve 99.7% parametric
yield
8
Selling Point Parametric YieldSelling Point Parametric Yield
Individual analysis for the effect of Leff and Vdd control on selling point parametric yield
Loose control of Leff (Vdd ) can cause loss up to 5% (2%) in yield
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
94
95
96
97
98
99
100
Sel
ling
Po
int
Yie
ld (
%)
of Leff
180nm 130nm 100nm 70nm
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
94
95
96
97
98
99
100
Sel
ling
Po
int
Yie
ld(%
)
of Vdd
180nm 130nm 100nm 70nm
9
No Further Control No Further Control
Effects of no further investments for controlof Leff and Vdd
compared with 180nm technology node
Results confirm that performance sensitivity
to Leff and Vdd variation
is high
10
ConclusionsConclusions
More accurate results with realistic correlation among variability included
With qualified projection of variation in scaled technology, the impact of variability is actually decreasing
Performance very sensitive to Leff variation Considering the huge cost of Leff control, tackling Leff
variation from design perspective may be more cost-effective
Vdd is an important source of variation The control of Vdd variation may give a better ROI than Leff control for achieving the same amount of variability–tolerance as technology scales
11
Ongoing ResearchOngoing Research
Incorporate multiple correlated critical paths More trials in MC simulation for more
accurate results Set up an analytical flow to parallel testbed
of MC simulation using HSPICE Set up cost-driven correction flow based
on the previous results Relax specs on some (non-critical) gates Goal: reduce costs with zero parametric yield
penalty
Toward Performance-Driven Reduction of the Cost of
RET-Based Lithography Control
Dennis Sylvester ([email protected]),
Jie Yang (Univ. of Michigan, Ann Arbor)Puneet Gupta, Andrew B. Kahng (UC San
Diego)
13
Trends in Mask Cost..
RETs increase mask feature complexities and hence mask costs
The average mask set produces only 570 wafers amortization of mask cost is difficult
Mask writers work equally hard to perfect critical and non-critical shapes; errors found in either during mask inspection will cause the mask to be discarded
14
MinCorr: The Cost of Correction Problem..
Define the selling point as the circuit delay which achieves 99% parametric yield
The MinCorr problem seeks a level of correction for each layout
feature such that a prescribed selling point delay is attained
with minimum total cost of corrections.
15
MinCorr: Parallels to Gate Sizing..
Use off-the-shelf synthesis tool, along with yield library similar to timing libraries (e.g., .lib) to perform OPC “sizing” operation
Gate Sizing MinCorr
Cell Area Cost of correction
Nominal Delay Delay (+k)
Cycle Time Selling point delay
Die Area Total cost of OPC
16
MinCorr: Yield Aware Library Characterization
Mask cost is assumed proportional to number of layout features
Monte-Carlo simulations, coupled with linear interpolation, are used to estimate delay variance given the CD variation
We generate a library similar to Synopsys .lib with (+3) delay values for various output loads
17
Experiments and Results
Three levels of OPC considered Input slew dependence ignored Interconnect variation ignored
Type of OPC
Ldrawn (nm)
3 of Ldrawn
Figure
Count
Delay (, ) for
NAND2X1
Aggressive
130 5% 5X (60.7, 7.03)
Medium 130 6.5% 4X (60.7, 7.47)
No OPC 130 10% 1X (60.7, 8.79)
Sample Result of Library Generation
18
Experiments and Results
4 combinational testcases ranging from 1600 to 9400 gates
Design Normalized Cost Normalized Selling Point Delay
alu128 5.0 (Aggressive OPC) 0.9644
4.0 (Medium OPC) 0.9739
1.0 (No OPC) 1.0000
1.0657 0.9644
1.0119 0.9976Sample results on 9410 gate testcase alu128
19
Experiments and Results
Small (4%) selling point delay variation between max- and min-corrected versions of design
Sizing-based optimization achieves 60-79% reduction in OPC cost without sacrificing parametric yield