Design Review Residue Stage Op Ampathena.ecs.csus.edu/.../ADC1_residue_opamp_PDR.pdf · Folded...
Transcript of Design Review Residue Stage Op Ampathena.ecs.csus.edu/.../ADC1_residue_opamp_PDR.pdf · Folded...
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Design ReviewResidue Stage Op Amp
Divyesh Shah
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Overview• Introduction• Specifications• Design of the Op Amp• Calculations for the W and L sizes.• Offset calculation• Simulation Results over corners• Switched capacitor CMFB (Design and
Simulations)
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Introduction
• Basic op amp requirements:High gain High bandwidth
• Architectural considerations:Two stage op ampFolded cascode op ampTelescopic op amp
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Architecture Recap
• The selected architecture
• Limited output swing• High gain• High bandwidth
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Specifications Required
• Gain >= 80db• Bandwidth >= 250Mhz• Phase Margin (when β=1/4) = 65-70degrees.• Offset Value <= 10mv• Settling time <= 18ns.
Designed op amp needs to meet all the above requirements.
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Initial Design
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Initial Design: Issues
• The gain of the circuit was found to be lower than the required specification.
• The phase and bandwidth were also barely meeting spec.
• Solutions:-• Redesign• Add an additional cascode device.
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Sizing calculations for the op amp (initial)
Equations and values used:-
Id= µnCox(w/L)/2 * (Von)2
µnCox= 114 and µpCox=53
Vtn=0.8 Vtp=0.9
Bandwidth=gm1/CLCL=1.25pF
Gm= 2*Id/VonRout= 1/lambda*Id
• Input devices:- Id=500µA Von=0.25VW/L= 100u/0.75u
• Pmos Load:- Id=500µA Von=0.4VW/L= 180u/1.5u
• Tail Current Mirror:- Id=1050µA Von=0.4VW/L= 120u/1u
• Biasing device:- Id=50µA Von=2Von(nmos) + Vt(0.8)W/L= 3u/0.6u
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Proposed Design
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Bias current Network• The input bias
current=75µA
• Ratio of devices1:5 and hence mirrored current=375µA.
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Pmos wide swing current mirror and load
• A ratio of 1/8 between for the wide swing mirror
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Input Devices• Sized the second
cascode lower to increase the bandwidth
• First cascode device was sized to get the required phase margin
• Input devices were sized bigger to increase gm and hence the gain
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Designed Vs Final ValuesW/L Von (mV) Id (µA)
Calculated 100/0.75
250 500
Final 320/0.75
180 375
Calculated 180/1.5
400 500
Final 250/1.5
350 375
Calculated 120 400 1100
Final 200 350 825
Tail current
PmosLoad
I/Pdevices
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Simulation at SS 85degree 4.5V
Gain and phase plot
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Simulation result Low Supply=4.5V and high Temperature=85
Gain UGBW Phase(at12d)
DesiredValues
>80db >250Mhz 70o-75o
SS 85db 257Mhz 70
FF 83db 316Mhz 72
SF 84db 280Mhz 72
FS 85db 290Mhz 71
TT 85db 267Mhz 71
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Simulation at room temp and full supply voltage
Gain and Phase Plot
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Simulation results at Temp=27 and supply voltage=5V
Gain UGBW Phase(at12d)
DesiredValues
>80db >250Mhz 70o-75o
SS 88db 290Mhz 70FF 86db 382Mhz 72FS 88db 348Mhz 70SF 86db 328Mhz 71TT 87db 327Mhz 70
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Switched Capacitor CMFB
• Design Considerations:-– The switch sizes can be minimum– The capacitors being switched can be between one-quarter to
one-tenth of non-switched capacitors.– Cannot be too big as they might add extra load to the op amp
during phase2 and cannot be too small.
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Designed S/W cap CMFB ckt.
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CMFB calculations• To ensure the stability and reasonable
settling of the common mode feedbackthe bandwidth can be 50%of the unity gain bandwidth.
The calculated value of Ccm was found to be 50fF.and hence the values greater than 50fF would give us the stability required and settling time.
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Floor plan for the op-ampQuiet Routing channel
Dedicated shielded well for the inputs
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Issues faced and solutions
• Issues found when integrated with the residue stage s/w cap circuit.
• High Overshoot• Solutions done• Adjust the size of the cascode device for a
higher phase margin.
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Conclusions
• The designed op amp meets the specifications.
• Future considerations:-– Design issues to be resolved before layout.– Optimize design– CMFB stability check
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Appendix
• Offset Calculations• Avtn=10.71 Avtp=17.8 βn=.1% βn=.2% • σvtn(1,2)=1.26mv σvtn(3,4)=1.26mv • σvtp(1,2)=1.21mv • σVos=2.2mv and hence 3σ=6.8mv <=
10mV (meets specifications)• The final devices used are bigger in size
and hence will have lower value of offset