Design of Sequential Circuits - University of Belgradepoincare.matf.bg.ac.rs/~vladaf/Courses/Matf...
Transcript of Design of Sequential Circuits - University of Belgradepoincare.matf.bg.ac.rs/~vladaf/Courses/Matf...
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CSC9R6 Computer Design. Spring 2006 Slide 94
Design of Sequential Circuits
Seven Steps: Construct a state diagram (showing contents of flip flop and
inputs with next state) Assign letter variables to each flip flop and each input and
output variable Construct a state table (m flip flops, n inputs, p outputs give
2n+m rows, and n + p + 2*m columns!) Choose a flip flop type Extend state table into an excitation table (given current state
and next state, what are flip flop inputs?) Obtain Boolean equations for flip flop inputs and any outputs of
the combinational part of the circuit Draw the circuit!
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CSC9R6 Computer Design. Spring 2006 Slide 95
Synchronous Binary Counter with Enable
Informal description: the counter counts 00,10,01,11 when E(enable) = 1. When E = 0 nothing happens.
Step 1: State diagram
Inside the states are the flip flop values, and the transitions arelabelled with input values (E). There are no outputs.
E = 1 00
10
01
11E = 1E = 1
E = 1
E = 0
E = 0
E = 0E = 0
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CSC9R6 Computer Design. Spring 2006 Slide 96
Synchronous Binary Counter
Step 2: Assign names A and B to flip flops. Step 3: State table
Present input nextstate stateA B E A B0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
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CSC9R6 Computer Design. Spring 2006 Slide 97
Excitation Tables
Characteristic tables of flip flops give next state fromcurrent inputs and state. During design we know nextstate and current state, so need to know what inputs toapply.
This is given by the excitation table. E.g. JK flip flop excitation table is
Q(t) Q(t+1) J K0 0 0 x0 1 1 x1 0 x 11 1 x 0
x means “don't care”.Eg 00 means no change 01 means clearBoth have the sameeffect.
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CSC9R6 Computer Design. Spring 2006 Slide 98
Other Excitation Tables
SR flip flop
Q(t) Q(t+1) S R0 0 0 x0 1 1 01 0 0 11 1 x 0
D flip flop
Q(t) Q(t+1) D0 0 00 1 11 0 01 1 1
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CSC9R6 Computer Design. Spring 2006 Slide 99
Synchronous Binary Counter
Step 4: Choose JK flip flops Step 5: Excitation table
present input next Flip Flop inputsstate stateA B E A B JA KA JB KB0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
The clock is implicit in the above.
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CSC9R6 Computer Design. Spring 2006 Slide 100
Synchronous Binary Counter
Step 6: Derive Boolean Equations Inputs to the circuit are E, A, B. Outputs from the circuit are JA, KA, JB, KB. (and A and B) Use the state table as a truth table to derive Karnaugh maps
and Boolean functions.
Result: JA = E KA = E JB = A.E KB = A.E
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CSC9R6 Computer Design. Spring 2006 Slide 101
Synchronous Binary Counter
Step 7: Draw the circuit!
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CSC9R6 Computer Design. Spring 2006 Slide 102
Digital Components
Sequential and Combinational systems can be built frombasic gates (AND, OR, NOT) and flip-flops
Other (slightly) larger scale components exist to make design easier
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CSC9R6 Computer Design. Spring 2006 Slide 103
Decoder
A decoder takes a binary number represented in n bits (so 0 - (2n - 1)
values possible) produces output on the appropriate one of m (= 2n) output lines
These are also called n to m line decoders. Applications of a decoder include:
detecting specific inputs selecting chips selecting I/O ports comparing numbers converting from one base to another ….
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CSC9R6 Computer Design. Spring 2006 Slide 104
Decoder
Eg 2 to 4 line decoderX1 X0 out0 0 Y0=10 1 Y1=11 0 Y2=11 1 Y3=1
all other outputs = 0
Enable input means all outputs 0 if Enable = 0
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CSC9R6 Computer Design. Spring 2006 Slide 105
Decoder Expansion
Enable is useful if you need to join two decoderstogether.
Eg When X2 = 0 the bottomdecoder (MSB) is disabled
X0 and X1 produce dataoutputs Y0 - Y3.
When X2 = 1 the topdecoder is disabled
X0 and X1 produce dataoutputs Y4 - Y7
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CSC9R6 Computer Design. Spring 2006 Slide 106
Encoder
An Encoder performs the inverse operation to adecoder. Given m = 2n inputs
outputs the corresponding binary code on n lines
Applications: keyboard encoder - one key press makes an input line high converting numbers from one base to another
Y0Y1Y2Y3
X0
X1
Encoder
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CSC9R6 Computer Design. Spring 2006 Slide 107
Encoder
OR gates can be used to implement the encoder Only 1 input should be 1 at any time
X0 = Y1 + Y3X1 = Y2 + Y3
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CSC9R6 Computer Design. Spring 2006 Slide 108
Multiplexers
A multiplexer is a data selector. Data is received on one of 2n input lines and directed to a single output line.
The selection of a particular input line is determined bythe selection inputs.
A 2n to 1 multiplexer has 2n data input lines, n selectlines and 1 output.
Applications: parallel to serial conversion hard coding of functions (see later)
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CSC9R6 Computer Design. Spring 2006 Slide 109
Multiplexer
Eg 4 to 1 multiplexer Whichever input S1 S0
selects is pipedstraight to Y.
S1 S0 Y0 0 D00 1 D11 0 D21 1 D3
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CSC9R6 Computer Design. Spring 2006 Slide 110
Demultiplexer
The converse operation to the Multiplexer Application - Data distribution
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CSC9R6 Computer Design. Spring 2006 Slide 111
Register Transfer and MicroOperations
Basic gates and larger components can be put togetherwith data and control paths to construct more complexsystems
How do we talk about the dynamic changes in systems,i.e. A set of registers and their purpose The operations which may be performed on the content of the
registers The controls which determine what happens and when
Operations on data stored in registers are called microoperations: logical, shift and arithmetic operations
The register transfer language is a concise andprecise means of describing those operations
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CSC9R6 Computer Design. Spring 2006 Slide 112
Bus construction
How does information get from one register to another? Direct connection of all registers
impossible - there are too many wires
Common bus system a set of common lines - one for each bit - through which the
binary information is transferred Control signals determine which register are active at any point
and therefore which data is present on the bus or which register should be loading the data from the bus
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CSC9R6 Computer Design. Spring 2006 Slide 113
Bus construction (2)
Use multiplexers to channel the data Selection lines choose which register delivers
information to the bus The number of multiplexers required is n, that is, no. of
bits in each register Each multiplexer is a k to1 mux, where k is the number
of registers The bus is usually implicit in the register transfer
language constructs
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CSC9R6 Computer Design. Spring 2006 Slide 114
Bus Construction (3)
4 × 1mux
30123
4 × 1mux
20123
4 × 1mux
10123
4 × 1mux
00123
A2B2C2 A1B1C1 A0B0C0
0123register A
A0A1A2
0123register B
B0B1B2
0123register C
C0C1C2
S0S1
4 linecommonbus
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CSC9R6 Computer Design. Spring 2006 Slide 115
Buses (4): Another example
4 × 1mux
30123
4 × 1mux
20123
4 × 1mux
10123
4 × 1mux
00123
0123register D
D0D1D2
A2B2C2D2 A1B1C1D1 A0B0C0D0
0123register A
A0A1A2
0123register B
B0B1B2
0123register C
C0C1C2
S0S1
4 linecommonbus
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CSC9R6 Computer Design. Spring 2006 Slide 116
Registers
Simple register constructed from D type flip flops.
8 bit register with parallel load. This uses the clock asan enable. Not always good!
D0 D1 D7
Q0 Q1 Q7
Clock
DEn
Q DEn
Q DEn
Q…
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CSC9R6 Computer Design. Spring 2006 Slide 117
Synchronised Registers with load
Here, the clockprovides pulses (tosynchronise the wholesystem).
The enable (load)signals when data (I0to I3) is to be loaded.
If no load signal thenold values (A0 to A3)are fed back.
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CSC9R6 Computer Design. Spring 2006 Slide 118
Shift Register
Can do more than just store data - can also manipulate it. shift its contents in one or both directions
Implemented by a chain of flip flops.
serial in/serial out - leftmost is least significant bit. data shifts left to right, moving from one flip flop to the next every
clock pulse - recall that this implements multiplication by 2(assuming LSB is at the left)
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CSC9R6 Computer Design. Spring 2006 Slide 119
Timing Diagram
Clock
In
Q1
Q2
Q3
Q4
1 2 3 4 5 6 7 8
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CSC9R6 Computer Design. Spring 2006 Slide 120
Example: Universal Shift Register
Can do serial in/serial out (SISO)
serial in/parallel out (SIPO) all Q outputs are externally accessible
parallel in/serial out (PISO) all P inputs simultaneously
parallel in/parallel out (PIPO)
data in data out
data out
data in
data in
data out
data in
data out
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CSC9R6 Computer Design. Spring 2006 Slide 121
Bidirectional shift register with parallel load
Has everything! (a Universal Register) Clock input Shift right and serial line to take new LSB Shift left and serial line to take new MSB Parallel load with n lines Parallel output on n lines Control state
Applications: time delay (input pulse advances each clock tick) conversion of parallel data to serial data and back again counter (seen already) arithmetic (multiplication and division)
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CSC9R6 Computer Design. Spring 2006 Slide 122
Bidirectional Shift Register
S1 and S0 select data inputs
S1 S0 = 00 means no change
S1 S0 = 01 means shift right(multiply: serial input for A0,previous flip-flop for others)
S1 S0 = 10 means shift left(divide: serial input for A3,next flip-flop for others)
S1 S0 = 11 means parallelload
LSB
MSB
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CSC9R6 Computer Design. Spring 2006 Slide 123
Logic Micro Operations
All 16 logic micro-operations can beimplemented using 4 basic operations: AND,OR, XOR and complement
S1 S0 Output Operation0 0 Ei = Ai ∧ Bi AND0 1 Ei = Ai ∨ Bi OR1 0 Ei = Ai ⊕ Bi XOR1 1 Ei = Ai Complement
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CSC9R6 Computer Design. Spring 2006 Slide 124
Logic Micro Operations
Logic micro-operations are carried out bitwise on registers,therefore this whole circuit is repeated for every bit of the register. i.e. if register A has 8 bits, then there are 8 copies, one for each Ai , i =
0 ... 7 The selection variables are applied to all stages simultaneously
E.g. A = 01101001B = 10101010
ThenA ∧ B = 00101000
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CSC9R6 Computer Design. Spring 2006 Slide 125
Shift Operations
Bidirectional shift register (of slide 122) - but this needs1 clock pulse to load the data and another to make theshift too slow
A combinational circuit is more efficient The register to be shifted is placed on a common bus
connected to the shifter, and the shifted number isloaded into the register, taking only 1 clock pulse
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CSC9R6 Computer Design. Spring 2006 Slide 126
Shift Operations(2)
Function tableselect outputs H0 H1 H2 H30 IR A0 A1 A21 A1 A2 A3 IL
MSB
mux
mux
mux
muxSerial input (IL)
A0
A1
A2
A3
Serial input (IR) H0
H1
H2
H3
S01
S01
S01
S01
select (0 for shift right, 1 for shift left) LSB
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CSC9R6 Computer Design. Spring 2006 Slide 127
Arithmetic ops: Binary adder
Calculates the arithmetic sum of2 binary numbers of any length
Constructed using a cascade offull adders (which add 2 bitsand a carry)
subscript 0 is least significantbit
n bit binary adder requires n fulladders (or n-1 full adders andone half adder)
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CSC9R6 Computer Design. Spring 2006 Slide 128
Binary Adder-Subtractor
Subtract/Add controls themode (+ or -)
If 0, the circuit is an adder, (Bi⊕ 0 = Bi)
If 1, the circuit is a subtractor(Bi ⊕ 1 = Bi')(and carry in C0 = 1)
implements + and - together
For unsigned numbers, subtraction is A - B if A ≥ B, 2's complement of (B- A ) if A < B
For signed numbers, subtraction is A - B if there is no overflow
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CSC9R6 Computer Design. Spring 2006 Slide 129
Binary Incrementer
implements + 1 Option 1 - use a counter
when the clock is enabled the contents of the register goes upby 1
Option 2 -independent ofregister
Use n half adders incascade
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CSC9R6 Computer Design. Spring 2006 Slide 130
Arithmetic Circuit
All operations can be implemented by a compositecircuit (in the same way as all logic micro-operationswere implemented in a single circuit)
The circuit calculatesD = A + Y + Cin
The multiplexers select the function by varying Y and the carry
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CSC9R6 Computer Design. Spring 2006 Slide 131
Arithmetic Circuit
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CSC9R6 Computer Design. Spring 2006 Slide 132
Arithmetic Circuit Functions
Function TableSelect input outputS1 S0 Cin Y D=A + Y + Cin micro-operation0 0 0 B D = A + B add0 0 1 B D = A + B + 1 add with carry0 1 0 B D = A + B subtract with borrow (A - B - 1)0 1 1 B D = A + B + 1 subtract1 0 0 0 D = A transfer A1 0 1 0 D = A + 1 increment A1 1 0 1 D = A - 1 decrement A1 1 1 1 D = A transfer A
ignore B and just give 0signore B and just give 1s
For example, whensubtracting A(2n)from B(2n) use thecircuit twice (or 2instances hooked up)
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CSC9R6 Computer Design. Spring 2006 Slide 133
Hardware: Arithmetic Logic Shift Unit
Instead of having separate sub-circuits for each kind ofmicro-operation most computers have a specialised unitwith associated storage registers this is the Arithmetic Logic Unit (ALU) often just the arithmetic & logic operations, but sometimes also
the shift operation
The next slide shows the circuitry for 1 bit - this isrepeated for n bits of the register size
The micro-operation is selected using S1 S0 the output of the arithmetic unit or logic unit or shifts is
selected by S3 S2 A Cin also affects which operation is chosen
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CSC9R6 Computer Design. Spring 2006 Slide 134
Hardware: Arithmetic Logic Shift Unit
4 × 1MUX
0123
select
One stage oflogic circuit (as
on slide 123)
S3S2S1S0
Bi
Ai
Ai-1Ai+1
Fi
shl
shr
Ei
Di
Ci
Ci+1
One stage ofarith circuit (ason slide 131)
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CSC9R6 Computer Design. Spring 2006 Slide 135
Function Table
S3 S2 S1 S0 Cin Operation Function 0 0 0 0 0 F = A + B addition 0 0 0 0 1 F = A + B + 1 add with carry 0 0 0 1 0 F = A + B subtract with borrow 0 0 0 1 1 F = A + B + 1 subtraction 0 0 1 0 0 F = A transfer A 0 0 1 0 1 F = A + 1 increment A 0 0 1 1 0 F = A - 1 decrement A 0 0 1 1 1 F = A transfer A 0 1 0 0 x F = A ∧ B AND 0 1 0 1 x F = A ∨ B OR 0 1 1 0 x F = A ⊕ B XOR 0 1 1 1 x F = A complement A 1 0 x x x F = shr A shift right A into F 1 1 x x x F = shl A shift left A into F