DESIGN OF PARITY GENERATOR AND PARITY CHECKER USING ... · cellular automata (QCA) is an emerging...

DESIGN OF PARITY GENERATORAND PARITY CHECKER USINGQUANTUM DOT AUTOMATA

MummadiSwathi1, UdariGnaneshwara chary2

Asst Professor’ Dept. of CSE,B.V.Raju Institute of Technology,

Narsapur, Medak.

April 30, 2018

Abstract

Lossless data transmission is very important in digitaldata communication. An ultra-high speed Quantum dotcellular automata (QCA) is an emerging technology whichtransfer the information with high speed and low power. Inthis paper, we are going to explain about the design of evenand odd parity generator and checker circuit for 3 and 4bits. The proposed 4 bit parity checker circuit occupies anarea of —–um2. QCA designer 2.0 is used for all proposedlayouts.

Key Words:QCA, Parity Generator, Parity Checker,Qubit.

1 Introduction

In computer networks, while data transmission there is a possibilityof getting errors that is data loss. The role of parity generator is,it generates parity bit while data is transferred from one device toother device. In this we have even parity and odd parity based onnumber of ones in the transferring data. The role of Parity checkeris to check whether the received data has any errors, these errors

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International Journal of Pure and Applied MathematicsVolume 118 No. 24 2018ISSN: 1314-3395 (on-line version)url: http://www.acadpubl.eu/hub/Special Issue http://www.acadpubl.eu/hub/

will identified based on parity bit. So by using parity checker onecan identify the errors in the data so it is easy to rectify errors whiledata transmission from one device to other device.

Quantum technology is one of the emerging technology whichmaking lot of changes in high speed computing. Quantum tech-nology is one of the emerging technologies in the field of Nanotechnology. It deals with the quantum dots which are representedin the form of Square Shape which is called as Qubit.

2 QUANTUM DOT COMPUTING AU-

TOMATA(QCA) BACKGROUND

Qubit consist of 4 quantum dots in which QCA cell is chargedwith two excess electrons which is allowed to tunnel between thequantum dots by a mechanism called clocking. Cross corners of thetwo dots are charged by the polarization. Below figure shows theQCA cell with Polarization 1 and Polarization 0. Polarization 1represents the logic 1 and Polarization 0 represents the Logic 0.

Fig 1: Basic Qubit cells

3 QCA WIRE REPRESENTATION

A horizontal connection of QCA cells are makes the wire and be-cause of the electrostatic interactions between the cells a binaryvalues propagates from input to output.

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International Journal of Pure and Applied Mathematics Special Issue

Fig 2: QCA wire logic

QCA wires are classified into two types depends on the quantumdot rotation. The wire which shown in figa is connected in 900 andconnection in the fig b represents the 450 wire.

Sasamal [1] proposed a five input majority voter XOR Gate withcoplanar QCA technology. This design mainly consists of five in-puts and rotated three input majority gate, Number of clock cycles0.75. In this proposal total 1126 cells are used to design a 32-bitparity generator.Santanusantra [2] Proposed a XOR gate in twodifferent approaches of XOR gate, One of the XOR gate takes 51number of cells with 5clock cycles. In this design with the inputsare used outside of XOR structure. The area taken for this circuitis 16524nm. In second method, they proposed XOR structure with30 numbers of cells and it consists of four clock cycles only and areais 9720nm2.

Ilanchezhian[3] proposed a241 cells 3 bit parity generator witharea is 215.552um2. The XOR gate which is used in the parity gen-erator consists of 64 cells with area of 52.511m2. They also proposeda parity checker with 197 cells and area is 293.6m2.Kakalidutta[4]proposed a XOR gate based on two dot one electron QCA method.In this, two quantum dots are used in which one electron is freeto move between the cell dots. They designed the parity generatorand checker based on this proposed XOR gate. This is mainlyrepresents reversible logic.TrilokyanathSasamal[5] Proposed a 32bit parity generator circuit using three input majority voter gateXOR logic. Which taken 40% less cells compared to previous log-ics.Ali NewazBhava[6] proposed three input majority voter XORgate. XOR gate consists of only 10cells and 4 parity generator tak-ing only 24 cells and 8bit parity generator designed by using only 51cells.In this work, we designed a 3bit, 4 bit and 8 bit parity checkercircuit based on Newazbahar XOR design.

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Fig 3: 2 input XOR gate

Fig 4:3 input XOR gate

Fig 5:3 input XNOR gate

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Fig 6: 3 input XNOR gate

4 MAJORITY GATES

There are so many types of Majority gates are available in QCA.Example 3 input majority gate which consist of MV(A,B,C) whereMV indicates Majority Voter gate.MV(A,B,C) = AB+BC+CA;MV(A,B,0) =AB;MV(A,B,1)=A+B;

5 PARITY GENERATOR CIRCUIT

Depends on number of ones in data parity bit is generated. Inputfor the parity generator is n-1 bit stream data and it generatesadditional bit which should transmit with bit stream i.e. paritybit. Parity generator is two types. 1. Even parity generator 2.Odd parity generator.

6 EVEN PARITY GENERATOR

In bit stream number of 1s are checked, if the number of 1s are eventhen 0 is added as a parity bit if the number of 1s are odd then1 is added as a parity bit Example consider the 3bit even paritygenerators

Table 1: 3 bit parity generator

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Fig 7: conventional 3 bit parity generator circuit

Fig8 : parity generator circuit using 3 input XOR

If we rearrange the circuit with 3 inputs XOR gate, this numberof XOR gates are reduced to 1.

QCA 3 bit parity generator3 bit even parity generator circuit designed based on 5 input

majority voter gate logic. For odd parity generator 3 input XNORgate is used, parity generator taken 10 cells with 2 clocks.

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Fig 9: QCA 3 bit even parity generator

Fig10: QCA 4 bit even parity generator

7 PARITY CHECKER CIRCUIT

In communication system when the data is transferred from onesystem to other system there is chance of getting errors, so to avoidthis problem a Parity bit will be sendto the other system with data,if there is any loss of data that will be detected using this parity bitwhich represents even or odd number of 1s in the transferred data.Parity checker is the process of determining whether the receiveddata has any errors or not based on the parity bit which is generatedby parity generator. In this we may have odd parity or even paritybased on number of 1s in data. For example consider the 8-bit data11001100 will have even parity because number of 1s are 4 that iseven.This circuit consists of only 10 cells to implement 3-bit paritygenerator. 3-bit parity checker:

Table2: 3 bit parity checker

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The output of the parity checker mainly depends on number of1s, if number of 1s are even output is 1 otherwise output zero.

After rearranging above circuit

Fig 11: Even Parity checker

By using Newazbahar 3 inputs XOR gate numbers of cells re-quired to design the above circuit in QCA layout is 20.

ODD PARITY CHECKER: In odd parity checker, odd par-ity bit is X-NORed with remaining input bits A, B, C

Fig. 12.

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Fig 13: 3 bit odd parity checker

Fig 14: 4 bit odd parity checker

As per the logic of parity checker for 4-bit data 3 XOR gatesare required. In below figure parity checker is designed by using 2input QCA XOR gates with less number of cell count and area alsosmall compared to the previous structures.

8 RESULTS

Fig15 :3 bit even parity generator

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Fig16:4 bit odd parity generator

Fig 17: 3 bit even parity checker

Fig18 : 4 bit odd parity checker

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9 CONCLUSION

Three input and Four input even and odd parity generators andparity checkers are designed based QCA logic and no of cells andarea also compared. Compared to previous designs less no of cellsand area obtained.

References

[1] Cho, H. and Swartzlander, E. E., Adder and multiplier de-sign in quantum-dot cellular automata, IEEE Transactions onComputers, 58(6), 2009, 721-727.

[2] Lent C.S., Tougaw P.D., Porod W.D., and Bernstein., G.H.Quantum cellular automata, Nanotechnology, 4(1), 1993, 4957.P. S. Huang, C. S. Chiang, C. P. Chang, and T. M. Tu, ”Robustspatial watermarking technique for colour images via directsaturation adjustment,” Vision, Image and Signal Processing,IEE Proceedings -, vol. 152, pp. 561-574, 2005.

[3] Seminario J.M, Derosa P.A, Cordova L.E and Bozard B.H.,A molecular device operating at terahertz frequencies, IEEETransactions on Nanotechnology, 3(1), 2004, 215218.

[4] Zhang, R., Walus, K., Wang, W., and Jullien, G. A., A methodof majority logic reduction for quantum cellular automata,IEEE Transactions on Nanotechnology, 3(4), 2008, 443-450.

[5] Hnninen, I. and Takala, J., Binary adders on quantum-dotcellular automata. Journal of Signal Processing Systems, 58(1),2010, 87-103.

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[6] Automata (QCA) shift register and analysis of errors, IEEETransactions on Electron Devices, 50(9), 2003, 1906-1913. .

[7] Tougaw, P. D., Lent, C. S., and Porod, W., Bistable satura-tion in coupled quantum-dot cells, Journal of Applied Physics,74(5), 1993, 3558-3566.

[8] Lent, C. S., Tougaw, P. D., and Porod, W., Bistable satura-tion in coupled quantum dots for quantum cellular automata,Applied Physics Letters, 62(7), 1993, 714-716.

[9] Azghadi MR, Kavehei O, Navi K., A novel design for quantum-dot cellular automata cells and full adders. J ApplSci 7(22),2007, 34603468.

[10] Cho H and Swartzlander EE., Adder designs and analyses forquantum-dot cellular automata. Nanotechnol IEEE Trans 6(3),2007, 374383.

[11] Gin A, Williams S, Meng H, Tougaw PD., Hierarchical designof quantum-dot cellular automata devices. J ApplPhys 85(7),1999, 37133720.

[12] Ke-ming Q and Yin-shui X., Quantum-dots cellular automatacomparator. In: 7thInternational Conference on ASIC. IEEE,Guilin, 22-25, Oct.2007.

[13] Kim K, Wu K, Karri R., The robust qca adder designs usingcomposableqca building blocks. IEEE Trans Comput AidedDes Integrated CircSyst 26(1), 2007, 176183.

[14] Mardiris VA and Karafyllidis IG., Design and simulation ofmodular 2n to 1 quantum-dot cellular automata (QCA) mul-tiplexers. Int J CircTheorAppl 38, 2010, 771785.

[15] Navi K, Farazkish R, Sayedsalehi S, Azghadi MR., A newquantum-dot cellular automata full-adder. Microelectron J41(12), 2010, 820826.

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