DESIGN OF ON CHIP TEMPERATURE MONITORING IN 90NM CMOS

A thesis submitted to the faculty of

San Francisco State University

In partial fulfillment of

The Requirements for

The Degree

Master of Science

In

Engineering: Concentration In Embedded Electrical and Computer Systems

by

Mojan Norouzi

San Francisco, CA

August 2010

Copyright by

Mojan Norouzi

2010

CERTIFICATION OF APPROVAL

I certify that I have read Design of on chip Temperature Monitoring in 90nm CMOS by

Mojan Norouzi, and that in my opinion this work meets the criteria for approving a thesis

submitted in partial fulfillment of the requirements for the degree: Master of Science in

Engineering: Concentration in Embedded Electrical and Computer Systems at San

Francisco State University.

___________________________________________________ Hamid Mahmoodi

Assistant Professor, Electrical and Computer Engineering

___________________________________________________ Hamid Shahnasser

Professor, Electrical and Computer Engineering

DESIGN OF ON CHIP TEMPERATURE MONITORING IN 90NM CMOS

Mojan Norouzi

San Francisco, California

2010

Modern VLSI designs experience significant temperature change due to variations in

workload and ambient conditions. The change in temperature can cause variation in other

performance parameters such as power and reliability. Modern chips use complex self-

calibration techniques to adjust design parameters to safeguard the chip’s operation

against temperature fluctuations. Any on-chip self-calibration system needs a temperature

monitoring to observe the temperature of the chip at the spot of interest. This thesis

describes a novel integrated design of on chip temperature monitoring sensor in 90nm

CMOS technology for a wide range of temperature variation.

I certify that the Abstract is a correct representation of the content of this thesis

_________________________________________________ ____________

Chair, Thesis Committee Date

ACKNOWLEDGMENTS

The following thesis, while an individual work, benefited from the insights and direction

of several people. First, my Thesis Chair, Dr. Hamid Mahmoodi provided timely and

instructive comments and evaluation at every stage of the thesis process, allowing me to

complete this project on schedule. Next, I wish to thank the thesis committee: Dr. Hamid

mahmoodi and Dr. Hamid Shahnasser. Each individual provided insights that guided and

challenged my thinking, substantially improving the finished product.

In addition to the technical and instrumental assistance above, I received equally

important assistance from family. My parents provided on-going support throughout the

thesis process, as well as technical assistance critical for completing the project in a

timely manner. My mother instilled in me, from an early age, the desire and skills to

obtain the Master’s.

v

TABLE OF CONTENTS

List of Figures ………………………………………………………….…….vii

Introduction…………………………………………………………………….1

Design and Specifications………………………………………………...…....4

Integrated Temperature Sensor………………………………………………...6

Design of Analog Operational Amplifier…....…………………………………9

Implementation of the Resistors and Capacitor………………………………15

Design of Analog Comparator…………………………………………..……18

Voltage Reference…………………………………………………………….20

Results and Discussions………….…………………………………………...22

Conclusions…………………………………………………………………...24

References…………………………………………………………………….25

vi

LIST OF FIGURES

Fig.1: Increase in leakage with technology scaling…………….………………………...1

Fig.2: Sleep transistor implementations…………………………………………………..2

Fig.3: System Block Diagram……………………………………………………………..5

Fig.4: Integrated Temperature Sensor.........................................................................…...6

Fig.5: Layout of Integrated Temperature Sensor…………………………………………7

Fig.6: Biasing Circuit for op-amp Width are shown ...………………………………..…11

Fig.7: Two stage op-amp………………………………………………………...………11

Fig.8: Temperature sensor connected to the differential amplifier ………………….....13

Fig.9: Output of Temp sensor and differential amplifier …………………………..……14

Fig. 10: Layout view of Capacitor……………………………………………………….17

Fig.11: Comparator…………………………………………………………....…………19

Fig.12: Voltage Reference……………………………………………………………….20

Fig.13: Output of Voltage Reference……………………………………...……………..21

Fig.14: Schematic of complete system…..………………………………………………22

Fig.15: Output of comparators…………………………………..……………………….23

vii

1

INTRODUCTION

Leakage current has been increasing exponentially with scaling down of the transistor as

shown in Fig.1. In 90nm node leakage current can reach as high as 35% of chip current.

Moreover reduction in power consumption becomes critical in low-power applications

such as mobile devices. Power-gating is the most recent and effective technique

developed to reduce leakage power [1].

Fig.1: Increase in leakage with technology scaling

In this technique array of sleep transistors are used as switches to shut on/off the power

supply to part of the system. As shown in Fig.2, an array of PMOS is used to connect and

disconnect supply voltage from the rest of the circuit. The gates of each PMOS are

connected to a source of proper voltage, which allows the entire array to turn on.

However, one notable disadvantage of this configuration is that the entire array of sleep

transistors are turned ON/OFF together using a single control signal, irrespective of the

operating temperature of the chip. Without temperature sensitivity the sleep transistor

array experiences increasing ON/OFF switching, which is known to accelerate the aging

2

effect [2]. These disadvantages result in accelerating aging sleep transistors over time.

Thus, there is an observed practical need for a system that can monitor the temperature

and control the power gating. At low temperatures, where the circuit operates faster,

portions of the sleep transistor array can be switched off to stop their aging. This requires

design sensor.

Fig.2: Sleep transistor implementations

The objective of this paper is to design a temperature monitoring system that can identify

if the temperature is in any of the pre-defined low, medium and high regions. To realize

such a design, four components are needed: Temperature sensor, Voltage reference,

analog Op-amp and analog Comparator. The intended application of this temperature

monitoring design is for self calibration of the sleep transistors against temperature. The

design shall be implemented and verified in the Synopsys 90nm CMOS technology.

The design that has resulted from the analyses discussed in subsequent sections of this

thieses, carries the following distinguishing features:

3

Fewer transistors and resistors for integrated temperature sensor than the design

reported in [5-6]. The temperature sensor proposed herein carries no resistors and

consumes less area.

CMOS is used instead of BICMOS [6], which allows for easier and less expensive

fabrication.

In [5-8], there is no completed temperature monitoring system, providing ability

to control other circuit such as array of sleep transistors.

4

DESIGN SPECIFICATIONS

The sensor in this work is a MOSFET temperature sensor (see Fig.3). The threshold

voltage for MOSFETs in this sensor is 200 mV at 25°C ambient temperature. The sensor

output voltage changes at the rate of 4.1 mV/°C, and the application requires the sensor to

measure temperatures ranging from 20°C to 100°C. Based on the application, the sensor

must recognize three ranges of temperatures: low (less than 60°C), medium (between

60°C to 70°C) and high (greater than 90°C). In addition, these temperature set-points

must be adjustable according to the requirements. In this system, the circuit uses a single

1.2V power supply. The limitation of this design is that it must use a 90nm transistor.

Also is desire to have small size of resistors and capacitors as much as possible.

A high-level block diagram of the design is shown in Fig.3. The design is composed of

three main modules, namely a temperature sensor, an op-amp and a comparator.

Basically the temperature sensor will sense the temperature of wanted area. Since the

output of temperature sensor is not large enough an op-amp is needed to boost the signal.

The output of the op-amp is an analog signal (something between 0 to 1.2V). A

comparator is needed to convert the analog output of the op-amp to logic zero or one in

order to control the sleep transistors.

5

Fig.3: System Block Diagram

Temperature

Sensor

Op-amp

Comparator

Referenc

e

6

INTEGRATED TEMPERATURE SENSOR

The schematic and layout of the temperature sensor is shown in Fig.3 and 5, respectively.

All transistors are biased to operate in the saturation region. Transistors & are

forming a current mirror and transistors and provide proper bias for the current

mirror. & are diode-connected and make a current source for the current mirror,

which generate voltages and [1].

Fig.4: Integrated Temperature Sensor

(The numbers represent width and L=0.1um for all transistors)

From basic electronics, in saturation mode the current of an NMOS transistor is given as

follows (α ≈ 2):

7

(2.1)

Where µ is the electron mobility, is the oxide capacitance, W is the width of

transistor, is the threshold voltage and L is the channel length (in this research L =

0.1u). There are two parameters in Eq.2.1, which are temperature dependent: μ and .

In general as temperature increases, both the threshold and the mobility decrease.

Reduction in mobility reduces drain current, but, reduction in causes to increase the

drain current. However, because decrease with temperature and its effect is a dominant

one, the overall effect of temperature increase is a decrease in drain current. In some

technologies because of small supply voltage, the current will be more sensitive to ,

resulting in current increase with temperature increase.

Fig.5: Layout of Integrated Temperature Sensor

8

Using Eq 2.1 for & , and can be expressed as follows:

= + (2.2)

= + (2.2)

Since in both & threshold voltage and mobility will decrease as temperature

increases, choosing significantly larger than can noticeably increase the

differences between and . In order to amplify the difference between and , a

differential op-amp is needed, which is described next.

9

DESIGN OF ANALOG OPERATIONAL AMPLIFIER

The second component in this system is an operational amplifier. The op-amp has two

main parts which are biasing circuit and two stages op-amp. Fig.6 shows a biasing circuit

for a general analog design, which uses the Beta-multiplier and critical capacitance MCP

for stability. PMOS is chosen for increasing the capacitance and further stabilize the

circuit [3].

The next circuit is op-amp with output buffer. A two-stage op-amp is shown in Fig.7. The

first stage, there is a cascaded differential amplifier. The gain of the first stage is:

(3.1)

(3.2)

The resistance looking into the drain of MC2, assuming M2 and MC2 are the same size,

is given by

= . (3.3)

And again the resistance looking into the drain of MC4, assuming MC4 and M4 are the

same size is given by:

= . (3.4)

So the gain of first stage is:

10

= ( . // . ) (3.5)

Where , and represent the transconductance (the constant relating and

) of transistor MC2 and MC4 and is the resistance looking at the drain of transistor

The gain of second stage of op-amp depends on the load. If no load is connected to the

output, then the gain is:

(3.6)

Where and represent the transconductance of transistor MC2 and MC4 and

is the resistance looking at the drain of transistor MP and MN.

11

Fig.6: Biasing Circuit for op-amp

Fig.7: Two stage op-amp Width is labeled for MOSFETs

and L=0.1um for all

transistors

Width is labeled for MOSFETs

and L=0.1um for all

transistors

12

The designed op-amp can be used in a differential amplifier configuration. The use of

differential op-amp has two advantages: Firstly, it increases the sensitivity of the

temperature sensor’s output. Secondly, the differential op-amp cancels common mode

noise on and also improving the reliability of the sensor. A schematic showing the

connection of the differential amplifier to the temperature sensor is shown in Fig.8 [4].

Fig.8 shows the simulated output of the temperature sensor and differential amplifier as

temperature is swept from to . The gain of differential amplifier (Fig.7) can

be expressed as follows:

( - )( ) (3.7)

Using the simulated result from Fig. 9 the above equation can be validated as follows:

= (0.71-0.48)*( ) = 1.01V

A gain larger than that shown above cannot be chosen because in this technology the

power supply cannot go higher than 1.2V. Any larger gain would cause saturation of the

circuit.

13

Fig.8: Temperature sensor connected to the differential amplifier

14

Fig.9: Output of Temperature sensor and differential amplifier

15

IMPLEMENTATION OF THE RESISTORS AND CAPACITOR

Since in the above design (op-amp), the use of resistors is required this section focuses on

the implementation of these resistors in CMOS. As a first step, the relevant properties of

resistive materials in a 90 nm CMOS process shall be evaluated. There are three options

for the selection of resistors: (1) N-well which provides 500 ohms/sq and 2400 ppm/C

(parts per million per degree C) (2) poly which gives 200 ohms/sq and 20ppm/C (3)

poly 400 ohms/sq and 160 ppm/C [1]. A notable advantage of the n-well resistor is its

established savings in area. However its inherent sensitivity to changing temperature is

as high as 2400 ppm/C. For this system, the high temperature sensitivity is undesirable.

The best case is using poly which is the most stable resistor under temperature

variations, and thus, the most suitable for this design configuration.

To demonstrate the low sensitivity of poly to changing temperatures, the changes in

resistivity of a 1kΩ resistor (at room temperature =27C) shall be calculated. Using

following relation:

R(T) = R( ) * [1+ TCR* (T- ) ] (4.1)

Where is room temperature and TCR is temperature coefficient.

For the resistance of = 1K at room temperature

16

= 1kΩ (1+ 2* *(100-27) = 1.00141kΩ

As shown above, the change in resistivity between room temperature and 100C is

insignificant relative to this configuration (0.14%).

For example for calculating the resistance of n-well that is W= 10 and L = 100 and n-well

sheet resistance is about 2KΩ/square. Using the following formula:

R = . L/W (4.2)

Where is sheet resistance, W is width and L is length.

So the typical resistance between the ends of n-well is

R = 2000 (100/10) = 20 kΩ

I here I would like to discuss the layout of the capacitor using n-well covered by n-imp

and poly. Layout view of the capacitor is shown in Fig. 10. The capacitor can be

calculated as follow:

. A (4.3)

Where = 8.85* F/um and represents dielectric constant ( = 3.9) and A is

area.

17

Fig.10: Layout view of Capacitor

n-imp

n-well

Poly

Contact

18

DESIGN OF ANALOG COMPARATOR

In order to recognize three temperature regions (low, medium, high), two comparators are

needed. The comparator consists of three stages (as shown in Fig. 11): (1) Preamplifier

stage, which amplifies the input signal to increase the sensitivity. This circuit is a

differential amplifier with the input of Vm and Vp (2) Positive feedback stage which

determine which signal is larger is basically is a heart of the comparator, and should be

capable of discriminating mV-level signal (3) the final component in this comparator is

output buffer which convert the signal to logic one or zero [3].

19

Fig.11: Comparator

Width is labeled for MOSFETs and L=0.1um for all transistors

transistors

Biasing Generator

Pre-amplifier

Decision

Output buffer

20

VOLTAGE REFERENCE

A voltage reference is needed as an input to the comparators. It is critical to have a

reference voltage, insensitive to temperature variation, to be used as a reference input to

comparators.

Presented below (reference Fig. 12) is a voltage reference using a MOSFET-only voltage

divider. Since = , we can write

( = ( (6.1)

Hence the reference voltage is given by

= (6.2)

Now by changing W, can be adjusted [3].

Fig.12: Voltage Reference

21

= 5.5um and = 0.23um yields 0.74V at the output. Fig.13 shows the stability of

voltage reference verses temperature. For C change in temperature, there is only

6.8mv change at the output. Therefore the output voltage is very stable in wide range of

temperature variations.

Fig.13: Output of Voltage Reference

22

RESULTS AND DISCUTIONS

After designing all subsystems, it is necessary to observe the desired output from the

entire system. Fig.14 shows the schematic of the complete designed temperature sensor.

The first comparator compares the output of the op-amp with the reference voltage. In

order to produce a reference voltage for the second comparator a voltage divider ( and

) is used for produce a smaller reference voltage.

Fig.14 Schematic of complete system

The simulated response of the complete design is shown in Fig.15. After biasing the

circuit, the output of comparators at low temperature (below C) is at logic zero

(low region). For temperatures ≥ C (medium region), the output of comparator

one is at logic one however the output of comparator two remains zero. For above

C (high region), the output of the second comparator is at logic high.

23

Fig.15: Output of comparators

24

CONCLUSION

Having a control over temperature is an increasingly important problem in scaled

technologies. In this thesis, a novel integrated system has been proposed for recognizing

three ranges of temperature. The proposed system employs integrated temperature sensor

followed by an op-amp in differential mode of operation with two comparators and the

voltage reference. This system provides a control of temperature on a chip for a wide

range in temperature. The advantages of the proposed system is its all CMOS

implementation for system-on-chip design

25

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