Design of a Power-Efficient Interleaved CIC Architecture for Software Defined Radio Receivers By...
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Transcript of Design of a Power-Efficient Interleaved CIC Architecture for Software Defined Radio Receivers By...
Design of a Power-Efficient Interleaved CIC Architecture for
Software Defined Radio Receivers
ByJ.Luis Tecpanecatl-Xihuitl, Ruth Aguilar-Ponce,
Ashok Kumar, Magdy A. Bayoumi
Center for Advanced Computer Studies (CACS)University of Louisiana at Lafayette
Lafayette, LA, USA
2
Outline
• Introduction
• Goal
• Cascaded-Integrator-Comb (CIC) Filter
• Proposed Architecture
• Results
• Conclusions
3
Introduction
• Two important current factors targeting Circuits for Communications:
– High Data Rates
– Multistandard Devices
* Topics in Circuits for Communications IEEE Communications Magazine, August 2005
4
Introduction
– High Data Rates
• Much information in is being to transferred between many of these devices
• PVR to flat- screen may require 221-1327 Mb/s.
• Downloading 1000 songs from a media center or Pc to MP3 player require 200 Mb/s in a reasonable amount of time.
* Topics in Circuits for Communications IEEE Communications Magazine, August 2005
5
– Multistandard Devices
• Portable devices integrating not only camera and cellphone, but also WLAN.
• Personal Video Recorder (PVR), Gaming and Digital TV.
• At the same time dissipating low power for long battery lifetime.
6
Introduction
• Use of Multi-Standard Digital Receiver
• Transition between generations
– 2G 3G 4G
• 4G “ABC” Always Be Connected
– Data Networks, PCS, Bluetooth, and more
7
Introduction
Old Standar
ds
Data Nets
Next Generatio
n
PCS Nets
3G
2G
4G
SpecificStandard
8
Introduction
• Several Communication Standards
• Incompatibility between them– For Example GSM in USA vs. Europe
• Many devices per user
• High Cost of new infrastructure
9
Introduction
• Benefits of Multi-Standard Device
– Several Standards– Take advantage of current infrastructure– Take advantage of different service
providers– Configurable by a PC, same provider or by
itself
10
Introduction
• How can this be possible?– Software-defined Radio
• Implement the different functionalities of a transceiver by means of software
• Flexibility
Analog Digital
Anti-aliasingFilter ADCLNA DSP
11
Introduction
• Architecture– Going so close to the antenna
Analog
Digital
Anti-aliasingFilter
ADCLNAH(z) R
H(z) R
Multistage Decimation Filters
I
Q
NCO
NCO
12
Introduction
• Digital Down Converter– Analog-to-Digital Converter (ADC)– Numerical Control Oscillator (NCO)– Mixers (Multipliers)– Decimator Filter
• Frequency translation• Computational intensive• Power demanding
13
Introduction
• Accelerator– Dedicated pieces of hardware which are
not programmable– Low power consumption– Reduced Area– Flexibility
ADC DACDSP
accelerators
14
Introduction
– Decimator• Digital Filter• Downsampler
H(z) MFin Fout = Fin/M
2
X(ej)
0
2
H(ej)
/M
1
0
W(ej)
/M0
Y(ej’)
/M0 2/M 4/M 6/M 8/M
’0 2 4 6 8
If M >> 2 then Coefficient length of H(z)
Increase
CIC good candidate
15
Introduction
• Distribution of power consumption on a Tap (multiplication, addition)
– Multiplication: 40% to 76% of total power consumption on each tap
– Additions: 14% to 25% of total power consumption on each tap
14%
10%
76%
Multiplications
Additions
other
Tap Filter Multiplication, Addition and Delay
16
• Major sources of power dissipation in digital CMOS circuits
– Switching– Short-circuit– Leakage currents
Ptotal = pt(CL V Vdd fclk ) + Isc Vdd + Ileakage Vdd
17
Introduction
• Process Design
– Identification of the blocks
or parts consuming an
important fraction of the
power during optimization
process.
2.-Algorithm
3.-Architecture
4.-Logic/Circuit
5.-Device/Process
1.-System
18
Goal
1. Power Reduction on CIC Filter– Reduced frequency of operation– Voltage Scaling
2. One structure to filter both Signals– Interleaving
3. Common Structure for different communication standards
19
CIC Filter
• Cascaded Integrator-Comb Filter
• Advantages – Multiplierless
implementation– No memory storage
Integrator M Comb
fs fs /M
M
z-1 z-1 z-1z-1
k stages k stages
kDD
n
n
z
zzzH
1
1
0 1
1
Wide wordlength
39 bits 19 bits
20
CIC Filter
• Two CIC filters– Double area– Power consumption– Integrator Section
• Frequency input• Wide Wordlength
Q
CIC
CIC
MultistageFilters
ADC
Q
I
I
Integrator M Comb
fs fs /M
21
Proposed Architecture
• Polyphase filter operates at frequency f/R1, where f is the input frequency.
• The polyphase filter structure for decimation filtering helps to reduce the speed requirement grouping the filter in subfilters. The serial input is passed to be filter by the subfilters. The outputs are added to obtain the final output. Thus, the subfilters will operate at reduced frequency fs/D, where D is the factor of decimation
22
Proposed Architecture
• The dynamic power dissipation in digital CMOS circuits can be modeled as
• The polyphase architecture is composed of polyphase components operating at the rate of f/M. Therefore, in these polyphase components, it is possible to reduce the voltage supply, which has an important impact on the power consumption. V’dd can be approximated by
fVCP ddeffdynamic2
22'
'
tdd
dd
tdd
dd
VV
VM
VV
V
23
Proposed Architecture
• Voltage Scaling– The obtained scaled voltage supply causes no degradation
in the performance of the whole structure. For the stages after the polyphase CIC filter the same voltage supply scaled is used without no decrement effect on performance
because the sampling rate is reduce each time. Standard Decomposition V’dd # Adders
Mobitex 5 107 1.48 V 7
Ardis 5 107 1.48 V 7
GSM 8 8 1.27 V 18
IS-95 5 1.48 V 7
UMTS 5 1.48 V 7
24
Results
• Wordlengths on CIC filter
Standard Sample RatesFirst decimation
factorWordlength
CIC – 3 stages [1]
Mobitex85.6 MHz 20 KHz 535
36 bits – 27bits – 19bits16bits - 15bits – 14 bits
Ardis85.6 MHz 48 KHz 535
36 bits – 27bits – 19bits16bits - 15bits – 14 bits
GSM80 MHz 541.6 KHz 64
28 bits – 23bits – 18bits16bits – 15bits – 14bits
IS-9580 MHz 2.4576 MHz 5 17bits – 17bits – 16bits
16bits – 15bits – 14bits
UMTS80 MHz 7.68 MHz 5 17bits – 17bits – 16bits
16bits – 15bits – 14bits
25
Results
• Power estimation– Three different factors– For our estimation, adders are the major power
consumer blocks for the direct CIC filter in the new architecture due to their dominant capacitance
0
22
144.0535
2107
3.3
48.1
6
3
5
2
3.3
48.1
6
10Pf
v
vCf
v
vC effeff
0
22
166.08
4
3.3
27.1
6
3
8
2
3.3
27.1
6
21Pf
v
vCf
v
vC effeff
0
2
134.05
2
3.3
48.1
6
10Pf
v
vCeff
26
Results
• where P0 denoted the power consumption of the reference system. The previous estimations correspond to the three different decompositions showed in previous Table.
• Therefore, the power consumption of the Interleaved CIC polyphase architecture is only around 15% of the original system.
27
Results
• Frequency Response– Interleaved CIC polyphase structure is
simulated in MATLAB
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 104
-80
-60
-40
-20
0
Hz
dB
Frequency Response
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 106
-80
-60
-40
-20
0
Hz
dB
GSMIS-95UMTS
ArdisMobitex
28
Conclusions
• Combination of different methods has been adopted to reduce the power consumption on CIC filters used on multistandard digital receivers implemented as software defined radio.
• Interleaving both signals I and Q, in a polyphase architecture results in a more efficient structure which works at low frequency.
29
Conclusions
• On each polyphase component the voltage supply is scaled to reduce the power consumption without compromising the performance of the whole architecture.
• The power consumption in the proposed architecture is estimated to be approximately 15% of the common architecture on the three cases.
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