DESIGN OF A 9 GHz CMOS LOW NOISEAMPLIFIER USING GAIN-ENHANCEDTECHNIQUE

Sen WangDepartment of Electronic Engineering and Graduate Institute ofComputer and Communication Engineering, National TaipeiUniversity of Technology, No. 1, Sec. 3, Chung-Hsiao E. Rd.,Taipei, Taiwan; Corresponding author: wangsen@ntut.edu.tw

Received 24 May 2010

ABSTRACT: In this article, a 9 GHz low noise amplifier (LNA) usinggain-enhanced technique is presented. The compact and high-gain LNA

with cascode topology is implemented in a standard 0.18-lm CMOSprocess. The gain-enhanced technique consists of two inductors in the

common gate (CG) stage of the cascode configuration. The first inductorat the source terminal in the CG stage eliminates the parasitic effectscaused by the parasitic capacitances of transistors at high frequencies.

Moreover, the second inductor at the gate terminal in the CG stageachieves a negative resistance making a high gain characteristic of the

amplifier. Finally, the measured small signal gain, noise figure andinput P1dB at 9 GHz are 16.5 dB, 4.5 dB, and �15 dBm, respectively.The chip size of the compact LNA is 0.48 mm � 0.8 mm including all

testing pads. VC 2011 Wiley Periodicals, Inc. Microwave Opt Technol

Lett 53:479–481, 2011; View this article online at

wileyonlinelibrary.com. DOI 10.1002/mop.25778

Key words: low-noise amplifier (LNA); coscode; CMOS

1. INTRODUCTION

Rapid developments of advanced wireless communications

requiring larger data rates make radio-frequency (RF) front-end

circuits moves toward at higher frequencies. Low noise ampli-

fiers (LNAs) are used to amplify received signal with minimum

noise contribution in the receiver. Moreover, CMOS LNAs have

been extensively investigated for low cost and high yield inte-

gration. However, silicon-based technologies such as CMOS and

BiCMOS processes suffer higher parasitic capacitance and loss

inherently with increasing operating frequencies on the silicon

substrate compared with GaAs processes.

Previous works related to CMOS LNAs utilize cascode-based

topology for high gain or low noise consideration at multi-giga

hertz [1–5]. These LNAs with cascode [1, 2], folded-cascode

[3], or triple-cascode topology [5] achieve acceptable gain per-

formances with low power consumptions. Moreover, the LNA

using the parallel-resonant technique achieve a minimum noise

figure (NF) at X-band [4]. In this article, a cascode-based

CMOS LNA using two gain-enhanced inductors is presented

around 9 GHz. The compact LNA demonstrates the feasibility

of the gain-enhanced technique, and achieves higher gain per-

formances with lower power consumptions compared with the

previously reported CMOS LNAs.

2. CIRCUIT DESIGN AND FABRICATION

Cascode configuration amplifiers feature high gain and good

reverse isolation performances due to the combination of com-

mon source and common gate (CG) stages. [5, 6]. The proposed

cascode configuration with two inductors, or LG and LS at the

CG stage is shown in Figure 1. At high frequencies, the parasitic

capacitances CPD and CPS of cascode transistors M1 and M2 de-

grade the small-signal gain and NF of this configuration. There-

fore, the introduction of LS between M1 and M2 aims to elimi-

nate the parasitic effects. Moreover the input impedance, or ZINat the CG stage is given by

ZIN ¼ 1� x2LGCgs2

gm2 þ jxCgs2

¼ �Req þ jxLeq (1)

where gm2, Cgs2 are the transconductance and gate-source capac-

itance of M2, respectively. �Req, Leq, and x are the equivalent

resistance, inductance, and operating frequency. Note that circuit

could achieve a negative resistance due to the LG at the gate ter-

minal of M2 [7, 8]. The gain of the circuit can be enhanced by

choosing proper inductance LG and aspect ratio of M2 for Cgs2

while the circuit is still stable.

Figure 2 shows the complete schematic of the proposed

CMOS LNA. The output matching circuits are realized by T-

networks for the maximum small signal gain. Furthermore, the

input matching circuits are designed for minimum NF considera-

tions. The input impedance of the matching network, or Zport1can be expressed as

Zport1 ¼ jxL1þ 1

jxCgs1

þ Rg þ RL1 (2)

where Cgs1, Rg, and RL1 are the gate-source capacitance, effec-

tive gate resistance of M1, and the parasitic resistance of theFigure 1 The cascode configuration with LG and LS at the CG stage

Figure 2 Schematic of the proposed X-band LNA

DOI 10.1002/mop MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 53, No. 3, March 2011 479

Figure 3 Chip photography of the CMOS LNA with a chip size of 0.48 mm � 0.8 mm

Figure 4 (a) Simulated and measured results of S21 and S12. (b) Simulated and measured results of S11 and S22

Figure 5 (a) Simulated and measured results of input P1dB. (b) Simulated and measured results of NF

480 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 53, No. 3, March 2011 DOI 10.1002/mop

inductors L1, respectively. Therefore, the Zport1 can be matched

to a 50 X easily by choosing L1 and the size of M1. The aspect

ratio of M1 and M2 are (72 lm/0.18 lm) and (128 lm/0.18

lm), respectively. The inductances of L2 and L3 are 0.57 nH

and 0.45 nH, respectively. Moreover, each gate is biased

through a 5-kX resistor, and bypass capacitors are added to sta-

bilize the supply voltage and to isolate the supply noise.

The compact X-band LNA was fabricated in a standard

mixed-signal/RF bulk 0.18-lm CMOS process, which provides

single poly layer and six metal layers (from M1 to M6 layers)

for interconnection. All the capacitors are realized by metal-

oxide-metal capacitors implemented from M1 to M6 for high

capacitance density, or 1.35-fF/lm2. Inductors in Figure 2 are

all implemented on the top metal layer (M6), or the 2.3-lm-

thick AlCu metallization layer for high quality factor. Figure 3

presents the chip photography of the CMOS LNA with a chip

size of 0.48 mm � 0.8 mm including all testing pads. More-

over, Figure 3 locates each component and device of the LNA.

A meshed ground plane implemented by M1 layer is distrib-

uted over the LNA as shown in Figure 3. Consequently, elec-

tromagnetic couplings are minimized making the overall chip

compact.

3. EXPERIMENTAL RESULTS

Measurement of the X-band LNA were performed via on-wafer

probing. The biasing conditions VG1, VG2, and VDD of the LNA

are 0.8 V, 1.8 V, and 3V, respectively. Therefore, the total current

consumption for the LNA is 5 mA. Figure 4(a) shows the meas-

ured results of small-signal gain (S21) and reverse isolation (S12)

of the LNA. The measured small signal gain and reverse isolation

is about 16.5 dB and �22 dB at 9 GHz, respectively. Moreover,

the measured input return loss (S11) and output return loss (S22) is

about 12 dB and 7 dB, respectively, as shown in Figure 4(b). The

measured input 1-dB compression point (P1dB) and NF is �15

dBm and 4.5 dB at 9 GHz, respectively, as shown in Figure 5.

Reasonable agreements between simulated and measured results

are obtained in Figures 4 and 5. Finally, Table 1 summarizes the

previously reported CMOS LNAs. It reveals that this work dem-

onstrates highest small signal gain with low power consumption

and a compact chip size around 9 GHz.

4. CONCLUSION

This work is to explore the potential of a LNA design using the

gain-enhanced technique. Moreover, a 9 GHz LNA is success-

fully designed, implemented, and verified in a standard 0.18-lmCMOS process. The two inductors at the CG stage of the LNA

aim to eliminate the parasitic effects and to achieve a negative

resistance making a high gain characteristic at high frequencies.

The good agreements between simulated and measured results

prove the design methodology of the LNA. The compact CMOS

LNA achieves a small signal gain of 16.5 dB and an acceptable

NF of 4.5 dB with an only power consumption of 15 mW. The

design is believed to be a significantly low power and high gain

and is suitable for microwave and millimetre-wave front-ends

applications.

ACKNOWLEDGMENTS

The authors thank the National Science Council (NSC) and Chip

Implementation Chip (CIC) of Taiwan for financial and technical

supports. This work was supported by the NSC under Contract

NSC-99-2218-E-027-004.

REFERENCES

1. R. Fujimoto, K. Kojima, and S. Otaka, A 7-GHz 1.8-dB NF

CMOS low-noise amplifier, IEEE J Solid-State Circuits 37 (2002),

852–856.

2. J. Gil, K. Han, and H. Shin, 13 GHz 4.67 dB NF CMOS low-noise

amplifier, Electron Lett 39 (2003), 1056–1058.

3. T.K.K. Tsang and M.N. El-Gamal, Gain controllable a very low

voltage (<1 V) 8–9 GHz integrated CMOS LNAs, IEEE RFIC

Symposium, Seattle, WA, 2002, pp. 205–208.

4. K.-J. Sun, Z.-M. Tsai, K.-Y. Lin, and H. Wang, A 10.8-GHz

CMOS low-noise amplifier using parallel-resonant inductor, Inter-

national Microwave Symposium, Honolulu, Hawaii, 2007, pp.

1795–1798.

5. B.-J. Huang, H. Wang, and K.-Y. Lin, A miniature Q-band CMOS

LNA with triple-cascode topology, International Microwave Sym-

posium, Boston, MA, 2009, pp. 677–680.

6. X. Fan, H. Zhang, and E.S. Sinencio, A noise reduction and linear-

ity improvement technique for a differential cascade LNA, IEEE J

Solid-State Circuits 43 (2006), 588–598.

7. C.R. Poole, The effect of device configuration on GaAs MESFET

negative resistance behavior, International Circuit and System Con-

ference, Shenzhen, China, 1991, pp. 427–430.

8. U. Karacaogle and I.D. Robertson, MMIC active bandpass filters

using varactor- tuned negative resistance elements, IEEE Trans

Microwave Theory Tech 43 (1995), 2926–2932.

VC 2011 Wiley Periodicals, Inc.

HIGH-IMPEDANCE SURFACE-BASEDSQUARE LOOP ANTENNA WITHRF-ABSORBER

Prafulla Deo,1 Amit Mehta,1 Dariush Mirshekar-Syahkal,2

Peter J. Massey,1 and Hisamatsu Nakano3

1Multidisciplinary Nanotechnology Centre (MNC), School ofEngineering, Swansea University, Swansea, Wales SA2 8PP,United Kingdom; Corresponding author: a.mehta@swan.ac.uk2 School of Computer Science and Electronic Engineering,University of Essex, Essex, Colchester CO4 3SQ, United Kingdom3College of Engineering, Hosei University, Koganei, Tokyo 184-8584, Japan

Received 25 May 2010

ABSTRACT: A beam steerable square loop antenna is presented over

a high impedance surface with RF-absorber. For a test frequency of 5.0GHz, the proposed antenna is 4.69-mm thick and has an impedance

TABLE 1 Comparisons of Previously Reported CMOS LNA

Ref. Process Architecture Frequency (GHz) Gain (dB) NF(dB) P1dB (dBm) PDC (mW) Chip Size (mm2)

[1] 0.2 lm CMOS Cascode 7 6.2 3.3 NA 13.8 0.86�0.61

[2] 0.18 lm CMOS Cascode 13 4.9 4.67 NA 9.7 0.31�0.33

[3] 0.18 lm CMOS Folded cascode 8 13.7 3.2 �13.2 22.4 1�0.9

[3] 0.18 lm CMOS Folded cascode 9 12.2 3.7 �8.7 19.8 1�0.9

[4] 0.18 lm CMOS Cascode with parallel-LC 10.8 9 2.5 �6.5 17.6 0.65�0.71

This work 0.18 lm CMOS Cascode with gain-enhanced L 9 16.5 4.5 �15 15 0.48�0.8

DOI 10.1002/mop MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 53, No. 3, March 2011 481