Design Efficient Multiplier Vhdl

8/11/2019 Design Efficient Multiplier Vhdl

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Final Year Project's is One place or all n!ineerin! Projects" Presentation"

seminar"

summer trainin! report an# lot more.

$O%&-%his wor is copyri!ht ()* to its +uthors. %his is only or #ucational

Purpose.

CERTIFIC$TE

This is to certify that the thesis entitled, TO DESIGN EFFICIENT MULTIPLIE

USING !"DL # s$%&itted %y M' (r$n Shar&a in )artial f$lfill&ents for the

re*$ire&ents for the a+ard of Master of Technoloy Deree in Electronics and

Co&&$nication Enineerin at -'M'I'T' ada$r is an a$thentic +or. carried o$t

%y hi& $nder &y s$)er/ision and $idance'

To the %est of &y .no+lede, the &atter e&%odied in the thesis has not %een

s$%&itted to any other Uni/ersity 0 Instit$te for the a+ard of any Deree'

Date1 Mr' Mano2 (rora

' "'O'D'E'C'E'De)tt'

-'M'I'T'ada$r

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Purpose.

CONTENTS

(%stract333333333333333333333333333333 45

List of

Fi$res333333333333333333333333333333ii

List of Ta%les iii

Introd$ction3333333333'33333333333333333346

!"DL 33333333333333333333333333333''''78

Filters33333333'''333333333333333'3333'''3'''9:

Ty)e of filters33333333333333333'3''3333333''''''96

(dders3'3333333333333333333'' 333333333;7


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Purpose.

Concl$sion3333333333333333333333333333 '5=

efrences33333333333333333333333333333'56



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Purpose.

Abstract

There are different entities that one +o$ld li.e to o)ti&i>e +hen desinin a !LSI circ$it'

These entities can often not %e o)ti&i>ed si&$ltaneo$sly, only i&)ro/e one entity at the

e?)ense of one or &ore others'The desin of an efficient &$lti)lier circ$it in ter&s of

)o+er, area, and s)eed si&$ltaneo$sly, has %eco&e a /ery challenin )ro%le&' Po+er

dissi)ation is reconi>ed as a critical )ara&eter in &odern !LSI desin field' In !ery Lare

Scale Interation, lo+ )o+er !LSI desin is necessary' M$lti)lication occ$rs fre*$ently in

finite i&)$lse res)onse filters, fast Fo$rier transfor&s, con/ol$tion, and other i&)ortant

DSP and &$lti&edia .ernels' The o%2ecti/e of a ood &$lti)lier is to )ro/ide a )hysically

co&)act, ood s)eed and lo+ )o+er cons$&in chi)' To sa/e sinificant )o+er

cons$&)tion of a !LSI desin, it is a ood direction to red$ce its dyna&ic )o+er that is the

&a2or )art of total )o+er dissi)ation' In this thesis, +e )ro)ose hih s)eed lo+@)o+er

&$lti)lier alorith&s' The %ooth &$lti)lier +ill red$ce the n$&%er of )artial )rod$cts

enerated %y a factor of 9' The adder +ill a/oid the $n+anted addition and th$s &ini&i>e

the s+itchin )o+er dissi)ation' The )ro)osed hih s)eed lo+ )o+er &$lti)lier can attain

s)eed i&)ro/e&ent and )o+er red$ction in the


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seminar"



Purpose.

This thesis )resents an efficient i&)le&entation of hih s)eed &$lti)lier $sin the array

&$lti)lier,shift A add alorith&,


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Purpose.

&$lti)liers +hich o)erate on diits in a )arallel fashion instead of %its %rin the

)i)elinin to the diit le/el and a/oid &ost ofthe a%o/e )ro%le&s' They +ere introd$ced

%y M' ' I%rahi& in 766;' These str$ct$res are iterati/e and &od$lar' The )i)elinin

done at the diit le/el %rins the %enefit of constant o)eration s)eed irres)ecti/e of the

si>e ofB the &$lti)lier' The cloc. s)eed is only deter&ined %y the diit si>e +hich is

already fi?ed %efore the desin is i&)le&ented'



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Purpose.

CHAPTER 2


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Purpose.

3.1. Basic binary multiplier

The o)eration of &$lti)lication is rather si&)le in diital electronics' It has its

oriin fro& the classical alorith& for the )rod$ct of t+o %inary n$&%ers' This

alorith& $ses addition and shift left o)erations to calc$late the )rod$ct of t+o

n$&%ers' T+o e?a&)les are )resented %elo+'10 x 8 = 80 -6 x = -2

1 0 1 0 1 0 1 0

1 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 1 1 1 0 1 0

1 0 1 0 0 0 0 0 0

1 0 1 0 0 0 0 1 1 1 0 1 0 0 0

!"#$re %&1&1'


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Purpose.

!"#$re %&1&2' Sined &$lti)lication alorith&



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Purpose.

3.2. Partial product generation

Partial )rod$ct eneration is the /ery first ste) in %inary &$lti)lier' These are

the inter&ediate ter&s +hich are enerated %ased on the /al$e of &$lti)lier' If

the &$lti)lier %it is 4B, then )artial )rod$ct ro+ is also >ero, and if it is 7B, then

the &$lti)licand is co)ied as it is' Fro& the 9nd %it &$lti)lication on+ards, each

)artial )rod$ct ro+ is shifted one $nit to the left as sho+n in the a%o/e

&entioned e?a&)le' In sined &$lti)lication, the sin %it is also e?tended to the

left' Partial )rod$ct enerators for a con/entional &$lti)lier consist of a series of

loic (ND ates as sho+n in Fi$re ;'9'7'

= : 5 8 ; 9 7 4

i

PPi= PPi: PPi5 PPi8 PPi; PPi9 PPi7 PPi4

!"#$re %&2&1' Partial )rod$ct eneration loic

Caref$l o)ti&i>ation of the )artial@)rod$ct eneration can lead to so&e



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Purpose.

s$%stantial delay and area red$ction H7'

Chapter

T(pe O) A**er+

ADDER

In electronics, an adder is a diital circ$it that )erfor&s addition of n$&%ers' In &odern

co&)$ters adders reside in the arith&etic loic $nit J(LUK +here other o)erations are

)erfor&ed' (ltho$h adders can %e constr$cted for &any n$&erical re)resentations, s$ch

as


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Purpose.

o$t)$t of a half adder is the s$& of t+o one@%it n$&%ers, +ith C %ein the &ost

sinificant of these t+o o$t)$ts'

The second ty)e of sinle %it adder is the f$ll adder' The f$ll adder ta.es into acco$nt a

carry in)$t s$ch that &$lti)le adders can %e $sed to add larer n$&%ers' To re&o/e

a&%i$ity %et+een the in)$t and o$t)$t carry lines, the carry in is la%eled Ci or Cin +hile

the carry o$t is la%eled Co or Cout'

Half a!!er

Fi@8'7 "alf adder circ$it diara&



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Purpose.

( half adder is a loical circ$it that )erfor&s an addition o)eration on t+o %inary diits'

The half adder )rod$ces a s$& and a carry /al$e +hich are %oth %inary diits'

Follo+in is the loic ta%le for a half adder1

In)$t O$t)$t

( < C S

4 4 4 4

4 7 4 7

7 4 4 7

7 7 7 4

Ta.e&1

F#ll a!!er



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Purpose.

In)$ts1 (,


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Purpose.

Fi@8'; Sche&atic sy&%ol for a 7@%it f$ll adder

( f$ll adder is a loical circ$it that )erfor&s an addition o)eration on three %inary diits'

The f$ll adder )rod$ces a s$& and carries /al$e, +hich are %oth %inary diits' It can %e

co&%ined +ith other f$ll adders Jsee %elo+K or +or. on its o+n'

In)$t O$t)$t

A B Ci

4 4 4

Co

4

S

4

4 4 7 4 7

4 7 4 4 7



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Purpose.

4 7 7 4

7 4 4 7

7 4 7 4

7 7 7 4

7 7 7 7

Ta.e&2Note that the final O ate %efore the carry@o$t o$t)$t &ay %e re)laced %y an O ate

+itho$t alterin the res$ltin loic' This is %eca$se the only discre)ancy %et+een O and



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Purpose.

O ates occ$rs +hen %oth in)$ts are 7P for the adder sho+n here, one can chec. this

is ne/er )ossi%le' Usin only t+o ty)es of ates is con/enient if one desires to

i&)le&ent the adder directly $sin co&&on IC chi)s'

( f$ll adder can %e constr$cted fro& t+o half adders %y connectin A andB to the in)$t

of one half adder, connectin the s$& fro& that to an in)$t to the second adder,

connectin Ci to the other in)$t and or the t+o carry o$t)$ts' E*$i/alently, S co$ld

%e &ade the three@%it ?or of A, B, and Ci and Co co$ld %e &ade the three@%it

&a2ority f$nction of A, B, and Ci' The o$t)$t of the f$ll adder is the t+o@%it arith&etic

s$& of three one@%it n$&%ers'



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Purpose.

CHAPTER /

M$.t"p."er t(pe+

M$lti)liers are cateori>ed relati/e to their a))lications, architect$re and the+ay the )artial )rod$cts are )rod$ced and s$&&ed $)'


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Purpose.

S0 !"#$re /&1'(rray &$lti)lier &echanis&

There are se/eral )ossi%le array to)oloies incl$din si&)le, do$%le and hiher@

order arrays'

/&2& S"p.e arra( $.t"p."er

In this ty)e of array, the o$t)$t of each ro+ of co$nters J;19 co&)ressorsK is thein)$t to the ne?t ro+ of co$nters H9' In the si&)le array, each ro+ of H;19

co&)ressors adds a )artial )rod$ct to the )artial s$&, eneratin a ne+ )artial

s$& and a se*$ence of carries' The delay of the array de)ends on the de)th of

the array' Therefore, the s$&&in ti&e for the si&)le array is N@9 H;19

co&)ressor delays, +here N is the n$&%er of )artial )rod$cts'

The dra+%ac. of this ty)e of array is the hard+are is $nder$tili>ed' The

co$nters are $sed only once in the calc$lation of the res$lt, for the re&ainin

ti&e, they are idle' This dra+%ac. can %e di&inished %y )i)elinin the

array so that se/eral &$lti)lications can occ$r si&$ltaneo$sly'Pi)elinin

+o$ld increase the thro$h)$t of the &$lti)lier, %$t +o$ld also increase the

latency and area of the &$lti)lier' ( f$lly )i)elined array is nor&ally a/oided,



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Purpose.

since the array +o$ld %e faster than the cloc. of )rocessor' Fi$re 8'9'7 de)icts

the layo$t of a si&)le array to)oloy' The dots re)resent the )artial )rod$cts'

!"#$re-/&2'Layo$t Of Si&)le (rray Technoloy



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/&%&Ser"a.Para..e. M$.t"p."er

In a serial0)arallel &$lti)lier,the &$lti)licand ? arri/es %it serially +hile the

&$lti)lier a is a))lied in a %it )arallel for&at'( co&&on a))roach $sed in

s$ch &$lti)liers is to enerate a ro+ or diaonal of %it )rod$cts in each ti&e

lot and )erfor& the additions conc$rrently'

S$))ose the data is )ositi/eQ4'Usin carry sa/e adder shift A add

alorith& can %e a))lied as sho+n in fi$re'

Fi$re@5';'Serial0)arallel &$lti)lier

Since is )rocessed %it serially and coefficient a is )rocessed %it )arallel,this

ty)e of &$lti)lier is called a serial0)arallel &$lti)lier


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/&/&Sh")t-a*-A** M$.t"p."er

Shift@and@add &$lti)lication is si&ilar to the &$lti)lication )erfor&ed %y

)a@)er and )encil' This &ethod adds the &$lti)licand X to itself Y ti&es,

+here Y de@notes the &$lti)lier' To &$lti)ly t+o n$&%ers %y )a)er and

)encil, the alorith& is to ta.e the diits of the &$lti)lier one at a ti&e fro&

riht to left, &$lti)lyin the &$lti@)licand %y a sinle diit of the &$lti)lier

and )lacin the inter&ediate )rod$ct in the a))ro)riate )ositions to the left

of the earlier res$lts'(s an e?a&)le, consider the &$lti)lication of t+o

$nsined 8@%it n$&%ers, R J7444K and 6 J7447K'

In the case of %inary &$lti)lication,

since the diits are 4 and 7, each ste)

of the &$lti)lication is si&)le' If the

&$lti)lier diit is 7, a co)y of

the &$lti)licand J7

&$lti)licandK is )laced in the

)ro)er )ositions if the &$lti)lier diit

is 4, a n$&%er o 4 diits J4 &$lti)licandK are )laced in the )ro)er

)ositions'

Consider the &$lti)lication of )ositi/e n$&%ers' The first /ersion of the&$lti)lier circ$it, +hich i&)le&ents the shift@and@add &$lti)lication &ethod

for t+o n@%it n$&%ers, is sho+n in Fi$re 5'5'7'

M$lti)licand 7444

M$lti)lier 7447

7444

4444

4444

7444

Prod$ct 7447444


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!"#$re /&/&1'First /ersion of the &$lti)lier circ$it

The 9n@%it )rod$ct reister JAK is initiali>ed to 4' Since the %asic

alorith& shifts the &$lti)licand reister JBK left one )osition each ste) to

alin the &$lti)licand +ith the s$& %ein acc$&$lated in the )rod$ct

reister, +e $se a 9n@%it &$lti)licand reister +ith the &$lti)licand )laced

in the riht half of the reister and +ith 4 in the left half'

!"#$re /&/&2&'The first /ersion of the &$lti)lication alorith&'


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Fi$re 5'5'9 sho+s the %asic ste)s needed for the &$lti)lication' The

alorith& starts %y loadin the &$lti)licand into theBreister, loadin the

&$lti)lier into the Qreister, and initiali>in theAreister to 4' The co$nter

N is initiali>ed to n' The least sinificant %it of the &$lti)lier reister J Q4K

deter&ines +hether the &$lti)licand is added to the )rod$ct reister' The

left shift of the &$lti)licand has the effect of shiftin the inter&ediate

)rod$cts to the left, 2$st as +hen &$lti)lyin %y )a)er and )encil' The riht

shift of the &$lti)lier )re)ares the ne?t %it of the &$lti)lier to e?@a&ine in

the follo+in iteration'

Exap.e 1

Usin 8@%it n$&%ers, )erfor& the &$lti)lication 6 79 J7447?7744K'

A+3er

Ta%le 9 sho+s the /al$e of reisters for each ste) of the &$lti)lication

alorith&'

,tructure o -omputer ,ystems

Table 3. ultiply e/ample usin! the frst 0ersion o the

al!orithm.

Ste% $ ( ) O%eraton

0 0000 0000 1100 0000 1001 Initializatin

1 0000 0000 1100 0001 0010 S!i"t l#"t B

0000 0000 0110 0001 0010 S!i"t $i%!t Q

2 0000 0000 0110 0010 0100 S!i"t l#"t B

0000 0000 0011 0010 0100 S!i"t $i%!t Q

3 0010 0100 0011 0010 0100 A&& B t A

0010 0100 0011 0100 1000 S!i"t l#"t B

0010 0100 0001 0100 1000 S!i"t $i%!t Q

4 0110 1100 0001 0100 1000 A&& B t A

0110 1100 0001 1001 0000 S!i"t l#"t B

0110 1100 0000 1001 0000 S!i"t $i%!t Q

The oriinal alorith& shifts the &$lti)licand left +ith >eros inserted in thene+ )ositions, so the least sinificant %its of the )rod$ct cannot chane after


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they are for&ed' Instead of shiftin the &$lti)licand left, +e can shift the

)rod$ct to the riht' Therefore the &$lti)licand is fi?ed relati/e to the

)rod$ct, and since +e are addin only n%its, the adder needs to %e only n

%its +ide' Only the left half of the 9n@%it )rod$ct reister is chaned d$rin

the addition'

(nother o%ser/ation is that the )rod$ct reister has an e&)ty s)ace +ith the

si>e e*$al to that of the &$lti)lier' (s the e&)ty s)ace in the )rod$ct

reister disa)@)ears, so do the %its of the &$lti)lier' In conse*$ence, the

final /ersion of the &$lti@)lier circ$it co&%ines the )rod$ct JAreisterK +ith

the &$lti)lier JQ reisterK' The A reister is only n %its +ide, and the

)rod$ct is for&ed in the A and Q reisters' Fi$re 5'5'; sho+s the ne+

/ersion of the circ$it'

!"#$re /&/&%: Final 0ersion o the multipliercirc$it'

the final /ersion of the &$lti)lication alorith& is sho+n in Fi$re 5'5';'


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Ta.e&

Booth Multiplication Algorithm4,,th M$.t"p."5at", A.#,r"th


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Step 2: Booth Algorithm

9ooth al!orithm re:uires eamination o the multiplier bits" an# shitin! o the

partialpro#uct. Prior to the shitin!" the multiplican# may be a##e# to partial pro#uct"subtracte# rom the partial pro#uct" or let unchan!e# accor#in! to the

ollowin! rules&

6oo at the frst least si!nifcant bits o the multiplier ;3


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1 2 3 3-

5555 5555 55 5

5555 5555 55 5

5555 5555 551 01110

1111

0000

0000

0011

1001

0

1

+## @Y (5555 A 5 B 5*,hit

1 2 3 3-

5555 5555 1100 5

5555 5555 55 5

5555 5555 55 5

5

55555555

55551

51

1111 1000 1100 1,hit only

We ha/e finished fo$r cycles, so the ans+er is sho+n, in the last ro+s of U and !

+hich is1 77777444 t+o

Note1


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4,,th $.t"p."5at", a.#,r"th ),r ra*"x

One of the sol$tions of reali>in hih s)eed &$lti)liers is to enhance )arallelis& +hichhel)s to decrease the n$&%er of s$%se*$ent calc$lation staes' The oriinal /ersion of the


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4 I i X9y

i 4 4 @9y

i 4 i @y

i I 4 @y

i I i X4

Ta%le : adi?8 Modified


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!"DL 1T"E L(NGU(GE


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Chapter-6 7&H&D&L&The La#$a#e

EPERIMENTAL

Many a))lications de&and hih thro$h)$t and real@ti&e res)onse, )erfor&ance

constraints that often dictate $ni*$e architect$res +ith hih le/els of conc$rrency' DSP

desiners need the ca)a%ility to &ani)$late and e/al$ate co&)le? alorith&s to e?tract

the necessary le/el of conc$rrency' Perfor&ance constraints can also %e addressed %y

a))lyin alternati/e technoloies' ( chane at the i&)le&entation le/el of desin %y the

insertion of a ne+ technoloy can often &a.e /ia%le an e?istin &arinal alorith& or

architect$re'

The !"DL lan$ae s$))orts these &odelin needs at the alorith& or %eha/ioral le/el,

and at the i&)le&entation or str$ct$ral le/el' It )ro/ides a /ersatile set of descri)tion

facilities to &odel DSP circ$its fro& the syste& le/el to the ate le/el' ecently, +e ha/e

also noticed efforts to incl$de circ$it@le/el &odelin in !"DL' (t the syste& le/el +e

can %$ild %eha/ioral &odels to descri%e alorith&s and architect$res' We +o$ld $se

conc$rrent )rocesses +ith constr$cts co&&on to &any hih@le/el lan$aes, s$ch as if,

case, loo), +ait, and assert state&ents' !"DL also incl$des $ser@defined ty)es, f$nctions,

)roced$res, and )ac.aes'Y In &any res)ects !"DL is a /ery )o+erf$l, hih@le/el,conc$rrent )rora&&in lan$ae' (t the i&)le&entation le/el +e can %$ild str$ct$ral

&odels $sin co&)onent instantiation state&ents that connect and in/o.e

s$%co&)onents' The !"DL enerate state&ent )ro/ides ease of %loc. re)lication and

control' ( dataflo+ le/el of descri)tion offers a co&%ination of the %eha/ioral and

str$ct$ral le/els of descri)tion' !"DL lets $s $se all three le/els to descri%e a sinle

co&)onent' Most i&)ortantly, the standardi>ation of !"DL has s)$rred the de/elo)&ent

of &odel li%raries and desin and de/elo)&ent tools at e/ery le/el of a%straction' !"DL,

as a consens$s descri)tion lan$ae and desin en/iron&ent, offers desin tool

)orta%ility, easy technical e?chane, and technoloy insertion


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!"DL1 The lan$ae

(n entity declaration, or entity, co&%ined +ith architect$re or %ody constit$tes a !"DL

&odel' !"DL calls the entity@architect$re )air a desin entity'


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The /ariety of conc$rrent state&ent ty)es i/es !"DL the descri)ti/e )o+er to create

and co&%ine &odels at the str$ct$ral, dataflo+, and %eha/ioral le/els into one si&$lation

&odel' The str$ct$ral ty)e of descri)tion &a.es $se of co&)onent instantiation

state&ents to in/o.e &odels descri%ed else+here' (fter declarin co&)onents, +e $se

the& in the co&)onent instantiation state&ent, assinin )orts to local sinals or other

)orts and i/in /al$es to enerics' in/ert1 M )ort &a) J 2 VQ a VQ c); We can then

%ind the co&)onents to other desin entities thro$h confi$ration s)ecifications in

!"DLs architect$re declarati/e section or thro$h se)arate confi$ration declarations'

The dataflo+ style &a.es +ide $se of a n$&%er of ty)es of conc$rrent sinal assin&ent

state&ents, +hich associate a taret sinal +ith an e?)ression and a delay' The list of

sinals a))earin in the e?)ression is the sensiti/ity list the e?)ression &$st %e e/al$ated

for any chane on any of these sinals' The taret sinals o%tain ne+ /al$es after the

delay s)ecified in the sinal assin&ent state&ent' If no delay is s)ecified, the sinal

assin&ent occ$rs d$rin the ne?t si&$lation cycle1

c ZV a X % after delay

!"DL also incl$des conditional and selected sinal assin&ent state&ents' It $ses %loc.

state&ents to ro$) sinal assin&ent state&ents and &a.es the& synchrono$s +ith a

$arded condition'


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c ZV i after delay

end )rocess

Other conc$rrent state&ents incl$de the conc$rrent assertion state&ent, conc$rrent

)roced$re call, and enerate state&ent' Pac.aes are desin $nits that )er&it ty)es and

o%2ects to %e shared' (rith&etic o)erations do&inate the e?ec$tion ti&e of &ost Diital

Sinal Processin JDSPK alorith&s and c$rrently the ti&e it ta.es to e?ec$te a

&$lti)lication o)eration is still the do&inatin factor in deter&inin the instr$ction cycle

ti&e of a DSP chi) and ed$ced Instr$ction Set Co&)$ters JISCK' (&on the &any

&ethods of i&)le&entin hih s)eed )arallel &$lti)liers, there is one %asic a))roach

na&ely ero' The Modified


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ANAL;SIS

7HDL 5,*e ),r +"xtee "t a**er

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

li%rary IEEE

$se IEEE'STD[LOGIC[ii:8'(LL $se

IEEE'STD[LOGIC[(IT"'(LL $se

IEEE'STD[LOGIC[SIGNED'(LL

@@@@ Unco&&ent the follo+in li%rary declaration if instantiatin

@@@@ any ilin? )ri&iti/es in this code'@@li%rary UNISIM

@@$se UNISIM'!Co&)onents'all

entity si?teen%it[fa is

Port J a 1 in STD[LOGIC[!ECTO Ji5 do+nto 4K

% 1 in STD[LOGIC[!ECTO Ji5 do+nto 4K

@@ cin 1 in STD[LOGIC

yo$t 1 o$t STD[LOGIC[!ECTO Ji5 do+nto 4K

co$t 1 o$t STD[LOGICK

end si?teen%it[fa

architect$re


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s$& 1 OUT std[loic

co$t 1 OUT std[loicK

END COMPONENT

%ein

carryiJ4KZV4

i1 for i in 4 to i5 enerate

f4 1 t+o%it[add POT M(PJaJiK, %JiK,carryiJiK,yo$tJiK, carryiJiXiKK

@@ inter[carrZVcarryJiXiK

end enerate iP

co$tZVcarryiJi:K

end


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a 1 in std[loic[/ectorJ= do+nto 4K

% 1 in std[loic[/ectorJ= do+nto 4K

)rod 1 o$t std[loic[/ectorJi5do+nto 4KK

end &$lt:8

architect$re


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end enerate

)cJnKJ4KZV4

addlast1for . in i to n@ienerate

)sJnKJ.KZV)cJnKJ.@iK?or )cJn@iKJ.@iK?or )[email protected]

)cJnKJ.KZVJ)cJnKJ.@iK and )cJn@iKJ.@iKK or

J)cJnKJ.@iKand )[email protected] or

J)cJn@iKJ.@iKand )[email protected]

end enerate

)rodJ9n@iKZV)cJnKJn@iK

)rodJ9n@9 do+nto nKZV)sJnKJn@ido+nto iK

end


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entity %ooth[&$lt is

Port J a 1 in STD[LOGIC[!ECTO J= do+nto 4K

% 1 in STD[LOGIC[!ECTO J= do+nto 4K

yo$t 1 o$t STD[LOGIC[!ECTO Ji5 do+nto 4K

o/f1 o$t std[loicK

end %ooth[&$lt

architect$re


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$91 %ooth[encoder POT M(PJa,%J5 do+nto ;K,));K

$;1 %ooth[encoder POT M(PJa,%J= do+nto 5K,))8K

siZV))9Ji;do+nto 4KAY44Y

s9ZV));Jiido+nto 4KAY4444Y

s;ZV))8J6 do+nto 4KAY444444Y

$81 si?teen%it[fa POT M(PJ))i,si,s$&i,.iK

$51 si?teen%it[fa POT M(PJs$&i,s9,s$&9,.9K

$:1 si?teen%it[fa POT M(PJs$&9,s;,yo$t,o/fK

end


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Port J a 1 in std[loic[/ectorJ= do+nto 4K

ar 1 in std[loic[/ectorJ9 do+nto 4K

))rod 1 o$t std[loic[/ectorJi5do+nto 4KK

end %ooth[encoder

architect$re


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ESULTS


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ESULTS OF DIFFEENT MULTIPLIES

Co&&on of FPG( reso$rces $tili>ed %y different &$lti)lication alorith&s

Power

Analysis

Shit an!

A!!

algorithm

Array

Multiplier

Booth

"a!i#$%

Multiplier

Pyrami!

Algorithm

Selecte!

&e'ice

8s755t7CD-

48s755t7CD-4 8s755t7CD-4 8s755t7CD-4

Total Power

(onsumption

)in m*+

8Em C5m 8Em 8Em

Po+er analysis of different &$lti)lication alorith&

&e'ice

,tili-ation

Summary

Shit an!

A!!

algorithm

Array

Multiplier

Booth

"a!i#$%

Multiplier

Pyrami!

Algorithm

Selecte!

&e'ice

8s755t7CD-

48s755t7CD-4 8s755t7CD-4 8s755t7CD-4

.umber o

Slices

G out o

H75

I

D4 out o

H75

8I

H7 out o

H75

I

GH out H75

HI

.umber o %

$input /,Ts:

87 out o

8G45

I

78 out o

8G45

8I

DG out o

8G45

4I

8EE out o

8G45

HI

.umber o

bon!e! Bs

84 out o

E8

HI

87 out o

E8

GI

88 out o

E8

HI

DC out o E8

8EI

Total

3ui'alent

number o

gate count

or !esign

4HC E8G 5E 487D


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Ti&e

analysis

Shit an!

A!!algorithm

Array

Multiplier

Booth

"a!i#$%

Multiplier

Pyrami!

Algorithm

5'47ns ;9'447ns ;='967 3('43)n*

CONLUSION


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CONCLUSION

O$r )ro2ect i/es a clear conce)t of different &$lti)lier and their i&)le&entation in ta)

delay FI filter' We fo$nd that the )arallel &$lti)liers are &$ch o)tion than the serial

&$lti)lier' We concl$ded this fro& the res$lt of )o+er cons$&)tion and the total area' In

case of )arallel &$lti)liers, the total area is &$ch less than that of serial &$lti)liers'

"ence the )o+er cons$&)tion is also less' This is clearly de)icted in o$r res$lts' This

s)eeds $) the calc$lation and &a.es the syste& faster'

While co&)arin the radi? 9 and the radi? 8 %ooth &$lti)liers +e fo$nd that radi? 8

cons$&es lesser )o+er than that of radi? 9' This is %eca$se it $ses al&ost half n$&%er of

iteration and adders +hen co&)ared to radi? 9'

When all the threse &$lti)liers +ere co&)ared +e fo$nd that array &$lti)liers are

&ost )o+er cons$&in and ha/e the &a?i&$& area' This is %eca$se it $ses a lare

n$&%er of adders' (s a res$lt it slo+s do+n the syste& %eca$se no+ the syste& has to

do a lot of calc$lation'

M$lti)liers are one the &ost i&)ortant co&)onent of &any syste&s' So +e al+ays need

to find a %etter sol$tion in case of &$lti)liers' O$r &$lti)liers sho$ld al+ays cons$&e

less )o+er and co/er less )o+er' So thro$h o$r )ro2ect +e try to deter&ine +hich of the

these alorith&s +or.s the %est' In the end +e deter&ine that radi? 8 &odified %ooth

alorith& +or.s the %est'


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RE!RENCES

We%sites referred1

i' + + +'+i.i)edia'co &

9' + + +'ho+st$ffs+or. 'co &

;' + + +'?il in?'co&


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:O'T'Chen,S'Wan and ,W'W$#Mini&isation of s+itchin acti/ities o )artial )rod$cts for

desinin lo+ )o+er &$lti)liers#IEEE Trans'!ery Lare Scale Inteer'J!LSIKSyst'!ol'77,N4'@;,))8,

= 2Wen@Chan eh and Chein@Wei -en, "ih@s)eed hih s)eed )i)elined

Design Efficient Multiplier Vhdl

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