Design Basics on Power Amplifiers
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Design Basics on Power Amplifiers
Wednesday, 16th December 2015
Pascual D. Hilario Re
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Outline1. Introduction2. Design3. Manufacturing4. Results5. Conclusions and Future work
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What is amplification?
1. Introduction
3
The operation of an electronic device increasing the power of a signal.
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Amplifiers depending on operating frequency
1. Introduction
4
Low frequency High frequency or RF
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Transistor
Inpu t MatchingNetwork
Outpu t MatchingNetwork
Bias Network(Gate)
Bias Netwo rk(Drain)
RF in
RF out
VgsVds
1. Introduction
5
Basic Microwave Amplifier scheme
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1. Introduction
6
Main concepts to work with:
• Linearity: capability of an amplifier to reproduce
increased exact copies of the input signal.
• Efficiency: how much of the DC power supplied to the
amplifier is transformed into amplification.
They are in inverse proportion.These characteristics determine the class of the amplifier!
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Transistor Characteristic IV Curves
1. Introduction
7
𝑉 𝐶𝐸
𝐼𝐶
𝐼𝐵=100𝜇 𝐴10𝑚𝐴
C (Collector) or D (Drain)
E (Emitter) or S (Source)
B (Base) or G (Gate)
V
+ _
𝑉 𝐶𝐸
𝐼𝐶
𝑰 𝑩
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Load-line
1. Introduction
8
DC equivalent
AC equivalent
𝑉 𝐶𝐸
𝐼𝐶
𝑉 𝐶𝐶−𝑉 𝑅𝐶−𝑉 𝐶𝐸−𝑉 𝑅𝐸
=0
𝑉 𝐶𝐶− 𝐼𝐶 𝑅𝐶−𝑉 𝐶𝐸− 𝐼𝐸 𝑅𝐸=0
𝑉 𝐶𝐶− 𝐼𝐶 (𝑅¿¿ 𝐶+𝑅𝐸)−𝑉 𝐶𝐸=0¿
Load-line equation (y = mx+n):
𝐼𝐶=−1
𝑅𝐶+ 𝑅𝐸𝑉 𝐶𝐸+
𝑉 𝐶𝐶
𝑅𝐶+𝑅𝐸
In saturation… Cut-off… 𝑉 𝐶𝐶
𝑅𝐶+𝑅𝐸
𝑉 𝐶𝐶
Q-Point
DC Load-line
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Load-line
1. Introduction
9
DC equivalent
AC equivalent
𝑣𝐶𝐸=−𝑖𝐶𝑟 𝐶
𝑉 𝐶𝐸−𝑉 𝐶𝐸𝑄=− ( 𝐼𝐶− 𝐼𝐶𝑄)𝑟𝐶
Load-line equation (y = mx+n):
𝐼𝐶=− 1𝑟𝐶
𝑉 𝐶𝐸+𝑉 𝐶𝐸𝑄
𝑟 𝐶+𝐼𝐶𝑄
𝑖𝐶
𝑉 𝐶𝐸
In saturation… In Cut-off…
Q-Point
𝑰 𝑪𝑸+𝑽 𝑪𝑬𝑸
𝒓 𝑪
𝑽 𝑪 𝑬𝑸+ 𝑰𝑪𝑸𝒓 𝑪
𝐼𝐶
AC Load-line
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Load-line
1. Introduction
10
Q-Point
𝑰 𝑪𝑸+𝑽 𝑪𝑬𝑸
𝒓 𝑪
𝑽 𝑪 𝑬𝑸+ 𝑰𝑪𝑸𝒓 𝑪 𝑉 𝐶𝐸
𝐼𝐶
AC Load-line
𝑣 𝐶𝐸
/𝐷𝑆≡
𝑣 𝑅𝐹 𝑜
𝑢𝑡
𝑖𝐶𝐸 /𝐷𝑆≡𝑖𝑅 𝐹𝑜𝑢𝑡
𝑖 𝐵≡𝑖 𝑅
𝐹 𝑖𝑛
𝑣 𝐺𝑆≡𝑣 𝑅
𝐹 𝑖𝑛
or
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Power Amplifier Classes
1. Introduction
11
Class Conduction Angle
A θ = 2π
AB π < θ < 2π
B θ = π
C θ < π
D – T θ ≈ 0
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Power Amplifier Classes
1. Introduction
12
Clase A Clase B
Clase AB Clase C
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Power Amplifier Classes
1. Introduction
13
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Outline1. Introduction2. Design3. Manufacturing4. Results5. Conclusions and Future work
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Transistor Tecnology Selection• GaN HEMT:
High Efficiency High Gain Great Bandwidth Low Power Consumption
Selección del Transistor
• CGH40010F (Cree Inc.)
2. Design
15
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IV Characteristics and Q-Point
2. Design
16
0 30 60 84Vds (V)
IV Curves
0
500
1000
1500
2000
2400
Ids
(mA
)
IV Curves (mA)
Q-Point (28V, 482mA)
S.O.A.
TrVi Ii
S
1 2
3
4 5 6
CGH40010F_R6_VAID=Q1Tbase=25Rth=8
Swp Step
IVCURVEID=IV1VSWEEP_start=0 VVSWEEP_stop=84 VVSWEEP_step=1 VVSTEP_start=-10 VVSTEP_stop=2 VVSTEP_step=0.2 V
• Maximum drain voltage (84 V)• Maximum drain current (1500 mA)• Cut-off threshold (67 mA)• Saturation threshold• Maximum dissipated power (14 W)
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Dynamic/AC Load-line
2. Design
17
TrVi Ii
S
1 2
3
4 5 6
CGH40010F_R6_VAID=Q1Tbase=25Rth=8
0.000399 mA
-2.2 V
482 mA
28 V
482 mA0 V
0 mA27.7 V
482 mA0 V
0 mA107 V
I_METERID=Id_intr
482 mAV_METERID=Vd_intr
DCVSID=VgsV=-2.2 V
0.000398 mA-2.2 V
I_METERID=I_in
0 mA
0 V
0 V
I_METERID=Ig
0.000399 mA
-2.2 V
DCVSID=VdcV=28 V
482 mA28 V
V_METERID=Vd
I_METERID=Id
482 mA
28 V
3:Bias
12
LTUNER2ID=TU3Mag=0Ang=0 DegZo=50 Ohm
0.000399 mA0 mA
0.000398 mA
3:Bias
1 2
LTUNER2ID=TU1Mag=0Ang=0 DegZo=50 Ohm
482 mA 0 mA
0 V
482 mA
V_METERID=VM_trise
PORTP=2Z=50 Ohm
0 mA
PORT_PS1P=1Z=50 OhmPStart=0.6 dBmPStop=40.6 dBmPStep=1 dB
0 mA
PORT1P=1Z=50 OhmPwr=27.6 dBm
Conn_Vi
27.7 V
Conn_Vi
27.7 V
Conn_Ii
0 V
Conn_Ii
0 V
0 30 60 84Vds (V)
IV Curves
0
500
1000
1500
2000
2400
Ids
(mA
)
28 V482.3 mAVstep = -2.2 V
IV Curves (mA)
DLL @ 7.6dBm (mA)
DLL @ 17.6dBm (mA)
DLL @ P1dB (mA)
0 0.3 0.6 0.816Time (ns)
RF in VS. RF out
-600
-400
-200
0
200
400
600
P1d
B In
put
Pow
er
-300
-200
-100
0
100
200
300
20dB
m I
nput
Pow
er
RF IN @ 20dBm (mA)
RF OUT @ 20dBm (mA)RF IN @ P1dB (mA)
RF OUT @ P1dB (mA)
DCVSID=VgsV=-2.2 V
0.000398 mA-2.2 V
I_METERID=I_in
0 mA0 V
0 V
I_METERID=Ig
0.000399 mA-2.2 V
3:Bias
12
LTUNER2ID=TU3Mag=0Ang=0 DegZo=50 Ohm
0.000399 mA0 mA
0.000398 mA
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Gain, Output Power and PAE
2. Design
18
0.6 10.6 20.6 30.6 40.6Power (dBm)
Pin VS Pout and Gain
0
10
20
30
40
50
27.6 dBm10.9 dB
18.52 dBm11.89 dB
Pout (dBm)
PGain (dB)
PAE (%)
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Stability
• Critical factor in order to avoid oscillations ()
• This is due to the negative either input or output resistance
2. Design
19
𝑅𝑒 {𝑍𝑆+𝑍 𝑖𝑛}<0 𝑅𝑒 {𝑍𝑜𝑢𝑡 +𝑍 𝐿 }<0
TransistorInput Matching Network
Output Matching Network
S in out L
0Z
0Z
𝑍=𝑍 01+Γ1− Γ
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Conditional Stability
Stability• Border which delimits between stable and unstable
regions:
2. Design
20
|Γ 𝑖𝑛|>1 |Γ 𝑖𝑛|<1
|Γ 𝑖𝑛|>1|Γ 𝑖𝑛|<1
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Unconditional Stability Unconditional Unstability
Stability• Border which delimits between stable and unstable
regions:
2. Design
21
|Γ 𝑖𝑛|>1
|Γ 𝑖𝑛|<1
|Γ 𝑖𝑛|<1
|Γ 𝑖𝑛|>1
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Stability2. Design
22
0 1.0
1.0
-1.0
10.0
10.0-10.0
5.0
2.0
3.0
4.0
0.2
0.4
0.6
0.8
0.8
-0.8
Stability CirclesSwp Max
1
Swp Min-1
Input Circle
Output Circle
• Stability circles @ → Potentially unstable
• Dashed lines → Unstable region
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Stability Factor: K-Δ Test
• It is convenient to have a design with in a reasonable BW
2. Design
23
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Stabilization methods
2. Design
24
50 2050 4050 6050 8050 10000Frequency (MHz)
Initial K Factor
0
2
4
6
8
2450 MHz4.424
2450 MHz0.5643
K (no resistor)
K (gate resistor)
0 1.0
1.0
-1.0
10.0
5.0
2.0
3.0
4.0
0.2
0.4
0.6
0.8
Stability Circles before stabilizationSwp Max3000MHz
Swp Min2000MHz
Input Stability Circles
Output Stability Circles
0 1.0
1.0
-1.0
10.0
5.0
2.0
3.0
4.0
0.2
0.4
0.6
0.8
Stability Circles after stabilizationSwp Max3000MHz
Swp Min2000MHz
Input Stability Circles
Output Stability Circles
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Unilateral Approximation
2. Design
25
𝑈=| 𝑆11𝑆12𝑆21𝑆22
(1−|𝑆11|2 ) (1−|𝑆22|
2 )|−20 log (1+𝑈 )<𝐺𝑇 −𝐺𝑇𝑈 (𝑑𝐵 )<−20 log (1−𝑈 )
Maximum gain design. Bilateral case:
Γ 𝐼𝑁=𝑆11+𝑆12𝑆21𝚪𝑳
1−𝑆22𝚪𝑳=Γ𝑆
∗
Γ𝑂𝑈𝑇=𝑆22+𝑆12𝑆21𝚪𝑺
1−𝑆11𝚪𝑺=Γ 𝐿
∗
Maximum gain design. Unilateral case:
Γ 𝐼𝑁=𝑆11=Γ 𝑆∗
Γ𝑂𝑈𝑇=𝑆22=Γ 𝐿∗
2-Port Device11S 22S
21S
?012 S
−3.7225 𝑑𝐵 ¿ 𝐺𝑇−𝐺𝑇𝑈 (𝑑𝐵 )<¿ 4.5775𝑑𝐵¿
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Load-Pull
2. Design
26
Process whereby a set of points of the Smith Chart are evaluated in
terms of good performance as potential candidates to be the final
reflection coefficient for the Output Matching Network.
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Load-Pull
2. Design
27
DCVSID=VDSV=28 VDCVS
ID=VGSV=-2.2 V
V_METERID=Vd
V_METERID=Vg
I_METERID=Ig
I_METERID=Id
Xo Xn. . .
SWPVARID=BiasVarName="iBias"Values=stepped(3,4,0.5)UnitType=None
Xo Xn. . .
SWPVARID=GammaL3VarName="iGammaL3"Values=stepped(-180,180,60)UnitType=None
Xo Xn. . .
SWPVARID=GammaL2VarName="iGammaL2"Values=stepped(0,360,90)UnitType=None
TrVi Ii
S
1 2
3
4 5 6
CGH40010F_R6_VAID=Q1Tbase=25Rth=8
3:Bias
12
LTUNER2ID=SourceTuner1Mag=0.5Ang=0 DegZo=50 Ohm
3:Bias
1 2
LTUNER2ID=LoadTuner1Mag=0.5Ang=0 DegZo=50 Ohm
PORTP=2Z=50 Ohm
PORT_PS1P=1Z=50 OhmPStart=0.600000000000001 dBmPStop=30.6 dBmPStep=1 dB
7
⦁ Attach gate / base current & voltage meters to desired device pin ⦁ Attach drain / collector current & voltage meters to desired device pins ⦁ Note that current should always defined into the desired pin
4
⦁ Set the Source Tuner to the desired impedance. ⦁ For 50 Ohms, set:
Mag1 = 0Ang1 = 0
2
⦁ Set power sweep ⦁ Disable power sweep by
replacing with PORT1
1
⦁ Enable / Disable SWPVAR blocks based on your needs ⦁ Set enabled SWPVAR sweep values ⦁ Do not change any swept variable names. ⦁ Contact technical support to sweep additional
variables
6
⦁ Replace with your DUT
iBias=3
iGammaL3=0iGammaL2=0
5
⦁ Replace DCVS with DCCS as needed
⦁ Do not delete any of the tuners or voltage and current meters; they are all needed for load pull simulation due to the switch to A/B wave file formats
⦁ It is okay to rename this schematic
3
⦁ Set schematic frequencies under schematic options
• AWR has its own script that automates the process
• Source-Pull is still in beta phase →
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Load-Pull
2. Design
28
Once the Load-Pull has been performed, the points that agree with the design
specifications are chosen.
0 1.0
1.0
-1.0
10.0
10.0
-10.0
5.0
5.0
-5.0
2.0
2.0
-2.0
3.0
3.0
-3.0
4.0
4.0
-4.0
0.2
0.2
-0.2
0.4
0.4
-0.4
0.6
0.6
-0.6
0.8
0.8
-0.8
Output Matching NetworkSwp Max2.6e+009
Swp Min11.1
Desired MN Impedance (Ohm)
Obtained MN Impedances (from 2.3 to 2.6 GHz)
GTrans Contours
PAE Contours
Output Stab. Circle
LTUNERID=TU1Mag=0.44152Ang=149.3904 DegZo=50 Ohm
TLINID=50Z0=50 OhmEL=47 DegF0=2450 MHz
CAPID=C1C=50 pF
TLINID=TL1Z0=50 OhmEL=45 DegF0=2450 MHz
OPENID=J1
PORTP=1Z=50 Ohm
PORTP=2Z=50 Ohm
PORTP=3Z=50 Ohm
PORTP=4Z=50 Ohm
Γ 𝑜𝑢𝑡=0.44152∠149.3904 °
0 1.0
1.0
-1.0
10.0
10.0
-10.0
5.0
5.0
-5.0
2.0
2.0
-2.0
3.0
3.0
-3.0
4.0
4.0
-4.0
0.2
0.2
-0.2
0.4
0.4
-0.4
0.6
0.6
-0.6
0.8
0.8
-0.8
Load PullSwp Max51.2778
Swp Min11.1
12.008 dBr 0.409879x 0.152749
51.278 %r 0.395923x 0.261322
Max. PAE @ P1dB
PAE @ P1dB
Max. GTrans @ P1dB
GTrans @ P1dB
Output Stability Circle
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LTUNERID=TU1Mag=0.44152Ang=149.3904 DegZo=50 Ohm
TLINID=50Z0=50 OhmEL=47 DegF0=2450 MHz
CAPID=C1C=50 pF
TLINID=TL1Z0=50 OhmEL=45 DegF0=2450 MHz
OPENID=J1
PORTP=1Z=50 Ohm
PORTP=2Z=50 Ohm
PORTP=3Z=50 Ohm
PORTP=4Z=50 Ohm
Load-Pull
2. Design
29
𝑍 𝑖𝑛=𝑍0𝑍𝐿+ 𝑗 𝑍0 tan (𝛽𝑙)𝑍 0+ 𝑗 𝑍𝐿 tan (𝛽𝑙)
01.0
-1.0
1.0
10.0
-1 0.0
10.0
5.0
-5 .0
5.0
2.0
-2 .02.0
3.0
-3 .0
3.0
4.0
-4 .0
4.0
0.2
-0.2
0.20.4
-0.4
0. 4
0.6
-0.6
0.6
0.8
-0.8
0.8
0 1.0
1.0
-1.0
10.0
10 .0
-10.0
5.0
5. 0
-5.0
2.0
2.0
-2.0
3.0
3.0
-3.0
4.0
4.0
-4.0
0.2
0.2
-0.2
0.4
0.4
-0.4
0.6
0.6
-0.6
0.8
0.8
-0.8
OMNSwp Max2450MHz
Swp Min2450MHz
Series TXLine
Open STUB
Γ 𝑜𝑢𝑡𝚪𝒐𝒖𝒕 Γ 1
𝚪𝟏
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Input Matching Network
2. Design
30
0 1.0
1.0
-1.0
10.0
10 .0
-10.0
5.0
5. 0
-5.0
2.0
2.0
-2.0
3.0
3.0
-3.0
4.0
4.0
-4.0
0.2
0.2
-0 .2
0.4
0.4
-0.4
0.6
0.6
-0.6
0.8
0.8
-0.8
Input Matching NetworkSwp Max2.6e+009
Swp Min2.3e+009
2450 MHzr 1.14997e-005x -0.435895
2450 MHzr 0.159695x -0.366266
Desired MN Impedance (Ohm)Obtained MN Impedances (from 2.3 to 2.6 GHz)Input Stab. CircleAfter parallelOpen Stub
• Conjugate Matching
TLINID=TL2Z0=17.93 OhmEL=24.3 DegF0=2450 MHz
OPENID=J1
TLINID=TL1Z0=48.27 OhmEL=65.7 DegF0=2450 MHz
PORTP=1Z=50 Ohm
PORTP=2Z=50 Ohm
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Bias Network
2. Design
31
• Critical design part in order to avoid RF leakage through the bias network.
• Many possible configurations:a. Low BWb. Acceptable BWc. Good BW and reduced size
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Bias Network
2. Design
32
TrVi Ii
S
1 2
3
4 5 6
CGH40010F_R6_VAID=Q1Tbase=25Rth=8
I_METERID=Id1
V_METERID=Vd1
I_METERID=Ig1
CAPID=C2C=20 pF
I_METERID=I_in1
MLINID=TL6W=2.1394617455677 mmL=9.00788441856134 mmMSUB=RO_RO4350B1
MLINID=TL7W=1.13179 mmL=18.2827939523261 mmMSUB=RO_RO4350B1
MLINID=TL14W=1.13179 mmL=8.42648946346399 mmMSUB=RO_RO4350B1
MLINID=TL20W=1.13179 mmL=3.44366958458732 mmMSUB=RO_RO4350B1
MLINID=TL27W=1.13179 mmL=6.2 mmMSUB=RO_RO4350B1
MLINID=TL28W=1.13179 mmL=3.9182030314894 mmMSUB=RO_RO4350B1
MOPEN$ID=TL12MSUB=RO_RO4350B1
1 2
3
MTEE$ID=TL15MSUB=RO_RO4350B1
RESID=R1R=6.81 Ohm
1 2
1 2
GPROBE2ID=GP1
1 2
1 2
GPROBE2ID=GP2
V_METERID=Vd2
I_METERID=Id2
V_METERID=VM_triseFinal
12
3
MTEE$ID=TL13MSUB=RO_RO4350B1
CAPID=C5C=47000 pF
DCVSID=Vgs1V=-2.2 V
MLINID=TL4W=W_TLStub mmL=L_TL2Stub mmMSUB=RO_RO4350B1
MLINID=TL22W=1.09377006058279 mmL=1.0929717637931 mmMSUB=RO_RO4350B1
MLINID=TL23W=5 mmL=5 mmMSUB=RO_RO4350B1
MLINID=TL26W=1.11213944458008 mmL=2.49627311533999 mmMSUB=RO_RO4350B1
MSRSTUB2ID=ST1Ro=Ro_stub mmWg=Wg_stub mmW=W_TLStub mmTheta=Theta_stub DegMSUB=RO_RO4350B1
1
2
3MTEE$ID=TL9MSUB=RO_RO4350B1
MVIA1PID=V4D=1 mmH=0.52578 mmT=0.017 mmW=5 mmRHO=0.7MSUB=RO_RO4350B1
RESID=R2R=37.4 Ohm
MLINID=TL8W=W_TLStub mmL=L_TL1Stub mmMSUB=RO_RO4350B1
PORT_PS1P=1Z=50 OhmPStart=0 dBmPStop=40 dBmPStep=1 dB
PORT1P=1Z=50 OhmPwr=10 dBm
Conn_ViConn_Ii
Low Freq. Stabilization Resistor
Bypass Capacitor
![Page 33: Design Basics on Power Amplifiers](https://reader034.fdocuments.us/reader034/viewer/2022042520/58a39f191a28abb1348b6807/html5/thumbnails/33.jpg)
Final design
2. Design
33
TrVi Ii
S
1 2
3
4 5 6
CGH40010F_R6_VAID=Q1Tbase=25Rth=8
I_METERID=Ig1
CAPID=C2C=20 pF
I_METERID=I_in1
MLINID=TL6W=2.1394617455677 mmL=9.00788441856134 mmMSUB=RO_RO4350B1
MLINID=TL7W=1.13179 mmL=18.2827939523261 mmMSUB=RO_RO4350B1
MLINID=TL14W=1.13179 mmL=8.42648946346399 mmMSUB=RO_RO4350B1
MLINID=TL20W=1.13179 mmL=3.44366958458732 mmMSUB=RO_RO4350B1
MLINID=TL27W=1.13179 mmL=6.2 mmMSUB=RO_RO4350B1
MLINID=TL28W=1.13179 mmL=3.9182030314894 mmMSUB=RO_RO4350B1
MOPEN$ID=TL12MSUB=RO_RO4350B1
1 2
3
MTEE$ID=TL15MSUB=RO_RO4350B1
RESID=R1R=6.81 Ohm
1 2
1 2
GPROBE2ID=GP1
V_METERID=Vd2
I_METERID=Id2
12
3
MTEE$ID=TL13MSUB=RO_RO4350B1
MLINID=TL4W=W_TLStub mmL=L_TL2Stub mmMSUB=RO_RO4350B1
MLINID=TL22W=1.09377006058279 mmL=1.0929717637931 mmMSUB=RO_RO4350B1
MLINID=TL26W=1.11213944458008 mmL=2.49627311533999 mmMSUB=RO_RO4350B1
MSRSTUB2ID=ST1Ro=Ro_stub mmWg=Wg_stub mmW=W_TLStub mmTheta=Theta_stub DegMSUB=RO_RO4350B1
1
2
3MTEE$ID=TL9MSUB=RO_RO4350B1
RESID=R2R=37.4 Ohm
MLINID=TL8W=W_TLStub mmL=L_TL1Stub mmMSUB=RO_RO4350B1
PORT_PS1P=1Z=50 OhmPStart=0 dBmPStop=40 dBmPStep=1 dB
PORT1P=1Z=50 OhmPwr=10 dBm
Conn_ViConn_Ii
CAPID=C1C=47 pF
CAPID=C4C=47000 pF
MLINID=TL1W=1.13179 mmL=9.1 mmMSUB=RO_RO4350B1
MLINID=TL2W=1.15424925832038 mmL=8.8091341147881 mmMSUB=RO_RO4350B1
MLINID=TL3W=1.13179 mmL=2.83546915660083 mmMSUB=RO_RO4350B1
MLINID=TL5W=W_DoubleStub mmL=L_DoubleStub mmMSUB=RO_RO4350B1
MLINID=TL11W=W_DoubleStub mmL=L_DoubleStub mmMSUB=RO_RO4350B1
MLINID=TL17W=1.13179 mmL=1.83798534101102 mmMSUB=RO_RO4350B1
MLINID=TL19W=1.13179 mmL=3.27959942836177 mmMSUB=RO_RO4350B1
MLINID=TL21W=W_TLStub mmL=L_TL2Stub mmMSUB=RO_RO4350B1
MLINID=TL25W=1.13179 mmL=2.36734037034666 mmMSUB=RO_RO4350B1
MLINID=TL29W=1.09977380371094 mmL=1.09910240478516 mmMSUB=RO_RO4350B1
MLINID=TL34W=W_TLStub mmL=L_TL1Stub mmMSUB=RO_RO4350B1
MOPEN$ID=TL10MSUB=RO_RO4350B1
MOPEN$ID=TL18MSUB=RO_RO4350B1
MOPEN$ID=TL33MSUB=RO_RO4350B1
MSRSTUB2ID=ST3Ro=Ro_stub mmWg=Wg_stub mmW=W_TLStub mmTheta=Theta_stub DegMSUB=RO_RO4350B1
12
3
MTEE$ID=TL16MSUB=RO_RO4350B1
1 2
3
MTEE$ID=TL24MSUB=RO_RO4350B1
1
2
3MTEE$ID=TL32MSUB=RO_RO4350B1
1 2
1 2
GPROBE2ID=GP2
1
2
3
4
MCROSSX$ID=MX1MSUB=RO_RO4350B1
PORTP=2Z=50 Ohm
W_DoubleStub=0.948360421001726L_DoubleStub=3.48189099549556
Input Matching Network
Output Matching Network
• Some changes were made after using real transmission lines
0 1.0
1.0
-1.0
10.0
5.0
2.0
3.0
4.0
0.2
0.4
0.6
0.8
Matching Networks ComparisonSwp Max
10
Swp Min-30
Mag 0.4531Ang 148.7 Deg
Mag 0.4151Ang 152 Deg
Mag 0.5691Ang -159.8 Deg
Mag 0.7377Ang -162.5 Deg
rhoS IDEAL
rhoS REAL
Input Stability Circle
rhoL IDEAL
rhoL REAL
Output Stability Circle
![Page 34: Design Basics on Power Amplifiers](https://reader034.fdocuments.us/reader034/viewer/2022042520/58a39f191a28abb1348b6807/html5/thumbnails/34.jpg)
Final design
2. Design
34
• RO4350B substrate with low thickness to take care about termal conductivity
50 2050 4050 6050 8050 10000Frequency (MHz)
Rollet's Condition in Final Design
0
5
10
15
20
0
0.5
1
1.5
2K (L)
B1 (R)
2000 2200 2400 2600 2800 3000
Frequency (MHz)
S-Parameters of the PA
-35
-30
-25
-20
-15
-10
-5
0
-5
-1.429
2.143
5.714
9.286
12.86
16.43
20
2450 MHz
2506 MHz-10 dB
2392 MHz-10 dB
2450 MHz-27.67 dB
2450 MHz15 dB
S11(dB) (L)
S21(dB) (R)
S12(dB) (L)
S22(dB) (L)
0 10 20 30 40Power (dBm)
Comparison
0
5
10
15
20
Gai
n (d
B)
10
20
30
40
50
Pou
t (d
Bm
)
0
20
40
60
80P
AE
(%)
26.16 dBm
26.16 dBm40.16 dBm
26.16 dBm53.3
26.16 dBm14 dB
PAE After
PAE Before
Pout After (dBm)
Pout Before (dBm)
Gain(dB) After
Gain(dB) Before
![Page 35: Design Basics on Power Amplifiers](https://reader034.fdocuments.us/reader034/viewer/2022042520/58a39f191a28abb1348b6807/html5/thumbnails/35.jpg)
2. Design
35
• RO4350B substrate with low thickness to take care about termal conductivity
Final design
RF OUTRF IN
![Page 36: Design Basics on Power Amplifiers](https://reader034.fdocuments.us/reader034/viewer/2022042520/58a39f191a28abb1348b6807/html5/thumbnails/36.jpg)
Outline1. Introduction2. Design3. Manufacturing4. Results5. Conclusions and Future work
![Page 37: Design Basics on Power Amplifiers](https://reader034.fdocuments.us/reader034/viewer/2022042520/58a39f191a28abb1348b6807/html5/thumbnails/37.jpg)
Heat Sink Selection
3. Manufacturing
37
𝜃 𝑗𝑎=𝜃 𝑗𝑐+𝜃𝑐𝑠+𝜃𝑠𝑎=𝑇 𝑗−𝑇 𝑎
𝑄 =14.8192º𝐶 /𝑊
𝜃𝑐𝑠=𝜌 ·𝑡𝐴 =0.5 º𝐶 /𝑊 (𝑇𝑦𝑝 .𝑖𝑛 h𝑡 𝑒𝑟𝑚𝑎𝑙 𝑐𝑜𝑚𝑝𝑜𝑢𝑛𝑑)
𝜃𝑠𝑎=𝑇 𝑗−𝑇𝑎
𝑄 −(𝜃 jc+𝜃𝑐𝑠)
𝜃 𝑗 𝑐=8.0 º𝐶 /𝑊 (𝑇𝑟𝑎𝑛𝑠𝑖𝑠𝑡𝑜𝑟 h𝐷𝑎𝑡𝑎𝑠 𝑒𝑒𝑡)
𝜃𝑠𝑎𝑀𝑎𝑥=6.31921 º𝐶 /𝑊
![Page 38: Design Basics on Power Amplifiers](https://reader034.fdocuments.us/reader034/viewer/2022042520/58a39f191a28abb1348b6807/html5/thumbnails/38.jpg)
Heat Sink Selection
3. Manufacturing
38
𝜃¿ ¿
![Page 39: Design Basics on Power Amplifiers](https://reader034.fdocuments.us/reader034/viewer/2022042520/58a39f191a28abb1348b6807/html5/thumbnails/39.jpg)
Assembly
3. Manufacturing
39
![Page 40: Design Basics on Power Amplifiers](https://reader034.fdocuments.us/reader034/viewer/2022042520/58a39f191a28abb1348b6807/html5/thumbnails/40.jpg)
Assembly
3. Manufacturing
40
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Outline1. Introduction2. Design3. Manufacturing4. Results5. Conclusions and Future work
![Page 42: Design Basics on Power Amplifiers](https://reader034.fdocuments.us/reader034/viewer/2022042520/58a39f191a28abb1348b6807/html5/thumbnails/42.jpg)
4. Results
42
![Page 43: Design Basics on Power Amplifiers](https://reader034.fdocuments.us/reader034/viewer/2022042520/58a39f191a28abb1348b6807/html5/thumbnails/43.jpg)
4. Results
43
2000 2200 2400 2600 2800 3000
Frequency (MHz)
S-Parameters of the PA
-35
-30
-25
-20
-15
-10
-5
0
-5
-1.429
2.143
5.714
9.286
12.86
16.43
20
2195 MHz 2450 MHz
Simulated S11(dB) (L)
Simulated S21(dB) (R)
Simulated S12(dB) (L)
Simulated S22(dB) (L)
Measured S11(dB) (L)
Measured S21(dB) (R)
Measured S12(dB) (L)
Measured S22(dB) (L)
• To correct the frequency shift:
![Page 44: Design Basics on Power Amplifiers](https://reader034.fdocuments.us/reader034/viewer/2022042520/58a39f191a28abb1348b6807/html5/thumbnails/44.jpg)
4. Results Inconvenients and unexpected stuff
After 4 minutes working, the transistor was BURNT!
Potential causes:
a. Thermal compound
b. Q-Point too close to the maximum dissipation curve
c. Testing with LOW Input Power. LOW PAE. HIGH dissipation
d. When frequency shift occurs, at 2.45GHz we have a totally different behaviour
• IT HAS NOT BEEN POSSIBLE TO MEASURE ANYMORE
44
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Outline1. Introduction2. Design3. Manufacturing4. Results5. Conclusions and Future work
![Page 46: Design Basics on Power Amplifiers](https://reader034.fdocuments.us/reader034/viewer/2022042520/58a39f191a28abb1348b6807/html5/thumbnails/46.jpg)
Conclusions
• Initial thermal analysis is critical
• Project with high didactic potential
Future Work
• Fix the overheating issue
• Design other amplifier classes such as AB and B to be
able to compare its performance, efficiency and so
forth
5. Conclusions and Future Work
46
![Page 47: Design Basics on Power Amplifiers](https://reader034.fdocuments.us/reader034/viewer/2022042520/58a39f191a28abb1348b6807/html5/thumbnails/47.jpg)
Thanks!
Any Question?