Design-aware Mask Inspection€¦ · Modeling Inspection Tool Defects # False Defects = Extrusion...
Transcript of Design-aware Mask Inspection€¦ · Modeling Inspection Tool Defects # False Defects = Extrusion...
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Design-aware Mask Inspection
Abde Ali Kagalwalla1, Puneet Gupta1, Chris Progler2 and Steve McDonald2
1{abdeali,puneet}@ucla.edu
Electrical Engr., UCLA2Photronics Inc.
www.nanocad.ee.ucla.edu1
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Outline
• Motivation
• Proposed design-aware inspection
• Results
• Conclusion & Future Work
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Motivation
Mask cost increase with technology
Source: ITRS 2009
Mask manufacturing cost budget
Source: Dai Nippon Photomask at SPIE 2008
• Decreasing feature size & RETs � mask inspection challenging
• Reducing mask cost critical for low volume SoCs
• Mask cost expected to be worse for future patterning(EUV,
nano-imprint)
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Mask Inspection Primer
Defect
Review
Repair/Replace
No
Defects
Mask Inspection ToolAIMS Emulator
• Defect review often manual � Slow
• AIMS emulation ‘gold standard’ but tedious
• Defect repair/replacement expensive
Inspection ToolAIMS Emulator
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Mask Inspection Tool
•Gray-scale image comparison
•Intensity difference > threshold � Defect
•Allows adjustable threshold
• More common used term is sensitivity(s)
• Can choose from different pixel sizes(p)• Can choose from different pixel sizes(p)
• Inspection resolution = K(p/s)
•First pass yield
-Masks that pass inspection without repair/replacement
-Key metric for cost reduction
•Controlling defect count of tool critical for turnaround time
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Why Design-Aware Inspection?
Defects Reported by
Inspection Tool
False Defects Real Defects
Non-printable Printable
Non-critical Critical
Design-awareness to minimize false + nuisance defects
reported without missing critical defects
Nuisance
Defects
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Modeling Inspection Tool Defects
# False Defects =
Extrusion
Pinhole
Intrusion
Pindot
Defect Types:•CD defects: Intrusion, extrusion
•Contamination: Pinhole, pindot
# False Defects =
• Models imaging system noise
• Typically models photon limited noise
# Nuisance Defects =
• Derived assuming negative binomial defect
distribution
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Intrusion
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Outline
• Motivation
• Proposed design-aware inspection
• Results
• Conclusion & Future Work
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Overview of our work
Post-OPC Layout
Non-functional
Feature FinderLocate redundant vias &
dummy fill
Criticality Assigner
Pixel size + sensitivity
Partitioner
MEEF
Timing Info.For each feature, assign
maximum defect size that
does not cause design to fail
oNo critical defect missed
oMinimize false+nuisance
defects
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Proposed Design-aware Inspection Flow
Defect
Review
Repair/Replace
No
Defects
Mask Inspection Tool
PartitionerCriticality
Assigner
Design
Information
Mask Inspection ToolAIMS Emulator
Non-
functional
feature Finder
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Non-functional Feature Finder: Overview
• Assume that layout has only rectilinear shapes
Post-OPC LayoutRedundancy
Finder
Redundant
Vias
Dummy Fill
• Assume that layout has only rectilinear shapes
- Valid for all digital designs
• Only floating fill with no via-connected fill considered
-Consistent with most fill insertion tools
• Approach extensible to identifying other non-
functional features like spare cells, non-tree routes
and assists
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Non-functional Feature Finder: Algorithm Steps
Sample Layout
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Non-functional Feature Finder: Algorithm Steps
Fracture polygons
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Non-functional Feature Finder: Algorithm Steps
Scan-line for graph construction
Segment + interval trees to store scan-line events
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Non-functional Feature Finder: Algorithm Steps
Merge Neighborhood Graph
Same color neighbor vertices merged
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Non-functional Feature Finder: Algorithm Steps
Analyze Merged Neighborhood Graph
Cycles � Redundant vias
Isolated vertices � Floating fill
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Non-functional Feature Finder: Algorithm Summary
• Algorithm steps:
• Fracture shapes
• Neighborhood graph construction
• Vertex merging• Vertex merging
• Cycle and isolated vertex finding
• Scan-line based graph construction time critical
step
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Runtime Reduction: Shape Simplification
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Runtime Reduction: Scan-line speedup
• Estimate routing direction
-Reduces average size of segment+interval trees
• Use separate interval+segment trees for each metal+via layer set
- Smaller tree size
- Easy to parallelize
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Poly Layer Assignment
W
Extrusion
Pinhole
PS• Timing slack � Max.
tolerable defect size
• Assume a fixed finite
number K(=10) of
defects per path
L
Pinhole
Intrusion
Pindot
Assumption: Pinholes have no design impact
defects per path
• Account for width
/spacing to prevent
opens/shorts
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Metal/Via Layer Assignment
•Require only post-OPC layout for assignment!!
Metal Layer
- Dummy features assigned larger minimum defect size
Via Layer
- Even smallest pinhole can cause short
- Non-dummy metal intersect regions- Non-dummy metal intersect regions
- Redundant vias assigned higher defect size
Pinhole
IntrusionExtrusion
Pindot
Metal Layer Via Layer21
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Criticality Assignment
Criticality
Assigner
Timing Slack
MEEF
Design Info.
d1 d2 d3
d4
d5
d6d7
d8
d10
d11d13Design Info. d9d12
• CD (extrusion/intrusion) and contamination (pinhole/pindot)
defects separately considered
-Inspection tools have different sensitivities for them
• Assumptions:
- Only binary, square defects considered
- MEEF=1 since modern Inspection tools adapt to it
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Partitioning
d1 d2 d3
d4
d5
d6d7
d8
d9
d10
d11
d12
d13
Partitioner
d1 d2 d3
d4
d5
d6d7
d8
d9
d10
d11
d12
d13
d9d12 d9d12
Goal: Partition with each region assigned a pixel size, sensitivity
Constraints:
1. CD tolerance of partition > Min. detectable defect size = K(p/s)
- Ensuring no critical defects missed
2. Min. width/height of each partition > Lmin
- Inspection tool requirement
Cost Function: #False Defects + γ*#Real Defects
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Partitioning Algorithm
• Scan-line based heuristic
- Move vertical and horizontal lines across design
- Max. tolerable defect of partition(p/s) � try all discrete p
values and pick minimum cost value
- Moving distance of Lmin to meet width constraint
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Outline
• Motivation
• Proposed design-aware inspection
• Results
• Conclusion & Future Work
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Experimental Setup• All implementation done in C++ using OpenAccess API
• Test cases taken from opencores.org
- SP&R � Cadence RC/Encounter + 45nm Nangate
- OPC � Mentor Calibre
- DRs � 45nm Free PDK
• Defect models fitted using commercial maskshop data• Defect models fitted using commercial maskshop data
• 800 reticles, 8000-15000mm2
•Pixel sizes: 72nm and 90nm, Sensitivity:0-100
• Lmin = 2.0um (wafer scale)
Design Name # Gates Area (um2)
Aes_cipher(8-metal) 15467 102494
Mips(6-metal) 11577 59461
Nova(6-metal) 43156 268594
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Experimental Results: Non-functional Feature
Design #Double #Dummy Runtime Memory
•Results verified using DEF file of designs
- Almost 100% accuracy for both dummy fill and redundant
vias
1.20E+07
1.40E+07#Rectangles before shape simplification
Design #Double
Vias
#Dummy
Fill
Runtime
(min)
Memory
(MB)
Aes_
Cipher
131464 97772 8 910
Mips 44004 67341 5 1190
Nova 209623 303792 79 4814
0.00E+00
2.00E+06
4.00E+06
6.00E+06
8.00E+06
1.00E+07
AES_CIPHER MIPS NOVA
#Rectangles after shape simplification
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Experimental Results: Partitioning• Average false defect reduction over two designs (MIPS and NOVA)
- Via layer: Most improvement � redundant vias
- Higher metal layers: Zero improvement � Less defects
• Substantial improvement in defect review time
0%
20%
40%
60%
80%
100%
Poly M1 M2 M3 M4 M5 M6 V1 V2 V3 V4 V5
Percentage Reduction in False Defects
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Experimental Results: Nuisance defect reduction
60%First Pass Yield Mean+Sigma
• Higher via, metal layers show substantial nuisance defect
improvement
• For first pass yield, Monte Carlo simulation with 7-150nm defects
distributed on the partitioned reticle area
90%Nuisance Defects Reduction
0%
10%
20%
30%
40%
50%
Poly M1 M2 M3 M4 M5 M6 V1 V2 V3 V4 V5
First Pass Yield
Mean+3 Sigma
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
Poly M2 M4 M6 V2 V4
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Outline
• Motivation
• Proposed design-aware inspection
• Results
• Conclusion & Future Work
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Conclusion
• Proposed a comprehensive design-aware mask inspection
methodology:
1. Identified non-critical features with full
accuracy in post-OPC layout
2. Method for evaluating criticality of shapes using
timing slack, non-critical info and design rulestiming slack, non-critical info and design rules
3. Partitioning algorithm to inspect different regions
with different pixel size and sensitivity
• Up to 4X reduction in false defects with up to 55%
improvement in first pass yield achieved by design-aware
inspection
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Future Work
• Current approach assumes mask shop has
complete mask set of design
- Techniques to work with limited design data
• Better false defect model
• Study tradeoffs of tuning only sensitivity versus
sensitivity + pixel size
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