Department of Science and Technology Institutionen för teknik och naturvetenskap Linköping University Linköpings universitet

gnipökrroN 47 106 nedewS ,gnipökrroN 47 106-ES

LiU-ITN-TEK-A--18/022--SE

Design and verification ofautomotive power supply

Johan Andersson

Adam Schelander

2018-06-11

LiU-ITN-TEK-A--18/022--SE

Design and verification ofautomotive power supply

Examensarbete utfört i Elektroteknikvid Tekniska högskolan vid

Linköpings universitet

Johan AnderssonAdam Schelander

Handledare Jonte BernhardExaminator Magnus Karlsson

Norrköping 2018-06-11

Upphovsrätt

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© Johan Andersson, Adam Schelander

Abstract

In the current and next generation automotive telematic platforms, high de-mands are put on high eiciency power supplies. This thesis investigatesdiferent switch mode power converter solutions that operates with high ei-ciency for both low and high power loads. A market survey was conductedalongside meetings with ACTIA Nordic and their subcontractors. Three so-lutions from the market survey were selected for further investigation. Onesolution from the investigation was selected and implemented as a demonstra-tion platform for further testing. The result shows a full test sequence for thedesigned power supply solution.

PrefaceThanks to Tomas Westlund at ACTIA Nordic AB in Linköping and Per Järmark atÅF AB in Linköping for providing the project and support. Special thanks to JonasPersson and the hardware group at ACTIA Nordic AB for supervision and guidance.

Thanks to Magnus Karlsson at the department of science and technology at LinköpingUniversity for guidance and support during this MSc thesis project.

Thanks to all alicted subcontractors of ACTIA Nordic for providing material andsupport.

i

AcronymsBCM Boundary Conductive Mode. 9, 42

BOM Bill of Materials. 8, 31

CCM Continuous Conductive Mode. 9, 11, 12, 42

CISPR22 Comite International Special des Perturbations Radioelectriques - Inter-national special Committee on Radio Interference. 20, 25, 57, 60–62, 75, 77,78, 80, 81, 85

DCM Discontinuous Conductive Mode. 9–12, 41, 42

DHU Data Handling Unit. 1, 2, 5, 81

DUT Device Under Test. 63, 77

EMC Electromagnetic Compatibility. 1, 2, 29, 59, 60, 80, 81, 85

EMI Electromagnetic Interference. 8, 20–22, 24, 25, 29, 45, 46, 52, 53, 59, 81

ESD Electrostatic Discharge. 30, 83

ESL Equivalent Series Inductance. 21

ESR Equivalent Series Resistance. 14, 16, 17, 27, 44

GNSS Global Navigation Satellite System. 1

IC Integrated Circuit. 8, 13, 21, 30, 31, 36, 46, 48, 79, 85

IEC International Electrotechnical Commission. 1

ITE Information Technology Equipment. 60

LDO Low-Dropout regulator. 32–34, 37, 79, 82

LISN Line Impedance Stabilization Network. 60, 75

LP Low-Pass. 19

MOSFET Metal Oxide Semiconductor Field Efect Transistor. vi, 5, 8, 9, 12, 13,19–24, 34, 37, 46, 47, 51, 53, 76, 78, 80

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PCB Printed Circuit Board. 1–3, 8, 31, 43, 52, 53, 55, 85

PFM Pulse Frequency Modulation. 10–12, 35, 36, 71, 79

PWM Pulse Width Modulation. 10–13, 71

QFN Quad Flat pack No lead. 23

QP Quasi-Peak. 60

RMS Root Mean Square. 33

RPP Reverse Polarity Protection. x, 19, 37, 50, 67, 78, 82

SMPS Switch Mode Power Supply. 5, 15, 24

TSSOP Thin Shrink Small Outline Package. 23

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Contents

1 Introduction 11.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Problem Formulations . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.5 Materials and Sources . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.5.1 Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.2 Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Theoretical Background 52.1 DC/DC Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1.1 Integrated Buck Converter . . . . . . . . . . . . . . . . . . . . 82.1.2 Buck Controller with External Switches . . . . . . . . . . . . 82.1.3 Flyback Converter . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Control and Stability of the DC/DC Converter . . . . . . . . . . . . 92.2.1 Boundary Conduction Mode . . . . . . . . . . . . . . . . . . . 92.2.2 Switch Control Signal . . . . . . . . . . . . . . . . . . . . . . 102.2.3 Feedback Control . . . . . . . . . . . . . . . . . . . . . . . . . 122.2.4 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 Reverse Polarity and Over Voltage Protection . . . . . . . . . . . . . 192.4 EMC and EMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.1 Reducing Radiated EMI in Buck Converter . . . . . . . . . . 202.4.2 Switch Node Ringing . . . . . . . . . . . . . . . . . . . . . . . 212.4.3 Conducted EMI . . . . . . . . . . . . . . . . . . . . . . . . . . 242.4.4 Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3 Implementation 293.1 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.2 Power Converter Market Survey . . . . . . . . . . . . . . . . . . . . . 303.3 Choice of Power Converter . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3.1 LDO pre-stage . . . . . . . . . . . . . . . . . . . . . . . . . . 333.4 System Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.4.1 Layout of LTC7801 . . . . . . . . . . . . . . . . . . . . . . . . 353.4.2 Layout of MAX17506 with LDO . . . . . . . . . . . . . . . . 363.4.3 Layout of Flyback Converter . . . . . . . . . . . . . . . . . . 393.4.4 Choice of Converter Layout . . . . . . . . . . . . . . . . . . . 41

3.5 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413.5.1 The Output Inductor . . . . . . . . . . . . . . . . . . . . . . . 413.5.2 Output Capacitors . . . . . . . . . . . . . . . . . . . . . . . . 44

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3.5.3 Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.5.4 Switching MOSFETS . . . . . . . . . . . . . . . . . . . . . . 463.5.5 Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . 483.5.6 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . 503.5.7 Reducing EMI in Buck Converter . . . . . . . . . . . . . . . . 523.5.8 Circuit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . 533.5.9 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4 Test and Veriication 574.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.1.1 Eiciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574.1.2 Switch Node Ringing . . . . . . . . . . . . . . . . . . . . . . . 574.1.3 Startup Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . 574.1.4 Turn On/Of Voltages and Times . . . . . . . . . . . . . . . . 574.1.5 Output Voltage Ripple and Noise . . . . . . . . . . . . . . . . 584.1.6 Output Line and Load Regulation . . . . . . . . . . . . . . . 584.1.7 Output Transient Response . . . . . . . . . . . . . . . . . . . 594.1.8 Temperature Evaluation . . . . . . . . . . . . . . . . . . . . . 59

4.2 Feedback Loop Stability Testing . . . . . . . . . . . . . . . . . . . . . 594.3 EMC Testing and Regulations . . . . . . . . . . . . . . . . . . . . . . 59

4.3.1 Conducted Emissions . . . . . . . . . . . . . . . . . . . . . . . 604.3.2 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . 62

5 Results 655.1 Results from Test and Veriication . . . . . . . . . . . . . . . . . . . . 66

5.1.1 Eiciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665.1.2 Line and Load Regulation . . . . . . . . . . . . . . . . . . . . 685.1.3 Switch Node Ringing . . . . . . . . . . . . . . . . . . . . . . . 685.1.4 Turn On and Of Voltage and Time . . . . . . . . . . . . . . . 705.1.5 Output Voltage Ripple and Noise . . . . . . . . . . . . . . . . 715.1.6 Output Transient Response . . . . . . . . . . . . . . . . . . . 725.1.7 Feedback Loop Stability . . . . . . . . . . . . . . . . . . . . . 735.1.8 Conducted Emissions . . . . . . . . . . . . . . . . . . . . . . . 755.1.9 Radiated Emission . . . . . . . . . . . . . . . . . . . . . . . . 775.1.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6 Discussion 796.1 Market Survey Discussion . . . . . . . . . . . . . . . . . . . . . . . . 79

6.1.1 Output Inductor Market Survey Discussion . . . . . . . . . . 796.1.2 Metal Oxide Semiconductor Field Efect Transistor (MOS-

FET) Market Survey Discussion . . . . . . . . . . . . . . . . . 806.2 System Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.2.1 EMC Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 81

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6.2.2 Stability and Loop Response Discussion . . . . . . . . . . . . 826.2.3 Result Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 82

7 Conclusion 85

Appendices A-1A Switch Node Ringing Measurements . . . . . . . . . . . . . . . . . . A-1B Output Voltage Ripple Measurements . . . . . . . . . . . . . . . . . . B-1C Radiated Emission Measurements . . . . . . . . . . . . . . . . . . . . C-1D Setup for Conducted Emission Measurements . . . . . . . . . . . . . D-1E Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1

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List of Figures1 Simpliied buck converter model . . . . . . . . . . . . . . . . . . . . . 52 Buck converter waveforms in CCM . . . . . . . . . . . . . . . . . . . 63 Output ripple of a buck converter . . . . . . . . . . . . . . . . . . . . 74 Integrated buck converter . . . . . . . . . . . . . . . . . . . . . . . . 85 Disctrete buck controller with external MOSFET´s . . . . . . . . . . 86 Buck converter characteristics keeping Vo constant . . . . . . . . . . . 107 PWM generator signals . . . . . . . . . . . . . . . . . . . . . . . . . . 118 PFM generator signals . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Voltage mode control feedback loop . . . . . . . . . . . . . . . . . . . 1210 Current mode control feedback loop . . . . . . . . . . . . . . . . . . . 1311 Hysteresis mode control feedback loop . . . . . . . . . . . . . . . . . 1412 Converter feedback loop gain without compensation network . . . . . 1513 Closed loop system schematic of buck converter . . . . . . . . . . . . 1614 Open loop buck converter system . . . . . . . . . . . . . . . . . . . . 1715 Type II feedback compensation . . . . . . . . . . . . . . . . . . . . . 1816 Type II compensation gain and phase . . . . . . . . . . . . . . . . . . 1817 Buck converter current loops . . . . . . . . . . . . . . . . . . . . . . . 2018 Frequency spectrum of switch pulses . . . . . . . . . . . . . . . . . . 2119 Switch node ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2220 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2321 QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2322 RC Snubber connected to switch node . . . . . . . . . . . . . . . . . 2323 Conductors with both common and diferential-mode currents . . . . 2424 Undamped LC-ilter . . . . . . . . . . . . . . . . . . . . . . . . . . . 2525 Gain of LC-ilter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2626 Damped LC-ilter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2727 Input current waveform of a buck converter . . . . . . . . . . . . . . 3428 Schematic for the LTC7801 solution . . . . . . . . . . . . . . . . . . . 3529 Schematic for MAX17506 . . . . . . . . . . . . . . . . . . . . . . . . 3630 Schematic for LT4356-2 . . . . . . . . . . . . . . . . . . . . . . . . . 3731 Integrated buck converter solution with LDO pre-stage . . . . . . . . 3832 Schematic of Flyback solution . . . . . . . . . . . . . . . . . . . . . . 3933 Eiciency curve lyback converter . . . . . . . . . . . . . . . . . . . . 4034 Eiciency at low current of lyback converter . . . . . . . . . . . . . . 4035 Output current waveform at diferent loads . . . . . . . . . . . . . . . 4236 BCM current level at diferent output inductances . . . . . . . . . . . 4237 Output voltage ripple at diferent capacitances . . . . . . . . . . . . . 4438 Input ilter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4539 Input ilter simulation LT Spice . . . . . . . . . . . . . . . . . . . . . 4640 Power Cad setup for loop compensation . . . . . . . . . . . . . . . . 48

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41 Loop gain and phase for the selected compensation components . . . 4942 Compensation network schematic values . . . . . . . . . . . . . . . . 5043 Topologies for reverse polarity protection; (a) Schottky-diode Reverse

Polarity Protection (RPP), (b) PMOS RPP and (c) NMOS RPP . . 5044 Power dissipation in diferent RPP solutions . . . . . . . . . . . . . . 5145 Main current loops on PCB . . . . . . . . . . . . . . . . . . . . . . . 5246 Secondary current loop PCB . . . . . . . . . . . . . . . . . . . . . . . 5347 Buck controller solution with RPP and input ilter . . . . . . . . . . 5448 PCB layer stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5549 PCB Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5650 PCB Signal Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5651 QP-detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6152 CISPR22 Limits for conducted emissions [24] . . . . . . . . . . . . . 6153 CISPR22 Limits for radiated emissions [24] . . . . . . . . . . . . . . . 6254 CISPR22 Measurement setup for radiated emissions [24] . . . . . . . 6355 PCB 3D model of the buck converter test board viewed from the side 6556 PCB 3D model of the buck converter circuit . . . . . . . . . . . . . . 6557 Photography of the designed power supply circuit . . . . . . . . . . . 6658 LTC7801 measured eiciency . . . . . . . . . . . . . . . . . . . . . . 6759 LTC7801 modiied eiciency plot, No RPP . . . . . . . . . . . . . . . 6760 Switch node ringing at 12 V input voltage . . . . . . . . . . . . . . . 6961 Switch node ringing at 48 V input voltage . . . . . . . . . . . . . . . 6962 Turn on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7063 Turn of time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7164 Output voltage ripple with 48 V input voltage in PWM mode . . . . 7165 Output voltage ripple with 48 V input voltage in PFM mode . . . . . 7266 Output transient response, rising edge . . . . . . . . . . . . . . . . . 7367 Output transient response, falling edge . . . . . . . . . . . . . . . . . 7368 Measured closed loop gain/phase using Bode 100 . . . . . . . . . . . 7469 Conducted EMI result for 1.7A PWM mode operation . . . . . . . . 7570 Conducted EMI result with two added capacitors . . . . . . . . . . . 7671 Conducted EMI result with added gate resistor . . . . . . . . . . . . 7672 Radiated emission with antenna aligned vertically . . . . . . . . . . . 7773 Radiated emission with antenna aligned horizontally . . . . . . . . . 77A.1 Switch node ringing 12 V input voltage, 3.9 Ω top gate resistor . . . . A-1A.2 Switch node ringing 48 V input voltage, 3.9 Ω top gate resistor . . . . A-1A.3 Switch node ringing 12 V input voltage, 2 Ω boot strap resistor . . . A-2A.4 Switch node ringing 48 V input voltage, 2 Ω boot strap resistor . . . A-2A.5 Switch node ringing 12 V input voltage, 390 pF, 1 Ω snubber . . . . . A-3B.1 Output voltage ripple at 12 V input voltage and 10 mA output currentB-1B.2 Output voltage ripple at 12 V input voltage and 400 mA output currentB-1B.3 Output voltage ripple at 12 V input voltage and 4 A output current . B-2

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B.4 Output voltage ripple at 24 V input voltage and 10 mA output currentB-2B.5 Output voltage ripple at 24 V input voltage and 400 mA output currentB-3B.6 Output voltage ripple at 24 V input voltage and 4 A output current . B-3B.7 Output voltage ripple at 48 V input voltage and 400 mA output currentB-4B.8 Output voltage ripple at 48 V input voltage and 4 A output current . B-4C.1 Radiated emission with antenna aligned vertically, 48 V input voltage C-1C.2 Radiated emission with antenna aligned vertically, 60 V input voltage C-1D.1 Setup for Conducted EMI measurements . . . . . . . . . . . . . . . . D-1E.1 Bill of material for the LTC7801 design . . . . . . . . . . . . . . . . . E-1

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List of Tables1 System requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Customer requirements - electrical components . . . . . . . . . . . . 303 Buck converter market survey . . . . . . . . . . . . . . . . . . . . . . 324 LDO calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Output Inductors 8.2 µH market survey . . . . . . . . . . . . . . . . 436 NMOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 Limits for conducted disturbance at the mains ports of class B ITE . 608 Limits for radiated disturbance of class B ITE at measuring distance

of 10 m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 measured line regulation . . . . . . . . . . . . . . . . . . . . . . . . . 6810 Measured load regulation . . . . . . . . . . . . . . . . . . . . . . . . . 6811 Reduction of switch node ringing . . . . . . . . . . . . . . . . . . . . 7012 Output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . 7213 Feedback loop stability testing . . . . . . . . . . . . . . . . . . . . . . 7414 Speciication buck converter design . . . . . . . . . . . . . . . . . . . 78

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1 IntroductionACTIA Nordic AB is a company that develops and designs products and solutionsfor the automotive industry. A customer of ACTIA wants to collect and monitordata from their warehouse trucks. ACTIA ofers a solution, called Data HandlingUnit (DHU), that collects data from all the sensors mounted on the warehouse trucksand transmits it wireless to a monitoring system.

The DHU is a ”black box” solution connected to the warehouse trucks for datahandling. It communicates with a cloudbased telematic server through 4G. In addi-tion the DHU receives Global Navigation Satellite System (GNSS) signals to trackthe truck position.

1.1 PurposeIn the current and next generation telematics platforms, high demands are put onhigh eiciency power supplies, which must operate at a higher eiciency than pre-vious generations and must be accommodated on smaller Printed Circuit Board(PCB) layout.

This thesis will include the deinition, design and validation of the main voltageconverter of the DHU system. The converter has to be able to handle tough envi-ronments such as voltage pulses, voltage surges and Electromagnetic Compatibility(EMC) requirements.

The design will include electrical schematics and PCB layout. Validation includeselectrical and stability testing at ACTIA and EMC testing at external part.

The assignment also includes communication with ACTIA’s subcontractors, internalpurchasing organization and other hardware designers.

1.2 Problem FormulationsThe main questions of this master thesis includes both a theoretical part and a designand validation part. The main issues of the thesis are compiled in the followingresearch questions:

• How should the design be realized in order to meet the requirements.The power supply has to meet the requirements from both the customer andACTIA, but also the International Electrotechnical Commission (IEC) stan-dards.

• How to minimize the EMC-footprint without the use of EMC shields

1

The power supply is a part of telematic and automotive equipment whichincludes hard regulations in the ield of EMC.

• How to maximize the eiciency of the power supply.The product is fed by the warehouse truck battery and therefore has to havehigh eiciency. Being able to deliver high eiciency even at low power outtakeis of great importance.

• How to minimize the size of the PCB layout.The size of the PCB layout for the power supply is important to give space tothe rest of the system because of the size limitations required by the customer.

1.3 LimitationsThe power supply in this thesis is limited to the main converter which converts thebattery voltage to the highest voltage used by other circuits in the DHU. The powersupply is complemented by ilters and protection circuits to ensure safe operation ofthe system. This thesis includes background theory, design and testing of DC/DCbuck converters.

1.4 Outline• 1. Introduction

Describes the purpose of this thesis along with problem formulation and limi-tations.

• 2. Theoretical BackgroundProvides the necessary theory needed for the implementation. The theory islimited to theory speciic for this thesis.

• 3. ImplementationThe implementation chronologically describes the worklow starting with amarket survey, followed by choice of components, schematic, layouts and PCBdesign.

• 4. Test and VeriicationProvides the sequence of tests performed on the system and the purpose ofeach test. The test sequence contains electrical, stability and EMC testing.

• 5. ResultShows the inal system schematic and PCB. All the results from the systemtesting is shown in this chapter.

2

• 6. DiscussionThis chapter presents a discussion with the authors thoughts about the imple-mentation process and the result of the project.

• 7. ConclusionThe conclusion chapter answers the problem formulation. This chapter con-tains conclusions about the solutions found in the market survey, the diferentdesign layouts and the manufactured design.

1.5 Materials and SourcesThe following section presents the materials and sources used in this thesis.

1.5.1 Sources

Sources used in this thesis were found using the database library at Linköping Uni-versity with databases such as IEEE Xplore: Digital Library. Other sources such asdata sheets and design recommendations were found at manufacturer websites.

1.5.2 Materials

To reach the inal design solution, evaluation kits from diferent manufacturers wereprovided. In house components at ACTIA were used to reconigure the evaluationkits. The inal design solution were manufactured to be tested.

1.5.3 Software

To draw electrical schematics and PCB netlists the software OrCad Capture CISsoftware were used [1]. The PCB layout were done using Altium Designer software[2]with imported netlists from OrCad Capture CIS. Electrical simulations were doneusing EE-Sim from Maxim Integrated [3], WEBENCH® from Texas Instruments [4],LTspice® [5] and LTpowerCAD® [6] from Analog Devices. Calculations and graphingwere done using MATLAB R2017b from MathWorks [7].

3

2 Theoretical BackgroundThe main component of the power supply is a Switch Mode Power Supply (SMPS)DC/DC buck converter [8]. It has the ability to step-down the nominal input voltagefrom the battery to an output voltage of 5 V , which is the highest voltage used inthe DHU system.

2.1 DC/DC Buck ConverterTo describe the basic function of a buck converter, a simple model with basic com-ponents is used, shown in Figure 1. The model contains a DC-voltage source, free-wheeling diode, inductor, capacitor and a resistive load. The switch in this case isin reality a MOSFET and the diode is often changed to a MOSFET with invertedcontrol signal compared to the switch. The circuit with the freewheeling diode isan asynchronous solution and the dual MOSFET solution is synchronous. Beneitswith the synchronous solution is that the voltage drop over a MOSFET is muchlower than over a diode. This leads to lower power losses and higher eiciency withthe synchronous solution at high output currents. Asynchronous converters couldhowever lead to higher eiciency than the synchronous at low currents due to powersavings without the gate driver [9].

Figure 1: Simpliied buck converter model

Figure 1 shows the current paths in the buck converter model in the cases whenthe switch is either open or closed. When the switch is closed the current lowsfrom the source to the load through the inductor. When the switch is opened thecurrent continuous to low through the load through the freewheeling diode. Thisresults in that the average output voltage is given by equation 1, where D is theswitching duty cycle and Ts is the switching period time [8].

5

Vo =1

Ts

∫ Ts

0

vo(t)dt =1

Ts

(∫ ton

0

Vindt+

∫ Ts

ton

0dt

)

=ton

TsVin = Vin ·D (1)

Figure 2 shows the waveforms of a buck converter. The current through the inductoris shown as a triangle wave due to the current inertia of the inductor. In the onstate the output voltage is given by Vo = (Vin − VL), where the inductor voltage isgiven by VL = L · di/dt. In the of state the output is disconnected from the inputvoltage source, which means that the inductor starts to discharge. The current keepslowing through the freewheeling diode and the output voltage is therefore equal tothe negative of the inductor voltage.

As seen in equation 1 the average output voltage is only dependent on the inputvoltage and the switching duty cycle and not on the inductor value. This is due tothe fact that in steady state operation the average inductor voltage is zero. Thisis shown in Figure 2, and calculated in equation 2, where the positive and negativeside areas of the inductor voltage are the same [8].

Figure 2: Buck converter waveforms in CCM

∫ Ts

0

VLdt =

∫ ton

0

VLdt+

∫ Ts

Ton

VLdt = 0 (2)

6

The values of the inductor and capacitor are still important even though they donot have an impact on the average output voltage. The values of the componentsdecides the waveform of the output voltage and how much voltage and currentripple there will be. The output current ripple of the converter is derived inequation 3.

VL = LdI

dt↔ ∆I = VL · dt

L↔ ∆I = (Vin − Vout) ·D

Lfs(3)

The output voltage ripple of the buck converter depends of the current ripplederived in equation 3. Figure 3 shows the relation between the current ripple andthe change in charge of the capacitor. The bottom graph of the igure shows theimpact the change in capacitor charge has on the output voltage ripple.

Figure 3: Output ripple of a buck converter

Equation 4 shows the relation between voltage and current ripple out of theconverter. The charge level of the output capacitor depends on the current ripplethrough the inductor as shown in Figure 3. Output voltage ripple is then given bythe change in charge divided by the capacitance, that with the help of Figure 3gives the expression in equation 4 [8].

∆Vout =∆Q

C=

1

C

1

2

∆IL2

Ts

2=

T 2s8C

Vout

L(1−D) (4)

7

2.1.1 Integrated Buck Converter

There are many diferent topologies of buck converter. One of them is called anintegrated buck converter. It has the switching MOSFET’s built into the IntegratedCircuit (IC) which reduces the number of components on the PCB. It also reducesthe layout size of the design as the MOSFET’s are among the larger componentsin the converter. Electromagnetic Interference (EMI) is also reduced by using anintegrated buck converter as the switching loop areas is reduced a lot with thebuilt in switches as well as the stray inductance in the MOSFET’s. With built inMOSFET’s the current is limited and is in most cases lower than by using externalMOSFET’s. An example of an integrated buck converter is shown in Figure 4.

Figure 4: Integrated buck converter

2.1.2 Buck Controller with External Switches

A buck controller, with the diference from the integrated converter, has the switch-ing MOSFET’s externally. This leads to increased Bill of Materials (BOM) andassembly costs. A buck controller solution however allows selection of the powertransistors. This enables the buck solution to be more lexible and allows it tohandle tougher requirements such as wide input voltage ranges and higher currents.One problem with external switches is that the current loop areas increases, whichwill be described in section 2.4.1.

Figure 5: Disctrete buck controller with external MOSFET´s

8

2.1.3 Flyback Converter

A lyback converter is working in the same way as the converter in section 2.1 withthe diference that the inductor of the converter is replaced with a transformer. Theprimary side of the transformer consists of a MOSFET driver that chops the voltageand the secondary side consists of a synchronous rectiier and/or a ilter. In this wayit is possible to electrically isolate the input from the output via the transformer.Using a transformer will however introduce higher power losses which will decreasethe eiciency of the converter [13].

2.2 Control and Stability of the DC/DC ConverterThis section is about how to control the switching duty cycle of the converter andhow to keep the switching in the stability region.

There are three diferent conduction modes of operating a DC/DC converter;Continuous Conductive Mode (CCM), Discontinuous Conductive Mode (DCM)and Boundary Conductive Mode (BCM). The mode used in section 2.1 to describethe basic functionality of the converter was the CCM. CCM is when the currenttrough the inductor never reaches zero. DCM is the mode when the currentsometime under the switching period is zero. BCM is the boundary between theother modes, this means that BCM is a continuous mode on the boundary onbecoming discontinuous [8],[10].

2.2.1 Boundary Conduction Mode

The condition for the boundary between CCM and DCM is when the averagecurrent through the inductor is equal to half the current ripple. Derived fromequation 3 gives the expression shown in equation 5.

IL =1

2∆I =

(Vin − Vo) ·D2Lfs

=TsVo

2L(1−D) (5)

This means that all currents below the half of the ripple will put the converter indiscontinuous mode. Maximum inductor current in boundary mode, at constantoutput voltage, is given when the switching duty cycle is zero. The boundary isshown in Figure 6.

9

Figure 6: Buck converter characteristics keeping Vo constant

Figure 6 shows that the low current low forces the converter to operate in DCMregion, which in some cases introduces more ripple, noise and emissions [10].

2.2.2 Switch Control Signal

There are two methods often used to produce the switch control signal to the con-verter, Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM)[12].

PWM consists of a comparator that compares the loop feedback voltage to a gen-erated sawtooth reference. If the feedback voltage is below the sawtooth voltagethe control signal turns high and vice versa. In this way the switching frequencyis constant and it is only the pulse width that is modulated. Figure 7 shows anexample of PWM with a constant output voltage.

10

Figure 7: PWM generator signals

PFM is another method to generate the control signal to the switch circuit. Thediference from PWM is that now the pulse width is kept constant and the frequencybetween pulses is modulated. Figure 8 shows the same example as Figure 7, butnow in PFM mode. Now it is the diference between the sawtooth reference andthe output voltage that decides the switching frequency. The sawtooth reference asin the examples is used in many application but can be changed to any oscillatingsignal that its the purpose.

Figure 8: PFM generator signals

In normal operation mode when the converter is operating in the CCM region thePWM method is often used. When the converter is forced into DCM, some con-verters have the ability to switch modes and start to operate with PFM in order

11

to maintain high eiciency at low current outtake. These converter changes modewhen the current through the inductor reaches zero . In this way the converter canenter a energy saving mode between the switching pulses which reduces the quies-cent current of the converter which increases the eiciency [12].

Why PWM is unable to operate at high eiciency in this region is due to switchingduty cycle reaching towards zero, which puts the output current in DCM. At to lowduty cycles the MOSFET’s wont be fast enough, which leads to operation in thelinear region. This is why some converters switch to PFM in this region, to maintainconstant pulse width and only change the frequency to keep the converter in CCM.Why PFM is not used all the time is because the output inductor and capacitancewill change characteristics as the frequency changes and the output ripple levels willbecome unreliable.

2.2.3 Feedback Control

Switching DC/DC converters uses a feedback loop in order to maintain the outputvoltage level. This control loop can be designed in three diferent ways; voltage,current or hysteresis mode [14]. Voltage division is used in all designs to changethe desired voltage output.

Voltage mode consists of an error ampliier that compares the output voltage witha programmed reference voltage. The diferential signal from the error ampliier isthen connected to a comparator that compares the voltage with an internal controlsignal, a triangle wave in the PWM case. A model of the voltage control mode isshown in Figure 9.

Figure 9: Voltage mode control feedback loop

12

Voltage control mode is an easy control method and has a high tolerance toexternal noise but it requires a complex compensation network to maintainstability [14].

Current mode is much alike the voltage mode control. Instead of comparing theerror ampliier voltage with a triangle wave in the PWM generator, it is comparedwith a current sensing circuit that converts the inductor current to voltage. Theoutput current can be measured in diferent ways by measuring the currentthrough the inductor, by measuring the resistance of the primary MOSFET or byusing a high resistive voltage divider on the output. An example of the currentmode feedback is shown in Figure 10.

Figure 10: Current mode control feedback loop

Advantages of using current control mode is that it requires a very simplecompensation network due to high stability in the feedback loop. In this mode thecompensation network is often built in to the IC. Current mode control alsoresponds faster than voltage mode to fast load transients which gives a fastervoltage regulation [14].

13

In hysteresis mode control, the output voltage is compared directly with thereference voltage in a comparator. The comparator is then connected straight tothe switch control circuit as shown in Figure 11.

Figure 11: Hysteresis mode control feedback loop

Hysteresis mode control has the fastest load transient response of the threemethods and the feedback loop is very stable and does not require a compensationnetwork. Drawbacks of the hysteresis mode control is that it requires a highEquivalent Series Resistance (ESR) output capacitor, which will generate a highoutput voltage ripple due to the high ESR [14].

14

2.2.4 Stability

In order to ensure a stable loop response, a compensation network needs to beimplemented. The purpose of a compensation network is to achieve the wantedphase and amplitude margins to get stability. For a typical SMPS, stability isbasically deined as when the phase margin is greater than 45° and the gain marginis greater than 6 dB. In other words, the overall gain of the system should cross0 dB with a slope of -20 dB/decade. Figure 12 shows the loop gain of a typicalbuck converter were it crosses 0 dB with -40 dB/decade [15]. This is not stableand a Type II compensation network is needed. There is a Type III network whichis a more complex solution and mostly used in voltage controlled mode. For thecurrent controlled buck converter, the Type II compensation network satisies therequirements regarding phase/gain margin and bandwidth.

Figure 12: Converter feedback loop gain without compensation network

The synchronous current mode controlled buck converter mainly consists of threeelements concerning compensation. The Modulator, output ilter and compensationnetwork is shown in Figure 13 [16].

15

Figure 13: Closed loop system schematic of buck converter

The modulator compares the output of the error ampliier with the reference. Theswitch node is the output of the modulator. The gain of the modulator is given byequation 6 [17], where ∆Vosc is the comparator reference voltage.

Gainmod = 20 · log(

Vin

∆Vosc

)

(6)

The output ilter consists of the main output inductor and decoupling capacitors.The input of the ilter is the switch node and it outputs the regulated output, andhas has a transfer function of a standard LC ilter shown in equation 7 [17].

GainFilter =1 + ESR · Cout

1 + s(ESR +DCR) · Cout + s2 · Cout · Lo(7)

Adding the modulator and the output ilter together results in the open loop systemshown in Figure 14. The gain of the open loop system as shown in Figure 12 withfrequency markings fp and fz corresponding to the LC double pole and ESR equalto zero [18].

16

Figure 14: Open loop buck converter system

The frequency fLC comes from the resonance frequency of the LC output ilter andfESR is related to the ESR of the output capacitor, which can be seen in equations8 and 9 [15].

fLC =1

2π√Lo · Cout

(8)

fESR =1

2π · ESR · Cout(9)

In order to achieve a stable system during input voltage luctuations and load per-turbations, the open loop needs to be closed by a compensation network. The TypeII compensation network shown in Figure 15, has the transfer function shown inequation 10 [17].

17

Figure 15: Type II feedback compensation

GainTypeII =1

R1 · C1

(

s+ 1R2·C2

)

s

(

s+ C1·C2·R2R1·C1

) (10)

Figure 16 shows the bode plot of the Type II compensation gain and phase. Thecompensation networks gives a phase boost of 90° to help countering the resonantefect at the double pole [17]. Adding the three elements together results in aclosed loop system shown in Figure 13. The compensation network inputs thebuck converter output voltage and delivers the error ampliied signal back to themodulator.

Figure 16: Type II compensation gain and phase

18

2.3 Reverse Polarity and Over Voltage ProtectionAn important aspect to take into consideration when designing a power supply cir-cuit is the ability to handle over voltage and reverse polarity voltage.

The easiest way to design a RPP circuit is by simply putting a Schottky diodein series with the power supply. This will prevent current from lowing in the re-verse direction. The downside of this solution is voltage drop over the diode innormal operation which leads to high power loss at high currents. At high powerloss the diode also intends to get very hot.

One solution that works similar to using a Schottky diode is by using a P-channelMOSFET circuit. The PMOS is simply connected with drain-source in series withthe power supply and the gate connected to the return. In this way the PMOS isalways open at normal working condition and closed at reversed polarity voltage.In this way the forward voltage drop is much lower, which leads to higher eiciencyand lower temperature evaluation. It is also possible to use a N-channel MOSFETconnected on the return path to prevent reverse polarity voltage. The downsidewith this solution is that it introduces ground shifting to the circuit, which candisturb sensitive systems like automotive telematic systems. The NMOS howeverhas a much lower drain-source resistance than a PMOS and would almost work asan ideal diode in this case.

To be able to use a NMOS in series with the positive side of the power supplythere has to be a control unit containing a charge pump to increase the gate voltageof the transistor. This coupling is called an ideal diode due to the low forward powerloss [19].

There are diferent ways to block high voltages to reach the buck converter. Aneasy way to prevent fast voltage burst is to use a Low-Pass (LP)-ilter, which willblock high frequencies. Another way is to use surge protection circuits which willeither block or short circuit over voltages.

19

2.4 EMC and EMIRegarding EMI it is crucial that the converter meets the requirements from theComite International Special des Perturbations Radioelectriques - International spe-cial Committee on Radio Interference (CISPR22) EN55022:2006 [20] to prevent itfrom interfering with other operating devices. Diferent techniques and methods canbe used to achieve a lower level of radiated and conducted emission.

2.4.1 Reducing Radiated EMI in Buck Converter

The goal of minimizing the radiated ields, is achieved by primarily reducing thehigh current loop areas A1 and A2 shown in Figure 17 [21] ,[22].These high switching current loops caused by the high and low side MOSFET’s canbe seen as one turn inductors and acts as antennas radiating electromagnetic waves[23].

Figure 17: Buck converter current loops

Equation 11 shows how the radiated ield for diferential mode currents is propor-tional to the frequency(f) squared, current loop area(A), the current(I) and thedistance from the current loop to the receiving antenna(d) [24].

|Edm| = 1.316 · 10−14 ·f 2 · A · I

d(11)

An efective and easy way to reduce EMI is by placing a bypass capacitor Cin closeto the high-side MOSFET, in order to minimize the current area. Additionally, aground plane can be added providing better return paths resulting in reduced cur-rent area. By adding a ground plane high frequency currents will induce opposing

20

currents in the ground plane, canceling the magnetic ield [23].

Another way to reduce EMI is by slowing down the rise/fall time of the high-sideMOSFET. By slowing down the rise/fall times, the higher frequency componentswill be reduced resulting in improved EMI performance. Figure 18 shows the fre-quency spectrum of the switching pulses. By increasing rise and fall times will shiftthe 1

πτRISEpoint to a lower level making the higher frequency components drop of

earlier with -40 dB/decade [21].

Figure 18: Frequency spectrum of switch pulses

Slowing down the rise/fall times can also be done by adding a resistor in series witha bootstrap capacitor that powers the gate of the high-side MOSFET. A resistorconnected to the high-side gate is also an option for slowing down the rise/fall times.However, slowing down the rise and fall times will lead to additional power loss sincethe MOSFET spends more time in the linear region. This trade of between EMI andpower loss needs to be taken into consideration if the rise time is to be modiied [25].

2.4.2 Switch Node Ringing

The second source of EMI is the switching node (SW), the connection point betweenthe inductor and the two MOSFET’s. A combination of the MOSFET’s parasiticcapacitances, the input ilter Equivalent Series Inductance (ESL) and the IC bondingwires, will cause the frequency ringing on the switching waveform [21]. Figure 19shows the high frequency ringing for the rising and falling edge which has a muchhigher frequency than the operating switching frequency [28].

21

Figure 19: Switch node ringing

When the high-side MOSFET is switched on, the parasitic capacitance of the low-side MOSFET and the parasitic inductance of the MOSFET’S switching loop willcause frequency ringing in the rising edge [26].When the high-side MOSFET switches of, the frequency ringing will be causedby its own parasitic capacitance and the low-side MOSFET’s parasitic inductancefrom source to ground [27]. The resonant frequency of the current loops is given byequation 12 [29]. Lloop is the total inductance in the current loop and Coss is thesmall signal output capacitance of the MOSFET that is in of state [11], [21].

fres =1

2π√

LloopCoss(12)

To minimize broad band EMI the resonant frequency should be as high as possible.There is multiple options on how to increase the resonant frequency. One way isto reduce the loop area, as the loop inductance can be seen as a one turn inductorthat is directly proportional to loop area. By increasing the resonant frequency theswitch node ringing can be reduced in amplitude. This is due to the rise time ofthe switching MOSFET, which is typically in the range of 1-30 ns. With the higherresonant frequency the frequency from the switch node is avoided and is therebynot ampliied. As mentioned in section 2.4.1 the rise time of the MOSFET can beincreased by applying a resistor in series with the gate pin. In this way the frequencyof the switch node ringing is reduced. This method should only be used if the res-onant frequency can not be pushed high enough as the eiciency of the converterwill be reduced with the longer rise time.

22

The choice of MOSFET’s also afects the resonant frequency as it is proportionalto the Coss capacitance in of state. The package types of the converter and MOS-FET’s has diferent designs with diferent pin conigurations which also afects thefrequency ringing. Some are using wire bond packages(Thin Shrink Small OutlinePackage (TSSOP) shown in Figure 20 and some are using lip-chip packages(QuadFlat pack No lead (QFN)) shown in Figure 21.

Figure 20: TSSOP Package Figure 21: QFN Package

The QFN package type has a better performance compared to the TSSOP typedue to the much shorter connection pads. The TSSOP has longer wire bonds andtherefore a higher per-unit-length inductance, which is desired to be minimized inorder to reduce high frequency ringing. On the other hand the TSSOP handle heatin a more eicient way than the QFN package type [21].

Another way to reduce the high frequency ringing is to use a RC snubber circuitconnected close to the switch node, shown in Figure 22 [30].

Figure 22: RC Snubber connected to switch node

The RC snubber allows for attenuation of the parasitic resonant LC circuit whichresults in lower frequency ringing. The RC snubber is able to discharge the MOSFETof its junction charge during on and of switching [21]. High frequency currents will

23

still pass through the RC snubber so leads needs to be short and placed very closeto the MOSFET. Equation 13 shows how the resistor value of the snubber dependson the parasitic inductance and capacitance, ξ is the damping factor ranging from0.5 for slight damping, to 1 for heavy damping [21].

Rs =1

2ξ

√

Lp

Cp(13)

In comparison to slowing down the top MOSFET with gate or bootstrap resistor,the snubber is the least power efective solution. The power loss of the snubber isgiven by equation 14 [32].

PLoss = Cs · V 2in · f (14)

The snubber capacitance value Cs needs to be dimensioned so that the resistor canachieve a steady resonance damping during falling and rising edge, though not toolarge since it would increase the power loss.

2.4.3 Conducted EMI

Conducted EMI originates from the switching operation of the SMPS, resulting indiscontinuous currents at the input of the DC/DC-converter. A voltage ripple whichis generated by these discontinuous currents, can travel down the conductor inter-fering and compromising other circuits in the system. In order to reduce this noisea ilter is necessary to implement at the input of the converter [24].

Figure 23: Conductors with both common and diferential-mode currents

24

Conducted EMI is divided into two sub-categories, diferential-mode and common-mode. Common-mode noise signals has typically the same phase and amplitude onboth the conductor (Line 1) and return path (Line 2) with respect to safety ground.In diferential-mode the noise signal exist between the Line 1 and Line 2. Thesediferent noises are described by equation 15 [24].

Icm =ILine1 + ILine2

2Idm =

ILine1 − ILine22

(15)

For typical non-isolated SMPS with two input lines, any current going in throughLine 1 is intended to go out on Line 2. Due to parasitics in the circuits there isunintended common mode currents that is not needed for the circuitry to work.Common-mode currents is usually very small and diferential-mode noise is there-fore the main focus when reducing conducted EMI [31]. Conducted EMI is onlydependent on current level and not voltage, so lower input voltage gives a highercurrent for same power level resulting in worse conducted EMI [31]. In order to passthe CISPR22 limits for conducted emission, an input ilter is necessary.

2.4.4 Input Filter

An input ilter is a crucial part in the buck converter design and has to be evaluatedand understood in order to pass the EMI requirements. The purpose of the ilter isto prevent electromagnetic interference on the power line caused by the switchingsource. It is also used to iler out high frequency voltages on the power line fromreaching the output [33]. In order to achieve this, a low-pass LC-ilter needs to beimplemented between the power source and input of the buck converter. Figure 24shows the schematic for an undamped LC-ilter.

Figure 24: Undamped LC-ilter

25

The ideal LC-ilter has no gain before the cutof frequency f0 and normally declineswith -40 dB/decade after f0 for a 2nd order Butterworth ilter [34]. A Chebyshev oran Elliptic ilter, ofers a steeper declination than the Butterworth ilter. The cutoffrequency is dependent on the inductance and capacitance values given by equation16 [34].

f0 =1

2π√LC

(16)

The gain of the LC-ilter has a peak at the cutof frequency which originates from thecharacteristic impedance of the ilter being ininite at the cutof frequency. This isillustrated in Figure 25 [35]. If the gain is large at the cutof frequency it could causetrouble and amplify the noise. This ampliication is not desirable, which means thatthe ilter needs attenuation at the cutof frequency.

Figure 25: Gain of LC-ilter

The amount of damping at the cutof frequency is given by the damping factor ξshown in equation 17 [35]. When ξ = 1 there is maximum damping at the cutoffrequency. As ξ then gets smaller, the gain peak increases which is shown in Figure25.

ξ =L

2 ·Rload√LC

(17)

26

Its common that the undamped ilter fails to meet the requirements regarding peakgain at the cutof frequency, which means that a damping circuit is needed. In orderto reduce the peak impedance at the cutof frequency a RC circuit is connectedin parallel to supply suicient damping to the ilter [35]. The resistor reduces thepeak impedance and the capacitor is used for reducing power dissipation in theresistor[35]. The damped LC-ilter is shown in Figure 26.

Figure 26: Damped LC-ilter

The ESR of the electrolytic capacitor Cd is usually large enough to work as thedamping resistor Rd.

27

3 ImplementationIn order to achieve an eicient power converter for the described system, a marketsurvey was conducted taking into account the requirements made on the system.The market survey was also used to get deeper knowledge of parameters that afectthe power converter such as EMI, eiciency and layout size. From the market surveymultiple designs were made and compared to each other. From the comparison, onesolution were chosen to be manufactured and fully tested.

3.1 System RequirementsThere are multiple requirements put on the design regarding voltage and currentlevels, temperature and EMC. Table 1 shows the electrical requirements put on thepower converter and Table 2 shows the general requirements on electrical compo-nents from the customer. Apart from the requirements in the tables, all the compo-nents has to be automotive classiied. This classiication contains components withhigher temperature tolerance and are more robust to better handle vibrations.

Table 1: System requirements

Parameter Speciication Conditions CommentsCurrent con-sumptionstandby

Max 5 mA At nominal supply volt-ages

Nominal sup-ply voltages

12 V, 24 V and 48 V Fluctuations 0.7 - 1.25 xnominal supply voltage

Over voltage 1.5 x nominal supplyvoltage

10 s every 2 minutes Full functionality isneeded in this region

Under voltage 0.5 x nominal supplyvoltage

50 ms

Estimated Out-put Power

>20 W At 5 V output voltageand 4 A output current

Operation tem-perature

-35 - +70 °C Ambient temperature

Minimum ei-ciency

>80 % >10 mA output current ∼ 90 % at full load

Reversed polar-ity

1.2 x nominal supplyvoltage

-60 V at 48 V supplyvoltage

Output currentripple

Table 2: Customer requirements - electrical components

Component test CommentsRadiated emis-sion

EN 55022:2006, class B 30-230MHz:30 dBµV/m 230-1000 MHz:37dBµV/m

The test component, shall be con-nected to cables with a length thatcorresponds to a real installation in atruck

Conductedemission

EN 55022:2006, class B 0.15-0.5MHz: quasi-peak 79 dBµV average66 dBµV 0.5-30 MHz: quasi-peak 73dBµV average 60 dBµV

Measurements shall be performed onthe power supply leads to the compo-nent

Radiatedimmunity

EN 61000-4-6:2006 27-1000 MHz:30V/m 1000-2700 MHz 15 V/m

The tested component, shall be con-nected to cables with a length thatcorresponds to a real installation in atruck, and at least one meter of thelength shall be exposed to the ield

Conducted im-munity

EN 61000-4-6:2009 0.15-27 MHz: 10V

Tests shall be performed on powerand signal lines separately

Fast transients EN 61000-4-44:2004 Test level 2 Tests shall be performed on powerand signal lines separately

ESD immunitypowered up

EN 61000-4-2:2009 Test level 4: ± 8kV contact discharge ± 15 kV air dis-charge

The lower test levels according to EN61000-4-2 must also be tested and ful-illed. Indirect discharges shall alsobe applied towards coupling planes(HCP and VCP).

ESD immunityunpowered

ISO 10605:2008 paragraph 9 ± 8 kVcontact discharge ± 15 kV air dis-charge

The lower test levels according to ISO10605 must also be tested and fulilled

Immunitymagnetic ield

EN 61000-4-8:2010 50 Hz: 100 A/m Applicable only to devices susceptibleto magnetic ield

3.2 Power Converter Market SurveyThe initial stage of the market survey was to compile all the requirements placedon the power converter from both ACTIA and the customer, shown in Table 1.EMC and EMI requirements from the customer were taken into account for thediferent power converter designs, sown in Table 2. The research for a compatiblepower converter was performed using the requirements parameters as inputs to theIC manufactures products. ACTIA had some initial suggestions regarding manufac-tures and power converters to investigate further. With a wide input voltage rangecombined with a high eiciency requirement for both low standby currents and highoperating currents, many of the power converters could be neglected from the earlyphase of the research. This limited the number of manufactures to a few, includingTexas Instruments, Maxim Integrated and Analog Devices. The three manufac-turer each has simulation tools for their converters which were used to simulate thecomponent values of the designs. The softwares are presented in section 1.5.3.

30

In addition to get an even clearer and better view of the power converter market,meetings were held with the diferent IC manufactures. This was done for moredetailed information about their circuits and solutions. Meetings were held withrepresentatives from Texas Instruments, Maxim Integrated and Analog Devices.

3.3 Choice of Power ConverterChoosing a suitable buck converter were done based on the market survey. Thechoice was done based on;

• BOMThe total number of components required in the design and the total cost. Thecost of the power converters presented, are taken from the distributer websitesand is not the large scale prices ofered by the distributer.

• SizeThe estimated physical size of the PCB

• EiciencyEstimated eiciency under the operating conditions given by the requirements.

• Input and output powerThat the converter is able to handle the total range of input voltage requiredto meet the speciications, or if it needs to be combined with other circuitry.It also has to meet the output power requirements of 20 W at 5 V and 4 A.

The resulting components from the market survey is shown in Table 3.

31

Table 3: Buck converter market survey

Model Vin/Iout Quiescentcurrent

Estimatedeiciency

Price Reference

LTC7801Controller

4-140 V> 5 A

40 µAshutdown =10 µA

∼ 80 % at 5 mA∼ 90 % at 10 mA> 90 % at > 10 mA

$4.46 [37]

MAX17536Integratedconverter

4.5-60 V4 A

128-168 µA ∼ 70 % at 5 mA∼ 78 % at 10 mA>85 % at > 100 mA

$2.95 [38]

MAX17506Integratedconverter

4.5-60 V5 A

128-168 µA ∼ 75 % at 5 mA∼ 80 % at 10 mA>85 % at >100 mA

$3.60 [39]

LM5141Controller

3.8-65 V>5A

35 µAshutdown =10 µA

∼ 70 % at 10 mA∼ 85 % at > 10 mA

$ 2.53 [40]

LM5161Integratedconverter

4.5-100 V1A

50-90 µA ∼85 % at 100 mA $2.07 [41]

LT4356-2Surge stopper

-60-100 V 60 µA (Linear regulation) $2.00 [42]

MAX17597Flyback, pri-mary side

4.5-36 V 2 mAshutdown =20 µA

∼ 90 % at 1 A $0.68 [43]

MAX17606Flyback, sec-ondary side

4.5-36 V4 A

320 µA ∼ 90 % at 1 A $0.71 [44]

From the market survey two diferent converters were chosen and designed to seewhich were the better. The irst one, circled in red in the table, LTC7801 is a buckcontroller that is able to handle more than the required input voltage range on itsown. The second, circled in blue, is MAX17506 that is an integrated buck converterthat needs only a few external components in the design. MAX17506 covers theinput voltage of 4.5-60 V, but needs a pre-converter to handle the highest voltages.The chosen pre-converter, also circled in blue in the table, is LT4356-2 from AnalogDevices, which is a surge stopper that can be conigured as a Low-Dropout regulator(LDO).

A third solution was also evaluated and tested, marked in green in the table. Thisbuck converter solution was based on an evaluation kit provided by Maxim Inte-grated that was reconigured. The evaluation kit consisted of a lyback converterwith a synchronous rectiier.

From the requirements and market survey the switching frequency were decidedto be 500 kHz. The choice were based on maintaining the required eiciency andstill keep the solution size small [48].

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3.3.1 LDO pre-stage

One major problem with the power supply circuit requirements were the widerange of input voltage. There are only a few converters on the market that canhandle the high input voltage of 72 V and convert it down to 5 V at 4 A. Onesolution was therefore to use a linear regulator or a LDO before the buckconverter. In this way the input voltage of the buck converter could be limited toabout 60 V where there are a lot of converters on the market.

A linear regulator acts like a variable resistor that varies with the load. The linearregulator is connected like a voltage divider to maintain constant output voltage.The downside with this solution is that the linear regulator converts the residualpower to heat which gives a low eiciency and high power loss. The linearregulator is supposed to cut the long durational over voltages and is inactive atnominal voltages.

To calculate the expected worst case scenario of the power dissipation of the LDO,maximum load current is expected. Maximum voltage drop over the LDO is 12 V.The duty cycle of the switching buck converter is also needed to calculate thepower dissipation as the current is discontinuous. The duty cycle is calculatedusing equation 1, which gives D = 1/12. With the given information the RootMean Square (RMS) values for the current trough and the voltage across the LDOis calculated using equation 18 and 19.

Iin,RMS =

√

1

T

∫ T

0

i2(t)dt =

√

1

T[t · i2(t)]TD0 (18)

Vdrop,RMS =

√

1

T

∫ T

0

v2(t)dt =

√

1

T[t · v2(t)]TD0 (19)

With the RMS and peak values of the voltage and current known, the average andpeak value of the power dissipation is calculated using equation 20 and 21.

PLDO,AV G = Iin,RMS · Vdrop,RMS (20)

33

PLDO,peak = Iin,peak · Vdrop,peak (21)

Table 4 shows the power, voltage and current levels, calculated using the previousequations.

Table 4: LDO calculations

Iin,RMS 1.155 AVdrop,RMS 3.414 VPLDO,AVG 4 WPLDO,peak 48 W

According to the calculations and the requirements the LDO has to be able tohandle a power dissipation of 4 W in 10 seconds every 2 minutes. The LDO alsohas to be able to handle peak power dissipation of 48 W at 4 A output current.

The input/output current relation in the circuit is shown in Figure 27. The inputcurrent follows the output current when the buck MOSFET is open and is close tozero when the MOSFET is closed.

Figure 27: Input current waveform of a buck converter

34

3.4 System LayoutThis section will show the layouts of the three diferent converter solution and discusswhich one used for the inal design.

3.4.1 Layout of LTC7801

The irst design was made using the LTC7801 controller from Analog Devices [37].LTC7801 has among the highest eiciencies of the buck converters from the marketsurvey. As the controller can handle voltages up to 140 V all the way down to 4 V,there is no need of a pre-converter.

LTC7801 has a mode called burst mode, which is a pulse skipping mode to maintainhigh eiciency at light loads. As seen in Table 3, it has an eiciency of 80 % atoutput current as low as 5 mA. The controller has a low current consumption of 2.5mA in active mode, 40 µA in sleep mode and 10 µA in shutdown. Active mode iswhen the controller operates at nominal switching condition. Sleep mode is whenthe controller operates in PFM mode, which means that the controller enters a lowpower mode between the switching pulses. Shutdown is a mode that the controllerenters when overheated or over voltage occurs, which means that most of the circuitsin the controller is shutdown to prevent damage. A duty cycle of 100 % is possiblewhich means that the design can handle to maintain nominal output voltage at thesame level as the input voltage. The LTC7801 circuitry is shown in Figure 28.

Figure 28: Schematic for the LTC7801 solution

35

3.4.2 Layout of MAX17506 with LDO

The second design was based on the converter MAX17506 from Maxim Integrated[39]. It is an integrated buck converter with an input voltage range of 4.5 to 60 V,which means that it had to be combined with another converter circuit.

MAX17506 does not require a complex external circuit to use, with most of thecomponents built in to the IC. It has its compensation network build into the chipand only has to be complemented by an external capacitor at certain switchingfrequencies. It has the top side switch built into the chip as well, but has to be com-plemented by an external low side switch. MAX17506 can be conigured to workin PFM at low current outtake to increase the eiciency by reducing the frequency.Figure 29 shows the schematic for the MAX17506 design that is able to work up to60 V of input voltage.

Figure 29: Schematic for MAX17506

The LT4356-2 from Analog Devices [42] was used as a pre-converter in the designbased on MAX17506. It is used to prevent the voltage of the main converter to riseabove 60 V. Figure 30 shows the schematic for the pre-converter circuit.

36

Figure 30: Schematic for LT4356-2

The pre-converter is a surge stopper that was conigured as a LDO. The converteris able to work at duty cycles up to 100 % which means that at voltages below 60V the MOSFET is always open. The NMOS gate driver was also used to drive thegate of an NMOS RPP circuit that is shown in the left hand side of Figure 30. Withn-channel MOSFET’s the series resistance in normal working conditions is very low.

In the top of the igure there is a pnp transistor which is controlled by an internalampliier. This was used as a linear regulator to save power in low current modes.The ampliier is still on when the LT4356-2 enters shutdown mode, which leads toa current consumption of only 60 µA and still keeps the output voltage at 5 V.

The design with the integrated converter MAX17506 from Maxim Integrated re-sulted in a layout with few components in the case from 60 to 5 V. LT4356-2 wasconigured as a LDO to handle the higher input voltages and the number of com-ponents in the design were doubled. The total price of the solution got higher thanthe LTC7801 controller solution that can handle the whole input voltage range onits own. Figure 31 shows the inal schematic for the solution.

37

Figure 31: Integrated buck converter solution with LDO pre-stage

38

3.4.3 Layout of Flyback Converter

The lyback layout was based on the MAX17606 evaluation kit from Maxim Inte-grated [45]. It is an isolated lyback converter with a synchronous rectiier and anoptocoupler feedback circuit. The evaluation kit can handle input voltages up to 36V so changes were made to the design to be able to handle higher input voltagesand also rise the eiciency at low current outtake.The Flyback converter evaluation kit for MAX17606 from Maxim Integrated wasreconigured as shown in Figure 32. The changes done to make the converter handlehigher input voltages were to add a large resistance on the input of the primary sidecontroller and couple the output voltage directly to the input port. In this way theprimary side converter is driven by the 5 V output voltage and a small current runsthrough the resistor to start up the circuit. The secondary side rectiier was also re-conigured to be driven from the output voltage through a small resistor. To reducethe amount of component the converter was reconigured to be non isolated to getrid of the optocoupler circuit. The non isolated design also has some modiicationson the compensation and feedback loop to stabilize the new design.

Isolated power supplies are often used in systems were there is human touch in-volved to prevent injuries. It is also used in systems like a microcontroller drivinga high current motor. Isolated power supplies are used for preventing high voltagespikes in the input side to reach the output. In this project the there is no needfor an isolated power supply, to save space and power consumption the optocouplercircuit was removed.

Figure 32: Schematic of Flyback solution

The design was eiciency tested but did not pass the requirements at low currents,

39

even with the modiications. The modiications however increased the eiciency atcurrents above 0.5 A. Measuring results are shown in Figure 33 and Figure 34.

Figure 33: Eiciency curve lyback converter

Figure 34: Eiciency at low current of lyback converter

40

3.4.4 Choice of Converter Layout

The schematics gave a better view on the total number of components in each design,to estimate cost and layout size of the solutions. Estimations along with somemeasurements, the chosen design to look further into was the LTC7801 converterdesign.

3.5 System DesignThe following section presents how the main components of the design were chosenfrom market surveys, simulations and calculations.

3.5.1 The Output Inductor

After the power converter was chosen, the next important component to choosewas the output inductor. As shown in section 2.1 the inductor decides how largethe output current ripple will be. The requirements on output current ripple isshown in Table 1, and has to be below 30 % at nominal input voltage. The largestpossible ripple is produced at maximum input voltage, as the voltage drop over theinductance is at maximum in this case. The inductor current ripple is given byequation 22

∆I =(Vin − Vout) ·D

Lfs(22)

The choice of inductor will decide at which output current the converter will enterDCM as the ripple is independent of the average output current. Figure 35 showscurrent waveform of the buck converter with an input voltage of 48 V with an outputinductor of 8.2 µH at 500 kHz.

41

Figure 35: Output current waveform at diferent loads

As shown in Figure 35 the BCM is at an average output current of 0.5 A. All cur-rents below this value will put the converter in discontinuous mode.Figure 36 shows the BCM current level of the converter with diferent output in-ductances. Average output currents above the BCM line puts the converter in CCMand lower currents puts the converter in DCM.

Figure 36: BCM current level at diferent output inductances

The choice of inductor was made from ive diferent parameters along with theautomotive classiication.

42

• InductanceDecide the current ripple and BCM level

• Series resistance (DCR)witch afects the eiciency due to power loss

• SizeThe physical size of the inductor which afects the PCB layout size

• ShieldingIf the case of the inductor is is magnetically and/or E-ield shielded

• Price

The inductance was chosen to be 8.2 µH, which gives an estimated output currentripple of 30 % at maximum load.This value was chosen to keep some current rippleat low input voltages as the controller is current controlled and need some currentripple to work. Table 5 shows the result from the inductance market survey.As shown in the table the physical size and resistance is directly proportional dueto the diameter of the copper wire in the inductors.

Table 5: Output Inductors 8.2 µH market survey

Model CurrentIrated/Isat

RDC Case/Size Price

784771082WürthElektronik

5.05 A / 5.5 A 20 mΩ Magneticallyshielded12 x 12 mm

$ 1.00

7843330820WürthElektronik

7.2 A / 12.8 A 15.9 mΩ Magneticallycapsuled10.6 x 10.6 mm

$2.04

XAL6060-822Coilcraft

6 A / 8.4 A 24 mΩ MagneticallyShielded6.36 x 6.56 mm

$0.66

XAL1010-822Coilcraft

12.9 A / 18.3 A 11.7 mΩ MagneticallyShielded10 x 11.3 mm

$1.40

IHLE-3232DD-5A(10µH)Vishay

5.1 A / 5.2 A 50 mΩ Magnetic/ E-ield Shielded8.7 x 8.9 mm

$ 0.93

IHLP-5050EZ-A1Vishay

9.5 A / 18 A 18.9 mΩ Magneticallyshielded13.2 x 12.9 mm

$3.22

The inductor XAL6060-822 [46] from Coilcraft was chosen to be used in the design,marked in red. It was chosen due to the small footprint which will reduce the sizeof the PCB. The DC-resistance of the inductor is low with respect to the size of thecasing.

43

3.5.2 Output Capacitors

The next step was to select the output capacitance which decides the output voltageripple. The output capacitor was also chosen large enough to handle the currentripple in the inductor. The output voltage ripple can be derived from equation4 in section 2.1, with the diference that the ESR of the capacitors is taken intoconsideration. The new expression for the output voltage ripple is shown in equation23.

∆Vout = ∆IL

(

Ts

8C+ ESR

)

(23)

Figure 37 is a MATLAB plot based on the previous equation and shows the outputvoltage ripple in percentage versus the output capacitance, with the resistive andcapacitive parts plotted separately. ESR were estimated to be around 50 mΩ andcapacitance varied. As seen in the igure the ripple goes from being dominated bythe capacitive part to the resistive part. This means that to lower the ripple theresistive part needs to be minimized as well as using a large value capacitance.

Figure 37: Output voltage ripple at diferent capacitances

To achieve low output ripple multiple capacitors were put in parallel to increase thecapacitance and lower the ESR.

44

ESRmax =∆Vout∆Iout

(24)

The chosen output capacitor was an electrolytic 1500 µF able to handle large loadtransients and current ripple. Along with the electrolytic capacitor a smaller ceramiccapacitor with 22 µF was selected in order to ilter the higher frequencies and reducethe switching loop areas to reduce EMI.

3.5.3 Input Filter

The input ilter was designed with two purposes. The irst purpose is to prevent EMIcaused by the switching device to reach the power line and afect other equipment.The second purpose is to prevent noise from the power line to reach the convertercircuit. As a rule of thumb the cutof frequency should be placed at least one decadebefore the switching frequency. The ilter should also be able to handle the ripplecurrent caused by load transients according to equation 25.

∆Iin =Vout

Vin · η·∆Iout (25)

The ilter should be able to handle around 1.4 A at the highest load transients atlow input voltage according to equation 25.The ilter designed is shown in Figure 38 and is a third order damped pi-ilter. Thecutof frequency is placed below 10 kHz to have high attenuation at the switchingfrequency. The electrolytic capacitor is used for damping and also handle highcurrent ripples. The ilter component values were chosen as high as possible withrespect to component size as an abrupt attenuation at the cutof frequency is notnecessary.

Figure 38: Input ilter design

45

Simulations were done using LT Spice to get the characteristics of the ilter, as shownin Figure 39. The simulation shows the amplitude and phase characteristics of theilter, which has an attenuation of -45 dB at switching frequency.

Figure 39: Input ilter simulation LT Spice

3.5.4 Switching MOSFETS

The MOSFET switches is an important component to evaluate in the matter ofeiciency and EMI. The MAX17506 solution had the primary switch built in to theIC but need an external synchronous switch. The LT7801 is a synchronous buckcontroller which means that both the primary and synchronous switches are externalMOSFET’s. The choice of MOSFET’s were made from the following parameters;

• Drain-Source resistance, Rds(on)The resistance between drain and source in on-state is a series resistance andafects eiciency.

• Package typeDiferent packages has diferent input inductance in the contacts which afectsswitch node ringing.

• Of state capacitance, CossAfects the resonant frequency of the conductive loops which afects the am-plitude of the switch node ringing. Most important is to have a low Coss valueon the low side MOSFET.

• Rise and fall timesDetermines the amount of time the MOSFET is in its linear region, whichafects eiciency.

46

• Package sizeAfects the layout size.

Table 6 shows the result from the market survey of the switching MOSFET’s. Asshown in the table the packages with no leads has higher of state capacitance, butat the same time lower series inductance. The current capacity of the MOSFETalso afects the capacitance as the internal widths are increased, which at the sametime lowers the series resistance. In the table some of the MOSFET’s are labeled”Dual”, which means that there are two MOSFET’s in the same package.

Table 6: NMOSFET

Model Voltage/Current

Rds(on)[mΩ]

Package/Size

Coss[pF]Vds:48V

Trise/Tfall[ns]

Price[$]

STL92N-10F7AGSTL

100 V/16 A

9.5 PowerFLAT6 x 5 mm

700 32/13 0.93

STL115N-10F7AGSTL

100 V/28 A

6 Power FLAT6 x 5 mm

1200 33/48 0.81

BUK7M17-80Enexperia

80 V/43 A

17 LFPAK33(SOT1210)3.4 x 3.4 mm

140 9.4/12 0.34

BUK9M34-100Enexperia

100 V/29 A

34 LFPAK33(Power33)3.4 x 3.4 mm

110 26.2/22 0.26

SQJQ910-ELVishay

100 V/40 A

8.6 PowerPAK®8 x 8L Dual8 x 8 mm

800 4/7 1.23

SQJB80EPVishay

80 V/30 A

24 PowerPAK®SO-8L Dual6 x 5 mm

375 3/24 0.45

SQSA80-ENWVishay

80 V/18 A

21 PowerPAK®1212-8W3.3 x 3.3 mm

375 2/5 0.42

The chosen MOSFET was SQSA80-ENW [47] from Vishay, marked in red in Table6. It was chosen due to the small footprint and fast rise and fall times. It also haslow on resistance with respect to size and smaller of capacitance than the largerMOSFET’s.

47

3.5.5 Loop Compensation

To maintain stability in the converter under all conditions a loop compensation net-work was designed. The MAX17506 converter has most of the compensation networkbuilt into the IC. The only thing needed was to put an external capacitor across thecompensation network as the frequency was chosen lower than the default frequency.

For the LTC7801 which is a current controlled converter, a Type II compensationwas used. With the decided values for the output inductance and capacitance withits parasitic parameters ESR and DCR, the compensation component values weredetermined. With the help of LT PowerCad and the transfer function of the closedloop, the compensation values were simulated until the gain and phase margin metthe requirements.

Figure 40: Power Cad setup for loop compensation

Figure 40 shows the setup in Power Cad with the option to adjust the compen-sation values Cth,Rth and Cthp. To the left in the igure is the selected outputcomponents with its characteristics. The yellow boxes at the bottom shows thephase margin and bandwidth for the given input voltage V in and output currentIo. The input voltage was increased throughout the entire voltage range and thecompensation values were adjusted so the the phase margin were held above 60°for the entire input voltage range, according to the in-house requirements for phasemargin, shown in Table 1. Figure 41 shows the bode plot of the system gain and

48

phase with the settings from Figure 40 and a 4.99 V output. The graphs added abetter visual understanding for when the components were determined.

The inal values for the compensation network are shown in Figure 42, which isa close-up on the full schematic in Figure 28. The bode plot for gain and phaseare shown in Figure 41, where gain is plotted in blue and phase in red. The phase-margin is held above 60° for the entire input voltage range and the bandwidth isat 14 % of the 500 kHz switching frequency, which is marked with a green line inFigure 41.

Figure 41: Loop gain and phase for the selected compensation components

49

Figure 42: Compensation network schematic values

3.5.6 Reverse Polarity Protection

To prevent damage from connecting the battery in reverse polarity, protection cir-cuits were designed. The RPP looks a bit diferent on the diferent designs as theLT4356-2 surge stopper has built in charge pump [42]. In this way it is possible toconigure the surge stopper as a smart diode using a backward connected NMOS.

In the design with the LTC7801 controller the choices were to use a PMOS, NMOSor a Schottky-diode for reverse polarity protection. The three diferent solutions areshown in Figure 43. Figure 43 (a) shows the Schottky-diode RPP, Figure 43 (b)shows the PMOS RPP and Figure 43 (c) show the NMOS RPP

Figure 43: Topologies for reverse polarity protection; (a) Schottky-diode RPP, (b)PMOS RPP and (c) NMOS RPP

The choice of RPP topology for the LTC7801 solution were made from the estimatedpower dissipation, complexity and cost. Equation 26 shows the power dissipationusing a Schottky-diode. The voltage drop was estimated to 0.6 V, which is basedon 60 V diodes from multiple manufacturers.

Ploss,Schottky = Vdrop · Iin = Vdrop · Io ·Vo

Vin(26)

50

As seen in the equation the diode has a high maximum power dissipation at low inputvoltage, resulting in lower eiciency at high loads as well as high heat evaluation.To compare the maximum power dissipation with the MOSFET solutions, the samecalculation were done for a PMOS and NMOS, shown in equation 27. The resistancevalues of the MOSFET’s used in the equation is based on values from diferentmanufacturers. For the NMOS the on state resistance were estimated to be 15 mΩand 130 mΩ for the PMOS.

Ploss,mosfet = Rds,on · I2 = Rds,on ·(

IoutVout

Vin

)2

(27)

The power dissipation calculations were done for multiple output currents which ispresented in Figure 44.

Figure 44: Power dissipation in diferent RPP solutions

Seen in the igure the power dissipation gets lower with the increased complexityof the protection circuit. From the calculations, complexity and estimated cost thePMOS solution were used in the LTC7801 circuit.

51

3.5.7 Reducing EMI in Buck Converter

In order to meet the requirements from the customer regarding EMC and EMI,several design choices were made to achieve this.

The utmost important design choice was to reduce the high di/dt loop area, whichwas achieved by placing the Cin capacitor C6 shown in Figure 28 close to the V interminal on the LTC7801. The transistors and the output inductor/capacitors werealso placed close to each other with their ground connections close to the groundconnection of the input capacitor, to reduce the primary current loop area. Figure45 shows the primary current loop in red and the shortest way for the high frequencycomponents in green.

Figure 45: Main current loops on PCB

Figure 46 shows the secondary current loop on the PCB highlighted in blue. Thelow side transistor, Q2, the output inductor, L1, and the output capacitor, C14,form the secondary current loops. Minimizing these three current loops was thehighest priority when placing the components on the PCB. A ground plane was alsoused as the second layer in the PCB stack, with the purpose of decreasing currentloops and in this way decreasing EMI.

52

Figure 46: Secondary current loop PCB

Minimizing the switch node ringing was the secondary EMI aspect to consider whendesigning the PCB layout. The snubber circuit shown in Figure 28 consisting ofR15 and C16 was implemented as an option in the PCB design. The snubber wasplaced close to the secondary MOSFET to act as a damping circuit parallel to theof state capacitance of the MOSFET.

In addition a 0 Ω gate resistor, R13, was also implemented in the design for thepurpose of slowing down the rise-time of the high-side FET and furthermore reduceswitch node ringing. The value of R13 can be modiied in order to set the desirablerise-time of the MOSFET. The QFN package type was used for the LTC7801 tolower the per-unit-length inductance which is one of the main causes for the ringingbehavior. A 0 Ω resistor, R14, was also implemented in series with the bootstrapcapacitor, C10, to reduce switch node ringing even further. This resistor also en-abled an option to reduce the rise time of the MOSFET if needed.

3.5.8 Circuit Layout

The solution that was most space and cost efective was the design based on the buckcontroller LTC7801 from Analog Devices. This was the solution that was chosen tomanufacture and test with a complete test sequence. Figure 47 shows the completecircuit for the power supply, with reverse polarity protection and input iltering.

53

Figure 47: Buck controller solution with RPP and input ilter

54

3.5.9 PCB Layout

From the schematic a PCB layout were made in Altium Designer. The PCB designwas built on a four metal layer substrate with layer two and four as ground planes.All components are placed on the top layer along with the high frequency currentloops. Close to the top layer is the irst ground plane for decoupling of high frequencycurrents. Layer three is used for routing small signal wires from the buck controllerand also for making the input voltage rail as large as possible. The fourth layer iskept close to the third layer for decoupling. Figure 48 shows the layer stack fromAltium Designer.

Figure 48: PCB layer stack

Figure 49 shows the top layer of the design. As seen in the igure the top layer issplit into four parts, which is input voltage, output voltage and two ground planes.There are two diferent ground planes to be able to predict the switching currentloops. The top left ground plane is connected to the other ground planes throughfour vias placed directly under the controller, U1. In this way it is easier to predictthe return path of the current loops.

55

Figure 49: PCB Top Layer

Figure 50 shows the second signal layer, which is layer three from the top. Thesignals routed on this layer is the current sensing signals from the output inductorto the controller. The current sensing signal traces are routed on this layer to beisolated from the high frequency signals that could generate noise into the currentsensing circuit. The input voltage is also available on this layer, which is the largepolygon in the middle of the igure.

Figure 50: PCB Signal Layer

56

4 Test and VeriicationThe sequence of tests performed on the system are described in this section. Thetests were performed to see if the design met the requirements from both customerand CISPR22. All the results from the tests are s