December 3, 2009

Design and optimization of integrated transmission lines on scaled CMOS technologies

1 Dipartimento di Elettronica, Università di Pavia, Italy 2 Istituto Universitario di Studi Superiori, Pavia 3 STMicroelectronics & Studio di Microelettronica, Pavia

F. Vecchi1,2, M. Repossi3, W. Eyssa1,2, P. Arcioni1, F. Svelto1

2 December 3, 2009

Outline

3 December 3, 2009

Motivations

4 December 3, 2009

Microstrip (MS)

* H. P. Hsu, “On the general relation between α and Q (correspondence)”, IEEE Transaction on Microwave Theory and Techniques, Vol. 11, No. 4, July 1963, p. 258.

Line Quality Factor (QL)*: β / (2α)

Pro: shielded from substrate losses (P+ Doped Well) Con: only one degree of freedom (W)

65 nm STMicroelectronics CMOS Technology

@ 60 GHz with Z0 = 50 Ω: QL ≈ 10.5

α = 1.2 dB/mm

5 December 3, 2009

Coplanar Waveguide (CPW)

Pro: two degrees of freedom (W and G)

Con: sensitive to substrate losses (P+ Doped Well)

A careful analysis of metal and substrate losses is necessary in order to optimize performance for a given characteristic impedance *

* F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni, F. Svelto, “Analysis of Loss Mechanisms in Coplanar Waveguides Integrated on Bulk CMOS Substrates”, 39th European Microwave Conference, EuMC 2009, pp. 189-192, September 2009.

6 December 3, 2009

CPW with P+ Well (Simulations)

Z0 (Ω) @ 60 GHz Line Quality Factor @ 60 GHz

@ 60 GHz with Z0 = 50 Ω: QL ≈ 7 α = 1.7 dB/mm

Z0 = 50 Ω

Z0 ↑

7 December 3, 2009

CPW without P+ Well (Simulations)

Z0 (Ω) @ 60 GHz Line Quality Factor @ 60 GHz

@ 60 GHz with Z0 = 50 Ω: QL ≈ 12 α = 1 dB/mm

Z0 = 50 Ω

Z0 ↑

8 December 3, 2009

Experiments (with and w/out P+ Well) Very good agreement between simulations and measurements

Substrate has to be accurately characterized in order to minimize losses

9 December 3, 2009

Grounded Coplanar Waveguide (G-CPW)

Is this the right solution?

Pro: two degrees of freedom (W and G)

Pro: shielded from substrate losses (P+ Doped Well)

10 December 3, 2009

Standard CPW Current Distribution

Standard CPW (W = 9.5, G = 4)

Negative Mutual Coupling between Signal and Ground

Conductor (currents are equal

and opposite)

Total per length inductance depends on mutual coupling between signal and ground conductors

Ground Signal

Magnetic Wall

Metal 7 Mutual

Coupling

Half T-Line Cross-Section

11 December 3, 2009

M1 Ground Effect (Current Distribution)

Standard CPW (W = 9.5, G = 4)

with Metal 1 Ground Plane (G-CPW)

Negative Mutual Coupling between Signal and Ground

Conductor (M1 & M7)

Total per length inductance is lower than Standard CPW Increased per length capacitance due to Metal 1 Ground Plane

Metal 7

Mutual Coupling

Metal 1

12 December 3, 2009

M1 Ground Effect (RLGC parameters)

Substrate losses (G) are suppressed, metal losses (R) slightly increased Mutual coupling lowers L and increases C Z0 lowers

13 December 3, 2009

Loss Distribution

75 % 13 %

12 %

G-CPW Optimization (Z0 = 50 Ω) W = 3 µm G = 3 µm

W = 5 µm G = 10 µm Loss Distribution

67 % 1 %

32 %

14 December 3, 2009

Physical T-Line Model *

* B. Kleveland, T. H. Lee, S. S. Wong, "50-GHz interconnect design in standard silicon technology“, 1998 IEEE MTT-S International Microwave Symposium Digest, Vol. 3, June 1998, pp. 1913-1916.

To suppress substrate losses without impairing L and C and without increasing total resistance, we have to:

• Lower Rp • Increase ZShield h

15 December 3, 2009

Shield with Anisotropic Conductivity

•  Can be achieved with a periodic structure

•  Difficult to analyze and optimize

HFSS Simulation: CPW with anisotropic shield

•  σ = 0 along Prop. Direction

•  Metal σ along orthogonal direction

16 December 3, 2009

Examples of periodic integrated TL

CMOS substrate CMOS substrate CMOS substrate

CPW Microstrip Slow-Wave CPW

Dummy Metal Fills Floating Strips

Lines not uniform in the propagation direction 2D E.M. analysis on the cross-section doesn’t apply

Conventional 3D analysis huge amount of CPU and memory resources

However, all these structures are (or can be implemented as) periodic

17 December 3, 2009

Periodic Structure Analysis

Structures inhomogeneous (but periodic) in the direction of propagation Floquet Analysis

For a given frequency, an E.M. Field is calculated such that the following relations are satisfied:

The Floquet port in HFSS is used exclusively with planar-periodic structures (not periodic in the direction of propagation)

However, it is possible to calculate the eigenmodes of a structure with periodic boundary conditions imposing a phase delay (not attenuation)

How to calculate the characteristic of the line?

18 December 3, 2009

Proposed Method* (1)

Transmission Line

Q-Factor

Generic Resonator Q-Factor

We need:

We impose:

* F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni, F. Svelto: “Design of Low-loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, September 2009, pp. 2605-2615.

19 December 3, 2009

Proposed Method (2)

Characteristic impedance is calculate by means of the standard definitions Zpv, Zpi, Zvi

Power flow is calculated by integrating the Poynting vector over the surface S

Voltage and current are calculated by integrating electric and magnetic field over appropriate integrating lines (blue and red line, respectively)

CMOS substrate

S

Voltage Integration

Line

Current Integration

Line

20 December 3, 2009

Design example 1 – Slow-Wave CPW (SW-CPW) *

Smart use of metal dummy fills to increase the phase constant of the line

Shorter lines needed in matching circuits, filters, … Reduced area occupation

As in G-CPW, substrate is shielded from the electric field almost no substrate losses

Large gap and small line widths needed to keep impedance close to 50 Ω Increased conductor losses

Design Rules Compliant

* F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni, F. Svelto: “Design of Low-loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, September 2009, pp. 2605-2615.

21 December 3, 2009

SW-CPW Design

•  Grey areas denote unfeasible values due to Design Rules

•  Lower Wb/d to enhance QL

•  Lower D to enhance β

Strips Geometry (M1 to M7)

22 December 3, 2009

Experimental verifications – SW-CPW Simulation time: 5 min. per frequency point

23 December 3, 2009

Design example 2 – Shielded CPW (S-CPW) *

Thin bars transverse to propagation

Equivalent to a slotted G-CPW no longitudinal currents in the bottom ground plane

As in G-CPW, substrate is shielded from the electric field almost no substrate losses

The reduced additional capacitance of the shield allows for wider signal line width Reduced conductor losses

Design Rules Compliant

* F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni, F. Svelto: “Design of Low-loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, September 2009, pp. 2605-2615.

24 December 3, 2009

S-CPW Design

•  Grey areas denote unfeasible values due to Design Rules

•  Lower Wb/d to enhance QL

•  Lower D to enhance QL and β

Strips Geometry (M1)

25 December 3, 2009

Experimental verifications – S-CPW

Best attenuation ever reported for standard scaled CMOS process

Simulation time: 5 min. per frequency point

26 December 3, 2009

State-of-the-art of attenuation for integrated TL

27 December 3, 2009

State-of-the-art references

28 December 3, 2009

Conclusions

29 December 3, 2009

Publications W. Eyssa, M. Repossi, F. Vecchi, P. Arcioni and F. Svelto, “Linee a Basse Perdite per Circuiti Integrati ad Onde Millimetriche in Tecnologia CMOS”, XVII Riunione Nazionale di Elettromagnetismo, RiNEm 2008, September 2008.

F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni, F. Svelto: “Design of Low-loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 9, September 2009, pp. 2605-2615.

F. Vecchi, M. Repossi, W. Eyssa, P. Arcioni, F. Svelto: “Analysis of Loss Mechanisms in Coplanar Waveguides Integrated on Bulk CMOS Substrates”, 39th European Microwave Conference, EuMC 2009, pp. 189-192, September 2009..