Design and Operational Testing on Thryristor Module for the SVC Kemps Creeek_siemens

8/9/2019 Design and Operational Testing on Thryristor Module for the SVC Kemps Creeek_siemens

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1321

DESIGN AND O PERATIONAL TESTING ON THYRISTOR MODULES FORTHE SVC KEM PS CREEK

B Endres G.Thiele

Siemens AG

Erlangen.Germany

I.Bonfant i

A b s tr a c t Th e p ap e r de a ls w i th th e d e s ig n a n d o p e ra t i o n a l

test ing o f va lves fo r the

SVC

t o b e i n s ta l l e d a t K e mp s Cre e k

Substation in Austral ia The most impo rtan t design pr inciples and

features o f the thyr is tor modules are g iven

O p e r a t i o n a l te s ts ca r r i e d o u t o n th e th y r i s to r mo d u le s a re

descr ibed, fo r th is test p rogram, notew or thy test c i rcui ts h ave

b e e n se t u p to p e r fo rm b o t h

TSR

and TSC fau l t cur rent tests wi t h

h igh test va lues and special wave forms Test resu l ts and test

circuits are presented Dielectr ic tests carried out on th e valve and

valve structure are no t included

Keywords: SVC, t h y r i s t o r va l ve, o p e ra t i o n a l te s ts ,

TSC

f a u l t

curren t test, TCRflSR fau lt current test

G.

Testi

CESl

Mi lan, I ta ly

INTRODUCTION

The in terconnect ion o f the South Austra l ian power system wi th

the previously in terconnected V ictor ia and New South Wales

system

i s

scheduled to take p lace in 1990

To

avo id degrad ing o f

the po wer transfer capabi l i ty of the existing Victor ia New South

Wales system, tw o Static Var C ompensators (SVC) wi l l be instal led

in the Sydney area a t Kemps Creek

/1/

Each SVC consists of t w o Thyristor Swit ched Capa citors (TSC)

ra te d a t 100 (TSC1) and 50 (TSCZ) MVAr and one Thyr is tor

Switched Reactor (TSR) rated at 100 MVAr TSR and

TSC

valves

have similiar structural arrangeme nts Concerning TSR, a 3-phase

valve tower consisting of 3 water -coo led thyr is tor m odules (one

modu le per va lve) , one on top o f the o ther , was used As

t

the

TSC valves, tw o series-connected modules provid e one phase and

there fore the 3-phase ar rangement consists o f two va lve tow ers

The

SVC

valves were subjected in 1988 to an extensive type test

program Die lectr ic tests were car r ied out o n the va lve structure

a n d o n th e val ve s Fu n c t i o n a l te s ts we r e p e r fo rme d o n th e

thyr is tor modules o f TSC and TSR by using special ly designed

pow er circuits

Th is paper deals wi th these funct iona l tests To d iscuss test

results and test circuits, it is necessary

to

d e a l w i th th e va l ve

design pr inc iples Deta i led in forma t ion i s g i v e n o n t h e p o w e r

circuits and o n the w ay o f ob taining fau lt current stresses on TSR

an d TSC valves

90 l nr 041-4 PWFB

paper recommended and approved

by the I Sub sta tion s Committee o t h e I Power

Engineering Society for presentation

a t

the IEEE/PES

1990 Winter Meeting Atlanta Georgia February

Manuscrip t submi tted August 31 1989:

made available for printing November 17 1989.

-

8 1990.

SVC

GENERAL DESCRIPTION AND MA IN D ATA

As ment ioned above, the SVC in Kemps Creek consists of t w o

ident ica l un i ts fo r re l iab i l ity considera t ions The requ i red power

of the comple te SVC was f ixed a t 300 MVA r capaci t ive and 200

MV Ar inductive Each SVC unit comprises one

TSR

a n d t w o TSCs

and

i s

e q u ipp e d w i th

i t s

ow n step-down t ransformer The TSR

ra te d p o we r

is

100 MVAr , the TSCs provide 100 a n d 50 MVAr,

respectively

Thus a un i fo rm step

size

of about 50 MVAr

is

achieved over the

ent i re contro l range

of

t h e t w o SVCs (-2OOMVAr / + 300MVAr)

In order to avo id harmonic genera t ion

it

was decided to use a

TSR instead of a Thyristor Control led R eactor (TCR) The general

conf igura t ion o f one

SVC is

i l lustra ted in F igure

1

330

k V

150 MVA

LT SC l

k

T S C l

TSC

1

100 M V A r

4

A

TSCZ

TSC 2

50

M V A r

f LTSR

SR

LTSR

100 M V A r

f LTSR

f

LTSR

TSR

100 M V A r

Flq . l :S impl i f ied s ing le l ine d iagram of one SVC

M AI N STRESSES CONSIDERED FOR VALVE DESIGN

The transient stresses considered for th e valve design i nclu de

those occuring at load rejection, severe 3-phase and single-phase

system faults, TSR and TSC mis f i r i n g , e tc , o r r e su l t i n g f r o m a

combinat ion o f these events

TSC o ve rvo l ta q e ca u se d b y l o a d r e j e c t i o n . Un d e r n o rma l

cond i t ions th e SVC i s requ i red to provide capaci t ive load i f the

system voltage drops belo w a specified level and induc tive load i f

the system voltage

is

beyond th is leve l A f te r load re ject ion the

transient v oltage r ises e g

f r o m 0

7

p U

t o 1

3

p U Request fo r

inductive load means instantaneous b locking of t h e

TSC

va lve

af ter load re ject ion , t ransient overvo l tages may then force the

capacito r vo l tage up to abou t 2 5 p

U

Since the recovery voltage

of the valve

i s

the sum of the dc vo l tage a t the capaci to r and the

system voltage, valve peak voltages of abo ut

4

p U are possible A

va lve d e s ig n a l l o w in g fo r su ch h i g h vo l ta g e s wo u ld n o t b e

economical


2/6

1322

The valve vo l tage can be redu ced by m eans o f a r res t o rs

connected across th e capacitor ban k an d across the valve. The

arran gem ent of these arresters is also shown in Figure

1 .

Misf ir inq of TSC valves: By the special arrester arran geme nt

shown in Figure 1 the valve vol tage w i l l be l im i ted to sui table

values.even in case of a TSC misfiring. Misfiring of a TSC can at

wors t occur whe n the system vol tage and th e ca'pac itor bank

voltage are in phase opposit ion. Although misf ir ing of the valve

in i t iated by mal funct ion of the cont ro l sys tem is unl ikely , the

valve design must al low for th e stress caused by mis f ir ing witho ut

a risk of valve damage.

In the case of m is fi r ing, th e rate-of - rise of t he fa ul t current w i l l

be l imi ted by the series reactor to prevent the thyr is tor valve

from being overstressed.

- - - - - - - -

Valve misf ir ing

I


3/6

1323

THYRISTOR VALVE AND MOD ULE DESIGN

To al low f or th e steady-state conditions as we l l as the transient

stresses on the valve, and considering test safety margins, the TSR

si li con w i th a wafer d iameter o f 100 mm and vo l tage ra t ings o f

5 5 kV in fo rw ard and reverse d irect ion .

To transmit valve con trol signals from th e valve base electronics

at ea r th potent ia l t o each thyr is tor , the TSC an d TSR valves a re

connected wi th a f ib re opt ic system as re liab ly used for HVDC

valves

A

description can be found in

/3/ )

F r o n t v i e w

' or

electronics

l h y r i s i o r m o d u l t

Duct

l o r l i g h t

Snunber c a p a c i l

wa t e r

c o o e a

,

snubner

r e r i s i

guides

S i d e

v i e w

T hyr is t o r

e le c t r o n m

d \

F l q V a l v e o w er

valve i s designed wi th

1 1

thyr istor levels, whereas the TSC valves

have 22 thyr istor levels in series The TSR th ree-phase va lve

shown in Figure

5

consists o f three m odules arranged one above

the o ther in the fo rm o f a tow er , whereas the TSC- three-phase

va lve consists o f t w o such towers

TSR

and TSC modu les are ident ica l except fo r t he adop ted

snubber circuits

A

v ie w o f t h e t h y r i s t o r m o d u l e

i s

sh o wn i n

Figure

6

Thyristor module

A

t h y r is t o r m o d u l e c o m p r i s e s t w o a n t i p a r a l l e l s t a c k s o f

thyrist ors Each stack consists of

1 1

thyr istors Each antipa ral lel

pair of thyr istors forms a thyr istor level with a paral lel-connected

snubber e lement Fur thermore the thyr is tors are each provided

wi th an electronic card, which gives fi r ing signals to th e thyr istor

gate e lectrode and checkback s igna ls to a m oni tor ing system

Cross cur rent t ransformers are f i t ted betwe en the two stacks The

thyristors used for this projec t are made from neutro n-irradia ted

Powe r supply for thyr istor electronics: The p owe r supply via cross

cur rent t ransformer is wo r th to b e n o t ice d .

Thyristor

I Cross curre nt electro nics

PS U): Power

supply via voltage

or snubber circuit

PS(I): Power

supply via current

-

Snubber circuit

Optical f iber

transm ission

f i r ing and

moni tor ing

signals

d i rect on

Pr inc i ia l d iagram of power supp ly fo r thyr is tor e lectron ics

In addition t o the energy extra ction via the snubber circuit as

u se d i n th e ca se

of

HV DC va l ve s o r TCR va l ve s , cu r re n t

t r a n s fo r m e r s ar e us ed t o p r o v i d e p o w e r f o r t h e t h y r i s t o r

e lectronics dur ing the on-sta te per iod o f TSR or TSC valves B y

plac ing these t ransformers in the cross connect ion o f t he tw o

stacks, a compact thyr is tor module is a ch ie ve d Th e p r i n c i p a l

d iagram of his powe r supp ly ar rangement

is

shown in F igure 7

Valve control: The fi r ing of the valves is control led by signals

from the valve base electronics The principle used for f i r ing the

valves is f i r inq on request

O n c e t h e t u r n - o n s i g na l h a s b e e n a p p l i e d t o t h e t h y r i s t o r

electronics (TE), no periodic repeti t ion is requ i red because the

th y r i s to r e l e c t r o n i cs th e mse l ve s g e n e ra te g a te p u l se s i f t h e

fo l low ing cond i t ions are fu l f i l led

-Sufficient thyr istor voltage and correct polar i ty

- In terna l power supp ly provided a t the TE

In th is case a shor t ga te pu lse o f e g 50 ps

is

genera ted

I t i s

possible to substi tute a f i r ing system using long pulses by one

u s i n g t h e p r i n c i p l e o f f i r i n g o n r e q u e s t w i t h o u t a n y

disadvantages In case of cC)mmutation fro m fo rw ard t o reverse

d i rect ion in the cur rent mode, the f i r ing pu lse fo r the reverse

d i rect ion is g e n e r a t ed i m m e di at e ly , t h e r e f o r e n o d e a d t i m e

occurs in the valve current

S p ec ial a t te n t i o n wa s p a id to t r a n s ie n t i n ru sh c u r re n t w i th

mul t ip le zero crossings and a lso to t he t ransi t ion f rom the on-

s ta te to th e o ff - s tate o f th e va lve , wh e re p a r t i a l tu rn -o f f o f th e

va lve cou ld occur To prevent damage to th e va lve in case o f

par t ia l tu rn-o f f , act ive e lectron ic backup t r igger c i rcu i ts and

BOD circuits are pro vided


4/6

1324

The act ive e lectronic backup t r igge r c i rcu i t opera tes dur ing th e

o n - s ta te a n d h e h o ld o f f i n te r va l l o f th e th y r i s to r Du r i n g th e o f f

s ta te o f th e va lve , the e lectron ic backup t r igger c i rcu i t is inactive.

ther e for e h igh vo l tage capab i l i ty

is

ach ieved

T o t a k e ca re o f t h e p a r t ia l t u r n o f f p h e n o m e n a , a d v l d t

pro tect io n c i rcu i t is inc luded Th is c i rcu i t becomes active f rom the

e n d o f th e a c tu a l co n d u c ti n g i n te r va l u p to th e e n d o f th e h o ld

of f in terva l l The dv/d t p ro tect ion c i rcu i t genera tes a pro tect ive

fir ing pulse if the posi tive ra te-o f- r ise o f th e thyr is tor recovery

vo l ta g e e xcee d s th e r e sp o nse l e ve l B y r e s t r i c t i n g th e d v / d t

p r o t e c t i o n t o t h e h o l d - o f f i n t e r v a l l , e

g

s o m e

100

ps

n o

d e g r a d in g o f va l ve w i th s ta n d ca p a b i l i t y fo r v o l ta g e imp u lse s

occurs at b locking stage

Pr inc ip le o f TSC va lve overvo l taqe pro tect ion

As

descr ibed

above, valve arresters (SR-arresters) and capacitor arresters (CC-

arresters) are used This offe rs some advantage s

- CC arrester act ion dur in g misf i r ing lowers the capacito r vo l tage

and thus th e va lve vo l tage I t a lso reduces the cu r rent ra te-o f- r ise

af te r misf i r ing and thus th e thyr is tor tu rn-o f f s tress ing Lower ing

the d i /d t a lso reduces the vo l tage overshoot a t tu r n-o f f

-The

SR

arrester pro tects the va lve aga inst overvo l tage s The

arrester level is set be low the sum of the ind iv idua l p ro tect ive

f i r i n g l e ve l s Th e re fo re

it i s

p o s s i b l e t o u s e a n i n d i v i d u a l

pro tect ive f i r ing system for each thyr is tor w i tho ut increasing the

r isk o f misf i r ing due to the act iva t ion o f th is pro tect ion on a l l

thyr is tors in case o f h igh overvo l tages Figure 2 shows

SR

and CC

arrestor ac tion durin g TSC mis-fi r ing

In case o f the va lve be ing f i red wi th t he ar rester in opera t ion .

th e ar rester cur rent comm utates to the thyr is tors To prev ent

thyr is tor dam age due t o h ig h d i id t s t ressing, the va lve ar rester is

arrange d n para l le l wi th he va lve and the TSC va lve reactor (see

Fig 1)

Principle of TSR valve ove rvolt aqe protec tion No arrester

is

used

for th e TSR In case th e voltag e capabi l i ty of t he TSR val ve

i s

exceeded, the ind iv idua l p ro tect ive f i r ing system p ro tects t he

va lve by f i r ing a l l thyr is tors Th is unco ntro l led f i r ing in i t ia te d by

the pro tect ive f i r ing system is one o f the possib i l i t ies o f TSR

mis fir ing Unde r worst-case conditions it ma y l e a d to a cu r re n t

value twic e as high as in contro l led circumstances This possibil i ty

is considered in he TSR valve design and h ence no valve arrester

is

necessary

The above overvo l tage pro tec t ion cr i te r ia were used also dur ing

the opera t iona l ests.

VAL VE TESTING

The Kemps Creek thyr is tor va lves we re sub jected in 1988 to an

extensive type test p rogram Di f f e ren t d ie lectr ic and opera t iona l

tests we re carr ied out o n the valve an d on valve sections Special

test circuits were used to p roduce mis fir ing stress on TSC valves

and to app ly fau l t cur rent t o he TSR modules

Some of the ests are specific for t he Kem ps Creek project, others

prove he va lve design fo r o ther app l ica t ions as we l l

Dielectric tests

On valve structure: These tests were carr ied

o u t o n t h e s a m e

structura l a r rangement as used in th e rea l p lan t , there fo re it was

necessary to carry ou t these tests o n a valve tow er as described in

Figure

S

The va lve structure was sub jected

to

he fo l low ing tests

-valve terminals

to

g ro u n d te s t w i th a c vo l ta g e a n d w i th a c

vo l tage super imposed on a dc vo l tage

- l igh tn ing impulse test be tween va lve te rmina ls and ground.

B e twe e n va lve te rm in a l s : Tw o d i f fe re n t t yp e s o f te s ts we re

car r ied out :

4est swi th ac vo l tage and wi t h ac vo l tage super imposed on a

dc voltage.

-swi tch ing im pulse tests w i th waveforms 20/200ps and

250125oops.

Al l

d ie le c t r ic te sts we re e xe cu te d a t th e te s t l a b o ta to r i e s o f

Siemens GWE

Operat iona l ests

S y n t h et i c c i r c u i t t e s t s T o p r o v e t h e t u r n - o n a n d t u r n - o f f

behaviour o f the va lve as we l l as the com mutat ion f rom forwa rd

to reverse cur rent in tu r n on m ode, a synthet ic test c i rcu i t as

described in

8

was used Figure 8 demonstra tes the wavefo rm

achieved by this test circuit Tests have been perform ed a t the

Siemens GWE factory

I

U

L

’

/

1 7

4

.

Turn- Changeover

Turn-

o n f r om t o - o f f

Flq.8:

Synthetic test circuit

Severa l tests were car r ied o ut us ing power c i rcu i ts a t the CESl test

labora to ry a t Mi lano, I ta ly

A

survey o f the p er form ed tests togethe r wi t h m ain test values

i s

g i ve n i n Ta b le l , wh i ch a lso i n d ica te s th e te s t c i r cu i ts a n d te s t

ob jects used, as we l l as the num ber o f thyr is tors exposed The

numbe r o f thyr is tors was chosen as appropr ia te fo r the requ i red

test va lues and th e capab i l i t ies o f th e test fac il i ties

Speci fica lly designed e lectron ic in ter faces we re se t up o prov ide

th e f i r ing s igna ls. as genera ted by the

CESl

contro l system, t o the

va lve base e lectron ic o f th e test ob ject in the pro per way an d to

synchronise al l th e diffe re nt test sequences

TSC combined heat- run and loss-determinat ion est The purpose

o f t h i s t e s t wa s t o d e m o n s tr a te t h e a b i l i ty o f t h e v a lv e t o

with stan d the m ost severe steady-state stresses The test circuit 1

used in hiscase

i s

shown in Figure

9

The test c i rcu i t uses the same ar rangem ent wh ich w i l l be used a t

Kemps Creek,

I

e a valve arrester

is

connected across the valve

and the cur rent- l imi t ing reactor

A capacitor arrester is u se d to

1

1


5/6

TEST

1

2

3A

36

3C

4 A

4 6

4c

SA

58

6

7

8

9

1325

Kind of test Test Steady state perio d Mis firing current Transie nt recovery voltage Test object Remarks

characteristic

Overload

ircuit Preload

No Load Dura- Load

Load

Dura- MIS-

Misfiring

Current First Firstjump M a x D u ra . V a l v e Thyriv

Number

load cur- tion

volt.

cur- tion tiring

currenW

rising

jump

incl

vo l tage

l ion t y p e

to r in o f

volt- rent age rent angle

loop

ON/ overshoot series thyristor

age

duration OFF under l e ve ls

kV A, min kV Arm, sec *e l

k V k V k V

sec test

tes led

TSCheat -runandloss-

3520

35

. . . 4 2

7 8 35 6 0 T S C l 11 11

determination t e s t

TSCper iod ic f i r ing

est 1

10.70

3770 10

.

- . 4 2 7 2 34

60 TSC

1 7 22

TSC19kA faultcurrent 3750 lo 12,95 4iso 130

19.2kA

,2mr 23Alus 18 3 2 . 6 39 60 TSC

1

9 1 1

with subseq.blocking

with subseq.blocking 4 2ms 12Alus circuit

TSC19kA

faultcurrent

1060 3 s 5 0

3o

35so 5,2 iso 20.lkA

.4mr

29Alus8Alus 2 3 9

3 5 4

37.3 0 3 T I C 9

9

with subreq.blocking

~ i ~ f ~ ~ ~ s ~ ~ u ~ l ~ ~ ~ ~ ~ ~ t10.70 3710 10

11.96 3700

5 85 3 , 3nrr

7kA 2 9 N u s

oAlus 20 33 39 30 T S C l 9

20

T S C 3 2 k A

fau l tcurrent 2

1 0 9 0 3 6 2 0 20

13

5 3300 5 90 3 ,0 ms

2 k A

35Alus3Alus 1 8 8 29.1 39 2 3 T S C I 9

9

with subseq. blocking

TSC36kA faultcurrent 2

10.30

3550 30

12.6

3450 5 90 36'4 kA 57Nus 19.6 2 7 8 4 0 4 0 . 3 T S C I

10

10

with

subseq.

blocking 2.3ms 37Nus

'SC'gkA

fau'tcurrent 1 10.67 3770 6 10.67 3770 105 1B '6kA i2pJus 32 4 0 .3 3 7 4 20 TSC

1 9

1 1 a t p r e l o a d

TSCAC-minimumtest 1 2 . 4 636 5 .

800

- 7

6

60

TSC

1 11 11

TSC

1

TSCAC-minimumtest 1

2 5 450

S

- 560 . 7 6

60 T S C 2

11

11 T S C 2

T S R h e a t m n a n d l o s r -

1080

3720

32

.

.

15 25

I 5

60

T S R 11

11

determination tes t

TSRperiodicfiringtest 76 4020 . . .

T SR

fault

cur ren t

with

subsequentbiocking 4 10.50 3815

10

17.3

4875

c rea~ i ng i o2800~ w i t h i n 22

23.5

2 4

5

60 T S R 10 10

(dc-trapped current)

TSR AC-minimumtest

3

4 80

550,

I

6 8 7.7

6 8 60 TSR

11

1 1

15 20 15 60 T S R 5 10

Starting

with

6BOOA de-

140 ms. f inal

peak

10.5kA

Table 1: Program of operationa l tests

S R

arrester

a

arrester I

-Test circuit 1

l imi t the vo l tage a t the capaci to r bank The ar resters used are

special ly designed and adap ted to he avai lable test faci l it ies

Du r i n g h e te s t seq u en ce th e i n l e t a n d o u t l e t te mp e ra tu re o f th e

coo l ing wate r was recorded as we l l as the wate r f lo w

So

it was

possible to ver i fy the energy d iss ipation o f the thyr is tor m odule

TSC per iod ic f i r inq test : The a im o f th is test was to de mon stra te

the behaviour o f the va lve in temporary over load cond i t ions The

supp ly vo l tage was set by the t ra nsform er , so some thy r is tors

w e r e s h o rt e d o u t t o a c h i ev e t h e r e q u i re d h i g h t e s t v o l t a g e

stressing per thyr is tor leve l dur ing the t ransi t ion f rom th e o n-

sta te to the o f f -s ta te o f the va lve Precharg ing o f th e capaci to r

bank was car r ied ou t before per iod ic f i r ing o f th e va lve began

The va lve was f i red whe n the system vo l tage wave was a t

i t s

m a x i m u m B y u s i n g t h i s p r o c e d u re , c u r r e n t o s c i l l a t i o n s

depend ing on the resonance f requency o f approx

150 Hz

cou ld

be avo ided

TSC fau l t cur rent test The aqm of th is test

wa s to d e m o n s t ra te

the va lve

s

fau l t cur rent capab i l i ty as we l l as the prop er vo l tage

l im i t i n g a c t i o n o f th e SR and CC arresters

In a first stage, tests no 3A. 3 8 a n d 4 A we re e xe cu te d Th e a im o f

th e 1 9 kA te s t was to r e a ch 1 9 kA m is f ir i ng cu r re n t p e a k w i th a

tu rn -o f f d i /d t o f 20 Nps a n d a vo l ta g e j u mp ( A V ) of a b o u t 8 5 %

o f th e ma x imu m vo l ta g e Th e a im o f th e h i g h cu r re n t te s t wa s to

reach

3 2

kA peak

In test 4A. a

2 7

kA peak cur rent resu l ts f rom a h igher network

imp e d an ce Th e n e two rk d i d n o t b e h a ve l i ke a s imp le se r i es

inductance as was assumed

in

previous calculations T he sh unt

capacit ive components o f the network produced d is tor t ion o f the

mis f ir i ng cu r re n t a n d o f th e r e co very vo lta g e A t te s t 3 A . th e

vo l ta g e j u mp wa s th e re fo re l o we re d to

50%

o f t h e m a x i m u m

recovery vo l tage In add i t ion the test

3 8

wa s n o w e xe cu te d o n

the pre load c i rcu i t A h igh vo l tage jump o f about 80 % o f t h e

ma x imu m vo l ta g e wa s n o w a ch ie ve d , b u t th e ( di/dt ), ,f wa s

l o w e r e d t o 1 2 p s

The test circuit used i s shown in F igure 10 I n a d d i ti o n t o t h e

circuit as shown in Figure 9, a second power supp ly was insta l led

Afte r reach ing steady sta te therma l cond i t ions. changeover t o

th e over load c i rcu it was executed by ope n ing CB

1

and closing

CB

2

Th e n th e va lve wa s ke p t a g a in i n f i r in g co n d i t i o n fo r a fe w

seconds to recover the drop in junct ion temp eratu re occur ing

d u r i n g t h e s w i tc h in g o p e r a t i o n F i n a ll y t h e m i s f i r i n g w a s

e xe cu te d Th e ch an g eo ve r f r o m th e p re lo a d to th e o ve r l o a d te s t

c i rcu i t requ i red about 200 ms The over load c i rcu it was fed f r om a

shor t c i rcu it power t ransforme r

Th e sp ec i fi ed m is f i ri n g cu r re n t wa s o b ta i n e d b y d e la y i n g th e

f i r i n g imp u lse to h e i n s tan t wh e re th e su p p ly vo l ta g e was o f th e

p ro p e r ma g n itu d e a n d i n o p p o s i t io n to th e ca p a c i to r vo l ta g e

Preceding calcu la t ions were car r ied out w i th bot h the NETOMAC

--


6/6

326

SR

arrester

T 2

CC

arrester

-

Fiq.10: Test circu it 2

/2/ and th e EMTP program t o coordinate the tes t results for e g

di /dt and voltage jump at the end of misf i r ing wi th the requi red

values In the same way c i rcui t e lements w ere dimens ioned,

especial ly th e voltage characterist ic an d energy capa bil i ty of the

arresters

Resul ts of th is f i rs t tes t series led t o a rearrangeme nt of the tes t

c i rcui t A ne wly d imens ioned CC arrester was instal led and the

inductance a t the o verload circu it was reduced as far as possible

Wit h the redes igned tes t c i rcui t a second ser ies of tes ts was

started in ApriVMay 1989

To come c lose to th e high vol tage jum p and di /dt value, the 19

kA tes t was repeated (tes t 3C) The resul twas now a high di idt o f

27 7AJps togeth er wi th a h igh vol tage jump o f approx 24 kV

A fa ul t current of 32 kA peak was appl ied ( test 48) and f inal ly by

removing the valve reactor X2 a 36kA faul t current tes t was made

possible (test 4c) The 32 kA est

i s

depicted in Figu re 11

1 8 9 k V I Di v

6 0 XAlDir

2.0

,nr/Dt

Fiq.11: 32 kA fau lt current test

TSC

ac minimum voltaqe test: The purpose of this test was to

demonst rate the minimum ac vol tage and current requi red t

ensure the proper operat ion of the thyr is tors and aux i l iary

circuits. Due t o the low er rate d current of TSC 2, another typ e of

c ross current t ransformer was used. Therefore tw o di f feren t types

o f

TSC

modules were tes ted.

The level of minimum current was res t r ic ted by the energy

necessary o r the ope rat ion o f the thyristor electronics.

TSR heat - run and loss-determinat ion tes t :Hea t - run and loss -

deter mina t ion tests were executed wit h test circuit 3 (Figure 12).

Reactor bank X1 was used to adjust the specif ied current. A test

current of approx. 3700Armswi th a durat ion o f abou t 30 minutes

demonst rated the valve 's s teady-s tate capabi l t it y . Measurements

we re carried o ut as described for the heat-ru n test on TSC valves.

F igure 13 demonst rates the behav iour

o f t he va lve a t t u rn -o f f

MB

CB

1

net -

wo rk Test object

-/-' I

Fiq.12: Test circuit 3

(overshoo t ) as we l l as comut a t i on f rom f o rw ard t o reverse

current dur ing the on-s tate of the valve.

9.1

kVID iv

6.0

k Oiu

5.0

~ Y D W

Fiq 13 TSR hea t run test

TSR

per iod ic f i r i nq t es t Temporary over load capab i l i t y was

demonst rated by apply ing 4020 Arms to the valve The iequi red

high block ing vol tage per thyr is tor level was reached by reduc ing

the number of thyr is tor levels to 5

TSR fau lt current test: In case of misf ir ing or in case of ne two rk

faults, current waves may occur with temporary absence of zero

crossings, sometimes called dc-trapped current The aim o f this

t es t was t o demons tra te t he va l ves ' w i t hs t and ab i l i t y i n t h i s

event A compromise was necessary t o def ine the tes t values The

most severe stresswas assumed to be the blocking o f the valve at

l 0 5 0 0 A

6800 A

I 4875 A

3815A,,,

r

-

-

-

- -

loop

I

1 0 m i n 3 0 0 m s

f

Recovery voltage /

Fiq 14: Test sequen ce fo r overcu rren t test o n TSR

(shown for one valve di rec t ion)

max imum junc ti on t emper a t u re There f o re a t es t wave was

selected which shif ts the junct ion tem perature of the thyr is tors at

valve turn -of f c lose to the calculated max imum value This tes t

wave isshown in F igure 14

Figure 15 shows the special test circuit used

The comp lete test sequence

is

as follow s:

-Star t w i th operat ion on preload c i rcuit w i th 3815 Arms (10

min) to obtain s teady-s tate hyr is tor junc t ion tem perature

-

Commut a tion t o over load c i r cu i t by ope n ing

CB

1 a n d

closing

CB

2 (commu tat ion t im e approx 300ms)

Design and Operational Testing on Thryristor Module for the SVC Kemps Creeek_siemens

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Transcript of Design and Operational Testing on Thryristor Module for the SVC Kemps Creeek_siemens