Design and Material Integration for an Advanced Wafer ... · PDF fileDesign and Material...
Transcript of Design and Material Integration for an Advanced Wafer ... · PDF fileDesign and Material...
Design and Material Integration for an Advanced Wafer-Level
Chip Scale PackageGlenn Rinne, Unitive ElectronicsMike Paugh, Texas InstrumentsJim Rosson, Texas Instruments
Craig Schuckert, HD Microsystems
Outline• Introduction• Package Requirements• Motivations• Design Solutions• Performance Metrics• Conclusion
Introduction• Unitive is a Wafer-Level Packaging
foundry with operations in North Carolina and Hsinchu, Taiwan.
• Recently released a new family of packages based on PSPI for low cost, high reliability WL-CSP applications.
• This overview describes the motivations and results of this development effort.
CSP on Organic
• Differential thermal expansion between the PCB and the CSP causes compressive, tensile, and shear strains in the interconnect.
SiCTE = 2.3E-6 K-1
Substrate5E-6 < CTE < 60E-6 K-1
T=300K
T=225K
T=425K
Package Requirements
• Coarse pitch• Low bump height• Elimination of underfill• Pb-free materials• Robust connections
• Redistribution• Electrical
performance• Low system level cost• Low radiation
Contemporary WL-CSPs require:
Bump Pitch• PCB costs drive chip size down and bump
pitch up.– Fine-pitch PCB footprints for CSP mounting
increase the cost of the whole PCB.• This multiplier provides significant leverage for
packagers
Bump Pitch Examples
50 micron pitch(40E3 bumps/cm2)
(12.6E6 bumps/wafer)
250 micron pitch
75 micron pitch
Bump Height• System size drives package height down and
bump height with it. (hpkg = 1 mm -> 0.625 mm)– Superhemispheric bumps previously desired to
minimize the strain in the bumps are too tall.– Short bumps will experience plastic deformation and
fatigue damage unless a stress buffer is used.• This drove the choice of PSPI
– Wide bumps transfer too much stress into the interface
Strain Asymmetry• Shear strains are nonuniform in the package.• Localized stress is higher in the polymer than in the solder.• PI adds compliance where it is needed, at the pad edge.
Generic Stress/Strain Cycle
ShearDisplacement(Strain)
Shear Force(Stress)
Elastic
Plastic
Creep
Thermomechanics of Temperature Cycling
LowTemperature
HighTemperature
SolderTemperatureCycle
ShearDisplacement(Strain)
Shear Force(Stress)
Elastic
Plastic
Creep
Bump Material• Portable applications subject packages to
impact and bending forces, yet Pb-free solders have higher modulus and absorb less stress.– Short, stiff bumps transmit the most stress
into the package and die. – The bumps must be well anchored.
Motivations• Our customers demanded a cost effective
WL-CSP that could meet the reliability requirements of portable electronics.
• Cost is becoming more a system concern than a component concern so materials must be selected for their total impact on system cost.
Unitive’s SolutionA family of PSPI passivated, Cu redistributed, 0.5 mm pitch CSPs
Package Options• Four package styles
have been qualified, depending on application requirements.– Each of these present
their own challenges • Stress• Process compatibility
BCB and HD PropertiesProperty HD4000 BCB
Dielectric Const 3.3 (1MHz) 2.65Breakdown Field (V/cm) > 2 X 106 3 x 106
Moisture Uptake (% wt.) 2 - 3 <0.2Cure Temp. (oC) 375 250Glass Trans. Temp. (Tg ) 325 >350CTE (ppm/C) 35 52
Tensile Strength (MPa) 200 87Elongation to break 45% 9%Young’s Modulus (GPa) 3.5 2.9Stress (MPa) 34 27Adhesion (General) Excellent ExcellentProcess Compatible with Cu Yes YesEase of Process (time variables; bakes; exp; etc Excellent Excellent
BCB and HD4000 ComparedProperty BCB HD4000
Tensile Strength Poor (80GPa) Excellent (200GPa)
Yield Strain Poor (9%) Excellent (45%)
Planarization Excellent Poor
Moisture Absorption Excellent (0.2%) Good (2%)
Relative Permittivity 3.3 2.65
Planarization• IC topology can be severe.
Bump on Pad
PI
Metal Pad
PI Outside I/O Passivation Cut PI Inside I/O Passivation Cut
BSE image
Double PI/RDL/Bump
Solder Sphere
Ti/Cu/Ni UBM
PI 2PI 1
Thick PI with RDL
<15 microns of Cu
PI 2
PI 1
Cu RDL
UBM
Solder
Mounted CSP Reliability Test SuiteTest Condition Criteria Sample
Size
Temperature Cycle
–40 to +125°C, 1 cycle/hr, 15 min. ramp, 1000 cycles,
R<1.2X from R0 36
Thermal Shock –40 to +125°C, 2 cycle/hr, 5 min. ramp, 500 cycle minimum
R<1.2X from R0 36
Drop Test 0.5m, 3 axes, ε > 0.002, measured impact 10 drops,
R<1.2X from R0 5
Key Push 100 cycle/min, 20K cycles, Force = 20N, Displacement = 2.7mm,
R<1.2X from R0 5
Three-point Bend
Strain Rate 5 mm/min, 100mm span
R<1.2X from R0 (35mm Maximum)
5
Reliability Test ResultsTest Conditions Lot 1
SS/F Lot 2 SS/F
Lot 3 SS/F
Life Test
155°C, 300 Hrs. 116/0 116/0 116/0
HAST 130ºC, 85%RH, 33.5 psia, 96 Hrs.
80/0 80/0 80/0
Autoclave 121°C, 15 psia, 100%RH, 240 Hrs.
80/0 80/0 80/0
Temp Cycle 55ºC to 125ºC, 500 cycles
80/0 79/0 79/0
Board Level Temp Cycle
-40ºC to 125ºC, 1500 cycles, 5ºC/ min Ramp Rate, 12 min dwell
36/0
Three Point Bend
Strain Rate 5 mm/min., 85 mm span
8/0
Keypush 100 cycles/min, 1300µ ª d = 2.7 mm max
8/0
Drop Test 50 cm 8/0 HT Storage Life
150C/1000Hrs 45/0 45/0 45/0
HT Storage Life
170C/420Hrs 45/0 45/0 45/0
Moisture Sensitivity
Level 1 @ 240C 12/0 12/0 12/0
Life Test Results
Thermocycle Failure Mode• Fatigue cracks in the solder rather than in
the dielectric.
Conclusion• A new family of wafer-level chip scale
packages has been introduced using PSPI to provide better thermomechanical reliability.