S. Reda EN160 SP’08

Design and Implementation of VLSI Systems(EN1600)

Lecture 20: Combinational Circuit Design (2/3)

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2008

[sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’08

Let’s get rid of pMOS

Reduced the capacitance and improved the delay Increased static power consumption

[see subsection 2.5.4]

Implementing a large resistive load in CMOS is not readily available

S. Reda EN160 SP’08

2. Pseudo-nMOS circuits

• Use a pull-up transistor that is always ON• Issues:

– Ratio or relative strength– Make pMOS about ¼ effective strength of pulldown network

[see subsection 2.5.4]

S. Reda EN160 SP’08

Logical effort of pseudo-nMOS gates

• Design for unit current on output to compare with unit inverter.• pMOS fights nMOS• psuedo-nMOS is slower on the average than CMOS but it works

well for wide NOR gates

logical effort independent of number of inputs!

S. Reda EN160 SP’08

Pseudo-nMOS power

• Pseudo-nMOS draws power whenever Y = 0– Called static power P = I•VDD

– A few mA / gate * 1M gates would be a problem– This is why nMOS went extinct!

• Use pseudo-nMOS sparingly for wide NORs• Turn off pMOS when not in use

A BY

C

en

S. Reda EN160 SP’08

Ganged CMOS

• When A=B=0:• both pMOS turn on in parallel pulling the output high fast

• When both inputs are ‘1’:• both pMOS transistors turn off saving power over psuedo-nMOS

• When one is ‘1’ or one is ‘0’ then it is just like the pseudo-nMOS case

Traditional pseudo-nMOS

S. Reda EN160 SP’08

3. Cascode Voltage Switch Logic (CVSL)

• Seeks the performance of pseudo-nMOS without the static power consumption

• CVSL disadvantages:– Require input complement– NAND gate structures can be tall and slow

S. Reda EN160 SP’08

4. Pass Transistor Logic

B

B

A

F = AB

0

Problem:

• ‘1’ is not passed perfectly

• cannot the output to the input of another gate

Advantage: • just uses two transistors

S. Reda EN160 SP’08

Complementary Pass Transistor Logic (CPTL)

• Complementary data inputs and outputs are available• Very suitable for XOR realization (compare to traditional CMOS)• Interconnect overhead to route the signal and its complement

A

B

A

B

B B B B

A

B

A

B

F=AB

F=AB

F=A+B

F=A+B

B B

A

A

A

A

F=A

F=A

OR/NOR EXOR/NEXORAND/NAND

F

F

Pass-Transistor

Network

Pass-TransistorNetwork

AABB

AABB

Inverse

(a)

(b)

S. Reda EN160 SP’08

Possible solution: interface to a CMOS inverter

VDD

In

Outx

0.5m/0.25m0.5m/0.25m

1.5m/0.25m

0 0.5 1 1.5 20.0

1.0

2.0

3.0

Time [ns]

Volta

ge [V

]

xOut

In

Threshold voltage loss causes static power consumption

M 2

M 1

M n

M r

OutA

B

VDD

VDDLevel Restorer

X

A better design: full swing; reduces static power

(AKA Lean Integration with Pass Transistors - LEAP)

S. Reda EN160 SP’08

Pass Transistor Logic with transmission gates

• In pass-transistor circuits, inputs are also applied to the source/drain terminals.

• Circuits are built using transmission gates.

Problem: • Non-restoring logic. • Traditional CMOS “rejuvenates” signals

S. Reda EN160 SP’08

Restoring Pass Transistor Logic

AM2

M1

B

S

S

S F

VDD

S. Reda EN160 SP’08

Circuit Families

Static CMOSRatioed CircuitsCascode Voltage Switch LogicPass-transistor Circuits Dynamic Circuits